1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2017 Phytec Messtechnik GmbH
4 * Author: Wadim Egorov <w.egorov@phytec.de>
5 * Teresa Remmet <t.remmet@phytec.de>
8 #include <dt-bindings/input/input.h>
11 model = "Phytec AM335x PCM-953";
12 compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx";
15 vcc3v3: fixedregulator1 {
16 compatible = "regulator-fixed";
17 regulator-name = "vcc3v3";
18 regulator-min-microvolt = <3300000>;
19 regulator-max-microvolt = <3300000>;
23 vcc1v8: fixedregulator2 {
24 compatible = "regulator-fixed";
25 regulator-name = "vcc1v8";
26 regulator-min-microvolt = <1800000>;
27 regulator-max-microvolt = <1800000>;
32 user_leds: user-leds {
33 compatible = "gpio-leds";
34 pinctrl-names = "default";
35 pinctrl-0 = <&user_leds_pins>;
38 gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
43 gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
48 user_buttons: user-buttons {
49 compatible = "gpio-keys";
50 pinctrl-names = "default";
51 pinctrl-0 = <&user_buttons_pins>;
55 linux,code = <KEY_HOME>;
56 gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
62 linux,code = <KEY_MENU>;
63 gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
71 user_buttons_pins: pinmux-user-buttons-pins {
72 pinctrl-single,pins = <
73 AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* emu0.gpio3_7 */
74 AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* emu1.gpio3_8 */
78 user_leds_pins: pinmux-user-leds-pins {
79 pinctrl-single,pins = <
80 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn1.gpio1_30 */
81 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn2.gpio1_31 */
88 dcan1_pins: pinmux-dcan1-pins {
89 pinctrl-single,pins = <
90 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart1_rxd.dcan1_tx_mux2 */
91 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLUP, MUX_MODE2) /* uart1_txd.dcan1_rx_mux2 */
97 pinctrl-names = "default";
98 pinctrl-0 = <&dcan1_pins>;
104 ethernet1_pins: ethernet1-pins {
105 pinctrl-single,pins = <
106 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
107 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
108 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
109 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
110 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
111 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
112 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
113 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
114 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
115 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
116 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
117 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
123 phy-handle = <&phy1>;
124 phy-mode = "rgmii-id";
125 ti,dual-emac-pvid = <2>;
130 phy1: ethernet-phy@2 {
136 pinctrl-names = "default";
137 pinctrl-0 = <ðernet0_pins ðernet1_pins>;
142 pinctrl-names = "default";
143 pinctrl-0 = <&cb_gpio_pins>;
145 cb_gpio_pins: pinmux-cb-gpio-pins {
146 pinctrl-single,pins = <
147 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* uart0_ctsn.gpio1_8 */
148 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* uart0_rtsn.gpio1_9 */
155 mmc1_pins: pinmux-mmc1-pins {
156 pinctrl-single,pins = <
157 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
158 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
159 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
160 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
161 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
162 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
163 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */
169 vmmc-supply = <&vcc3v3>;
171 pinctrl-names = "default";
172 pinctrl-0 = <&mmc1_pins>;
173 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
179 uart0_pins: pinmux-uart0-pins {
180 pinctrl-single,pins = <
181 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
182 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
186 uart1_pins: pinmux-uart1-pins {
187 pinctrl-single,pins = <
188 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
189 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
190 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
191 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
195 uart2_pins: pinmux-uart2-pins {
196 pinctrl-single,pins = <
197 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */
198 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */
202 uart3_pins: pinmux-uart3-pins {
203 pinctrl-single,pins = <
204 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd3.uart3_rxd */
205 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd2.uart3_txd */
211 pinctrl-names = "default";
212 pinctrl-0 = <&uart0_pins>;
217 pinctrl-names = "default";
218 pinctrl-0 = <&uart1_pins>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&uart2_pins>;
228 pinctrl-names = "default";
229 pinctrl-0 = <&uart3_pins>;