1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
5 * Copyright (C) 2013 Texas Instruments, Inc.
8 corex2_d3_fck: corex2_d3_fck {
10 compatible = "fixed-factor-clock";
11 clocks = <&corex2_fck>;
16 corex2_d5_fck: corex2_d5_fck {
18 compatible = "fixed-factor-clock";
19 clocks = <&corex2_fck>;
25 dpll5_ck: dpll5_ck@d04 {
27 compatible = "ti,omap3-dpll-clock";
28 clocks = <&sys_ck>, <&sys_ck>;
29 reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
34 dpll5_m2_ck: dpll5_m2_ck@d50 {
36 compatible = "ti,divider-clock";
40 ti,index-starts-at-one;
43 sgx_gate_fck: sgx_gate_fck@b00 {
45 compatible = "ti,composite-gate-clock";
51 core_d3_ck: core_d3_ck {
53 compatible = "fixed-factor-clock";
59 core_d4_ck: core_d4_ck {
61 compatible = "fixed-factor-clock";
67 core_d6_ck: core_d6_ck {
69 compatible = "fixed-factor-clock";
75 omap_192m_alwon_fck: omap_192m_alwon_fck {
77 compatible = "fixed-factor-clock";
78 clocks = <&dpll4_m2x2_ck>;
83 core_d2_ck: core_d2_ck {
85 compatible = "fixed-factor-clock";
91 sgx_mux_fck: sgx_mux_fck@b40 {
93 compatible = "ti,composite-mux-clock";
94 clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
100 compatible = "ti,composite-clock";
101 clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
104 sgx_ick: sgx_ick@b10 {
106 compatible = "ti,wait-gate-clock";
112 cpefuse_fck: cpefuse_fck@a08 {
114 compatible = "ti,gate-clock";
122 compatible = "ti,gate-clock";
123 clocks = <&omap_32k_fck>;
128 usbtll_fck: usbtll_fck@a08 {
130 compatible = "ti,wait-gate-clock";
131 clocks = <&dpll5_m2_ck>;
136 /* CM_ICLKEN3_CORE */
138 compatible = "ti,clksel";
141 #address-cells = <0>;
143 usbtll_ick: clock-usbtll-ick {
145 compatible = "ti,omap3-interface-clock";
146 clock-output-names = "usbtll_ick";
147 clocks = <&core_l4_ick>;
153 compatible = "ti,clksel";
156 #address-cells = <0>;
158 mmchs3_ick: clock-mmchs3-ick {
160 compatible = "ti,omap3-interface-clock";
161 clock-output-names = "mmchs3_ick";
162 clocks = <&core_l4_ick>;
168 compatible = "ti,clksel";
171 #address-cells = <0>;
173 mmchs3_fck: clock-mmchs3-fck {
175 compatible = "ti,wait-gate-clock";
176 clock-output-names = "mmchs3_fck";
177 clocks = <&core_96m_fck>;
183 compatible = "ti,clksel";
186 #address-cells = <0>;
188 dss1_alwon_fck: clock-dss1-alwon-fck-3430es2 {
190 compatible = "ti,dss-gate-clock";
191 clock-output-names = "dss1_alwon_fck_3430es2";
192 clocks = <&dpll4_m4x2_ck>;
198 dss_ick: dss_ick_3430es2@e10 {
200 compatible = "ti,omap3-dss-interface-clock";
206 usbhost_120m_fck: usbhost_120m_fck@1400 {
208 compatible = "ti,gate-clock";
209 clocks = <&dpll5_m2_ck>;
214 usbhost_48m_fck: usbhost_48m_fck@1400 {
216 compatible = "ti,dss-gate-clock";
217 clocks = <&omap_48m_fck>;
222 usbhost_ick: usbhost_ick@1410 {
224 compatible = "ti,omap3-dss-interface-clock";
232 dpll5_clkdm: dpll5_clkdm {
233 compatible = "ti,clockdomain";
234 clocks = <&dpll5_ck>;
237 sgx_clkdm: sgx_clkdm {
238 compatible = "ti,clockdomain";
242 dss_clkdm: dss_clkdm {
243 compatible = "ti,clockdomain";
244 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
245 <&dss1_alwon_fck>, <&dss_ick>;
248 core_l4_clkdm: core_l4_clkdm {
249 compatible = "ti,clockdomain";
250 clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
251 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
252 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
253 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
254 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
255 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
256 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
257 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
258 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
259 <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
260 <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>;
263 usbhost_clkdm: usbhost_clkdm {
264 compatible = "ti,clockdomain";
265 clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>,