1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP34xx/OMAP36xx clock data
5 * Copyright (C) 2013 Texas Instruments, Inc.
9 compatible = "ti,clksel";
14 ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 {
16 compatible = "ti,composite-no-wait-gate-clock";
17 clock-output-names = "ssi_ssr_gate_fck_3430es2";
18 clocks = <&corex2_fck>;
24 compatible = "ti,clksel";
29 ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 {
31 compatible = "ti,composite-divider-clock";
32 clock-output-names = "ssi_ssr_div_fck_3430es2";
33 clocks = <&corex2_fck>;
35 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
39 ssi_ssr_fck: ssi_ssr_fck_3430es2 {
41 compatible = "ti,composite-clock";
42 clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
45 ssi_sst_fck: ssi_sst_fck_3430es2 {
47 compatible = "fixed-factor-clock";
48 clocks = <&ssi_ssr_fck>;
54 compatible = "ti,clksel";
59 hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2 {
61 compatible = "ti,omap3-hsotgusb-interface-clock";
62 clock-output-names = "hsotgusb_ick_3430es2";
63 clocks = <&core_l3_ick>;
67 ssi_ick: clock-ssi-ick-3430es2 {
69 compatible = "ti,omap3-ssi-interface-clock";
70 clock-output-names = "ssi_ick_3430es2";
71 clocks = <&ssi_l4_ick>;
76 ssi_l4_ick: ssi_l4_ick {
78 compatible = "fixed-factor-clock";
85 compatible = "ti,clksel";
90 usim_gate_fck: clock-usim-gate-fck {
92 compatible = "ti,composite-gate-clock";
93 clock-output-names = "usim_gate_fck";
94 clocks = <&omap_96m_fck>;
99 sys_d2_ck: sys_d2_ck {
101 compatible = "fixed-factor-clock";
107 omap_96m_d2_fck: omap_96m_d2_fck {
109 compatible = "fixed-factor-clock";
110 clocks = <&omap_96m_fck>;
115 omap_96m_d4_fck: omap_96m_d4_fck {
117 compatible = "fixed-factor-clock";
118 clocks = <&omap_96m_fck>;
123 omap_96m_d8_fck: omap_96m_d8_fck {
125 compatible = "fixed-factor-clock";
126 clocks = <&omap_96m_fck>;
131 omap_96m_d10_fck: omap_96m_d10_fck {
133 compatible = "fixed-factor-clock";
134 clocks = <&omap_96m_fck>;
139 dpll5_m2_d4_ck: dpll5_m2_d4_ck {
141 compatible = "fixed-factor-clock";
142 clocks = <&dpll5_m2_ck>;
147 dpll5_m2_d8_ck: dpll5_m2_d8_ck {
149 compatible = "fixed-factor-clock";
150 clocks = <&dpll5_m2_ck>;
155 dpll5_m2_d16_ck: dpll5_m2_d16_ck {
157 compatible = "fixed-factor-clock";
158 clocks = <&dpll5_m2_ck>;
163 dpll5_m2_d20_ck: dpll5_m2_d20_ck {
165 compatible = "fixed-factor-clock";
166 clocks = <&dpll5_m2_ck>;
172 compatible = "ti,clksel";
175 #address-cells = <0>;
177 usim_mux_fck: clock-usim-mux-fck {
179 compatible = "ti,composite-mux-clock";
180 clock-output-names = "usim_mux_fck";
181 clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
183 ti,index-starts-at-one;
189 compatible = "ti,composite-clock";
190 clocks = <&usim_gate_fck>, <&usim_mux_fck>;
194 compatible = "ti,clksel";
197 #address-cells = <0>;
199 usim_ick: clock-usim-ick {
201 compatible = "ti,omap3-interface-clock";
202 clock-output-names = "usim_ick";
203 clocks = <&wkup_l4_ick>;
210 core_l3_clkdm: core_l3_clkdm {
211 compatible = "ti,clockdomain";
212 clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
215 wkup_clkdm: wkup_clkdm {
216 compatible = "ti,clockdomain";
217 clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
218 <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
219 <&gpt1_ick>, <&usim_ick>;
222 core_l4_clkdm: core_l4_clkdm {
223 compatible = "ti,clockdomain";
224 clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
225 <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
226 <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
227 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
228 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
229 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
230 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
231 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
232 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
233 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
234 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,