1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
6 #include <dt-bindings/bus/ti-sysc.h>
7 #include <dt-bindings/clock/omap4.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/omap.h>
11 #include <dt-bindings/clock/omap4.h>
14 compatible = "ti,omap4430", "ti,omap4";
15 interrupt-parent = <&wakeupgen>;
43 compatible = "arm,cortex-a9";
45 next-level-cache = <&L2>;
48 clocks = <&dpll_mpu_ck>;
51 clock-latency = <300000>; /* From omap-cpufreq driver */
54 compatible = "arm,cortex-a9";
56 next-level-cache = <&L2>;
62 * Needed early by omap4_sram_init() for barrier, do not move to l3
63 * interconnect as simple-pm-bus probes at module_init() time.
65 ocmcram: sram@40304000 {
66 compatible = "mmio-sram";
67 reg = <0x40304000 0xa000>; /* 40k */
70 gic: interrupt-controller@48241000 {
71 compatible = "arm,cortex-a9-gic";
73 #interrupt-cells = <3>;
74 reg = <0x48241000 0x1000>,
76 interrupt-parent = <&gic>;
79 L2: cache-controller@48242000 {
80 compatible = "arm,pl310-cache";
81 reg = <0x48242000 0x1000>;
86 local-timer@48240600 {
87 compatible = "arm,cortex-a9-twd-timer";
88 clocks = <&mpu_periphclk>;
89 reg = <0x48240600 0x20>;
90 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
91 interrupt-parent = <&gic>;
94 wakeupgen: interrupt-controller@48281000 {
95 compatible = "ti,omap4-wugen-mpu";
97 #interrupt-cells = <3>;
98 reg = <0x48281000 0x1000>;
99 interrupt-parent = <&gic>;
103 * XXX: Use a flat representation of the OMAP4 interconnect.
104 * The real OMAP interconnect network is quite complex.
105 * Since it will not bring real advantage to represent that in DT for
106 * the moment, just use a fake OCP bus entry to represent the whole bus
110 compatible = "simple-pm-bus";
111 power-domains = <&prm_l4per>;
112 clocks = <&l3_1_clkctrl OMAP4_L3_MAIN_1_CLKCTRL 0>,
113 <&l3_2_clkctrl OMAP4_L3_MAIN_2_CLKCTRL 0>,
114 <&l3_instr_clkctrl OMAP4_L3_MAIN_3_CLKCTRL 0>;
115 #address-cells = <1>;
120 compatible = "ti,omap4-l3-noc";
121 reg = <0x44000000 0x1000>,
124 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
128 l4_wkup: interconnect@4a300000 {
131 l4_cfg: interconnect@4a000000 {
134 l4_per: interconnect@48000000 {
137 target-module@48210000 {
138 compatible = "ti,sysc-omap4-simple", "ti,sysc";
139 power-domains = <&prm_mpu>;
140 clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
142 #address-cells = <1>;
144 ranges = <0 0x48210000 0x1f0000>;
147 compatible = "ti,omap4-mpu";
152 l4_abe: interconnect@40100000 {
155 target-module@50000000 {
156 compatible = "ti,sysc-omap2", "ti,sysc";
157 reg = <0x50000000 4>,
160 reg-names = "rev", "sysc", "syss";
161 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
166 clocks = <&l3_2_clkctrl OMAP4_GPMC_CLKCTRL 0>;
168 #address-cells = <1>;
170 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
171 <0x00000000 0x00000000 0x40000000>; /* data */
173 gpmc: gpmc@50000000 {
174 compatible = "ti,omap4430-gpmc";
175 reg = <0x50000000 0x1000>;
176 #address-cells = <2>;
178 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
182 gpmc,num-waitpins = <4>;
183 clocks = <&l3_div_ck>;
185 interrupt-controller;
186 #interrupt-cells = <2>;
192 target-module@52000000 {
193 compatible = "ti,sysc-omap4", "ti,sysc";
194 reg = <0x52000000 0x4>,
196 reg-names = "rev", "sysc";
197 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
198 ti,sysc-midle = <SYSC_IDLE_FORCE>,
201 <SYSC_IDLE_SMART_WKUP>;
202 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
205 <SYSC_IDLE_SMART_WKUP>;
206 ti,sysc-delay-us = <2>;
207 power-domains = <&prm_cam>;
208 clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
210 #address-cells = <1>;
212 ranges = <0 0x52000000 0x1000000>;
214 /* No child device binding, driver in staging */
218 * Note that 4430 needs cross trigger interface (CTI) supported
219 * before we can configure the interrupts. This means sampling
220 * events are not supported for pmu. Note that 4460 does not use
221 * CTI, see also 4460.dtsi.
223 target-module@54000000 {
224 compatible = "ti,sysc-omap4-simple", "ti,sysc";
225 power-domains = <&prm_emu>;
226 clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 0>;
228 #address-cells = <1>;
230 ranges = <0x0 0x54000000 0x1000000>;
233 compatible = "arm,cortex-a9-pmu";
237 target-module@55082000 {
238 compatible = "ti,sysc-omap2", "ti,sysc";
239 reg = <0x55082000 0x4>,
242 reg-names = "rev", "sysc", "syss";
243 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
246 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
247 SYSC_OMAP2_SOFTRESET |
248 SYSC_OMAP2_AUTOIDLE)>;
249 clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
251 resets = <&prm_core 2>;
252 reset-names = "rstctrl";
253 ranges = <0x0 0x55082000 0x100>;
255 #address-cells = <1>;
258 compatible = "ti,omap4-iommu";
260 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
262 ti,iommu-bus-err-back;
266 target-module@4012c000 {
267 compatible = "ti,sysc-omap4", "ti,sysc";
268 reg = <0x4012c000 0x4>,
270 reg-names = "rev", "sysc";
271 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
272 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
275 <SYSC_IDLE_SMART_WKUP>;
276 clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
278 #address-cells = <1>;
280 ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
281 <0x4902c000 0x4902c000 0x1000>; /* L3 */
283 /* No child device binding or driver in mainline */
286 target-module@4e000000 {
287 compatible = "ti,sysc-omap2", "ti,sysc";
288 reg = <0x4e000000 0x4>,
290 reg-names = "rev", "sysc";
291 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
294 ranges = <0x0 0x4e000000 0x2000000>;
296 #address-cells = <1>;
299 compatible = "ti,omap4-dmm";
301 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
305 target-module@4c000000 {
306 compatible = "ti,sysc-omap4-simple", "ti,sysc";
307 reg = <0x4c000000 0x4>;
309 clocks = <&l3_emif_clkctrl OMAP4_EMIF1_CLKCTRL 0>;
312 #address-cells = <1>;
314 ranges = <0x0 0x4c000000 0x1000000>;
317 compatible = "ti,emif-4d";
319 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
321 hw-caps-read-idle-ctrl;
322 hw-caps-ll-interface;
327 target-module@4d000000 {
328 compatible = "ti,sysc-omap4-simple", "ti,sysc";
329 reg = <0x4d000000 0x4>;
331 clocks = <&l3_emif_clkctrl OMAP4_EMIF2_CLKCTRL 0>;
334 #address-cells = <1>;
336 ranges = <0x0 0x4d000000 0x1000000>;
339 compatible = "ti,emif-4d";
341 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
343 hw-caps-read-idle-ctrl;
344 hw-caps-ll-interface;
350 compatible = "ti,omap4-dsp";
351 ti,bootreg = <&scm_conf 0x304 0>;
353 resets = <&prm_tesla 0>;
354 clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
355 firmware-name = "omap4-dsp-fw.xe64T";
356 mboxes = <&mailbox &mbox_dsp>;
361 compatible = "ti,omap4-ipu";
362 reg = <0x55020000 0x10000>;
365 resets = <&prm_core 0>, <&prm_core 1>;
366 clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
367 firmware-name = "omap4-ipu-fw.xem3";
368 mboxes = <&mailbox &mbox_ipu>;
372 aes1_target: target-module@4b501000 {
373 compatible = "ti,sysc-omap2", "ti,sysc";
374 reg = <0x4b501080 0x4>,
377 reg-names = "rev", "sysc", "syss";
378 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
379 SYSC_OMAP2_AUTOIDLE)>;
380 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
383 <SYSC_IDLE_SMART_WKUP>;
385 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
386 clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
388 #address-cells = <1>;
390 ranges = <0x0 0x4b501000 0x1000>;
393 compatible = "ti,omap4-aes";
395 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
396 dmas = <&sdma 111>, <&sdma 110>;
397 dma-names = "tx", "rx";
401 aes2_target: target-module@4b701000 {
402 compatible = "ti,sysc-omap2", "ti,sysc";
403 reg = <0x4b701080 0x4>,
406 reg-names = "rev", "sysc", "syss";
407 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
408 SYSC_OMAP2_AUTOIDLE)>;
409 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
412 <SYSC_IDLE_SMART_WKUP>;
414 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
415 clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
417 #address-cells = <1>;
419 ranges = <0x0 0x4b701000 0x1000>;
422 compatible = "ti,omap4-aes";
424 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
425 dmas = <&sdma 114>, <&sdma 113>;
426 dma-names = "tx", "rx";
430 sham_target: target-module@4b100000 {
431 compatible = "ti,sysc-omap3-sham", "ti,sysc";
432 reg = <0x4b100100 0x4>,
435 reg-names = "rev", "sysc", "syss";
436 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
437 SYSC_OMAP2_AUTOIDLE)>;
438 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
442 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
443 clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
445 #address-cells = <1>;
447 ranges = <0x0 0x4b100000 0x1000>;
450 compatible = "ti,omap4-sham";
452 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
458 abb_mpu: regulator-abb-mpu {
459 compatible = "ti,abb-v2";
460 regulator-name = "abb_mpu";
461 #address-cells = <0>;
463 ti,tranxdone-status-mask = <0x80>;
464 clocks = <&sys_clkin_ck>;
465 ti,settling-time = <50>;
466 ti,clock-cycles = <16>;
471 abb_iva: regulator-abb-iva {
472 compatible = "ti,abb-v2";
473 regulator-name = "abb_iva";
474 #address-cells = <0>;
476 ti,tranxdone-status-mask = <0x80000000>;
477 clocks = <&sys_clkin_ck>;
478 ti,settling-time = <50>;
479 ti,clock-cycles = <16>;
484 sgx_module: target-module@56000000 {
485 compatible = "ti,sysc-omap4", "ti,sysc";
486 reg = <0x5600fe00 0x4>,
488 reg-names = "rev", "sysc";
489 ti,sysc-midle = <SYSC_IDLE_FORCE>,
492 <SYSC_IDLE_SMART_WKUP>;
493 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
496 <SYSC_IDLE_SMART_WKUP>;
497 power-domains = <&prm_gfx>;
498 clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
500 #address-cells = <1>;
502 ranges = <0 0x56000000 0x2000000>;
505 * Closed source PowerVR driver, no child device
506 * binding or driver in mainline
511 * DSS is only using l3 mapping without l4 as noted in the TRM
512 * "10.1.3 DSS Register Manual" for omap4460.
514 target-module@58000000 {
515 compatible = "ti,sysc-omap2", "ti,sysc";
516 reg = <0x58000000 4>,
518 reg-names = "rev", "syss";
520 power-domains = <&prm_dss>;
521 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
522 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
523 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
524 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
525 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
526 #address-cells = <1>;
528 ranges = <0 0x58000000 0x1000000>;
531 compatible = "ti,omap4-dss";
534 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
536 #address-cells = <1>;
538 ranges = <0 0 0x1000000>;
541 compatible = "ti,sysc-omap2", "ti,sysc";
545 reg-names = "rev", "sysc", "syss";
546 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
549 ti,sysc-midle = <SYSC_IDLE_FORCE>,
552 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
553 SYSC_OMAP2_ENAWAKEUP |
554 SYSC_OMAP2_SOFTRESET |
555 SYSC_OMAP2_AUTOIDLE)>;
557 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
558 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
559 clock-names = "fck", "sys_clk";
560 #address-cells = <1>;
562 ranges = <0 0x1000 0x1000>;
565 compatible = "ti,omap4-dispc";
567 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
574 compatible = "ti,sysc-omap2", "ti,sysc";
578 reg-names = "rev", "sysc", "syss";
579 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
582 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
583 SYSC_OMAP2_AUTOIDLE)>;
585 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
586 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
587 clock-names = "fck", "sys_clk";
588 #address-cells = <1>;
590 ranges = <0 0x2000 0x1000>;
595 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
596 clock-names = "fck", "ick";
601 compatible = "ti,sysc-omap2", "ti,sysc";
604 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
605 clock-names = "sys_clk";
606 #address-cells = <1>;
608 ranges = <0 0x3000 0x1000>;
611 compatible = "ti,omap4-venc";
614 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
620 compatible = "ti,sysc-omap2", "ti,sysc";
624 reg-names = "rev", "sysc", "syss";
625 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
628 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
629 SYSC_OMAP2_ENAWAKEUP |
630 SYSC_OMAP2_SOFTRESET |
631 SYSC_OMAP2_AUTOIDLE)>;
633 #address-cells = <1>;
635 ranges = <0 0x4000 0x1000>;
638 compatible = "ti,omap4-dsi";
642 reg-names = "proto", "phy", "pll";
643 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
646 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
647 clock-names = "fck", "sys_clk";
649 #address-cells = <1>;
655 compatible = "ti,sysc-omap2", "ti,sysc";
659 reg-names = "rev", "sysc", "syss";
660 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
663 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
664 SYSC_OMAP2_ENAWAKEUP |
665 SYSC_OMAP2_SOFTRESET |
666 SYSC_OMAP2_AUTOIDLE)>;
668 #address-cells = <1>;
670 ranges = <0 0x5000 0x1000>;
673 compatible = "ti,omap4-dsi";
677 reg-names = "proto", "phy", "pll";
678 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
681 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
682 clock-names = "fck", "sys_clk";
684 #address-cells = <1>;
690 compatible = "ti,sysc-omap4", "ti,sysc";
693 reg-names = "rev", "sysc";
695 * Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP
696 * but HDMI audio will fail with them.
698 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
700 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
701 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
702 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
703 clock-names = "fck", "dss_clk";
704 #address-cells = <1>;
706 ranges = <0 0x6000 0x2000>;
709 compatible = "ti,omap4-hdmi";
714 reg-names = "wp", "pll", "phy", "core";
715 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
718 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
719 clock-names = "fck", "sys_clk";
721 dma-names = "audio_tx";
727 iva_hd_target: target-module@5a000000 {
728 compatible = "ti,sysc-omap4", "ti,sysc";
729 reg = <0x5a05a400 0x4>,
731 reg-names = "rev", "sysc";
732 ti,sysc-midle = <SYSC_IDLE_FORCE>,
735 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
738 power-domains = <&prm_ivahd>;
739 resets = <&prm_ivahd 2>;
740 reset-names = "rstctrl";
741 clocks = <&ivahd_clkctrl OMAP4_IVA_CLKCTRL 0>;
743 #address-cells = <1>;
745 ranges = <0x5a000000 0x5a000000 0x1000000>,
746 <0x5b000000 0x5b000000 0x1000000>;
749 compatible = "ti,ivahd";
755 #include "omap4-l4.dtsi"
756 #include "omap4-l4-abe.dtsi"
757 #include "omap44xx-clocks.dtsi"
761 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
763 #power-domain-cells = <0>;
767 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
770 #power-domain-cells = <0>;
774 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
776 #power-domain-cells = <0>;
779 prm_always_on_core: prm@600 {
780 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
782 #power-domain-cells = <0>;
786 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
789 #power-domain-cells = <0>;
793 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
796 #power-domain-cells = <0>;
800 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
801 reg = <0x1000 0x100>;
802 #power-domain-cells = <0>;
806 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
807 reg = <0x1100 0x100>;
808 #power-domain-cells = <0>;
812 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
813 reg = <0x1200 0x100>;
814 #power-domain-cells = <0>;
817 prm_l3init: prm@1300 {
818 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
819 reg = <0x1300 0x100>;
820 #power-domain-cells = <0>;
823 prm_l4per: prm@1400 {
824 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
825 reg = <0x1400 0x100>;
826 #power-domain-cells = <0>;
829 prm_cefuse: prm@1600 {
830 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
831 reg = <0x1600 0x100>;
832 #power-domain-cells = <0>;
836 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
837 reg = <0x1700 0x100>;
838 #power-domain-cells = <0>;
842 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
843 reg = <0x1900 0x100>;
844 #power-domain-cells = <0>;
848 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
850 #power-domain-cells = <0>;
853 prm_device: prm@1b00 {
854 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
860 /* Preferred always-on timer for clockevent */
865 assigned-clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
866 assigned-clock-parents = <&sys_32k_ck>;