src/arm64/amazon/alpine-v3.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2020, Amazon.com, Inc. or its affiliates. All Rights Reserved
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9
  10 / {
  11         model = "Amazon's Annapurna Labs Alpine v3";
  12         compatible = "amazon,al-alpine-v3";
  13
  14         interrupt-parent = <&gic>;
  15
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 cpu@0 {
  24                         device_type = "cpu";
  25                         compatible = "arm,cortex-a72";
  26                         reg = <0x0>;
  27                         enable-method = "psci";
  28                         d-cache-size = <0x8000>;
  29                         d-cache-line-size = <64>;
  30                         d-cache-sets = <256>;
  31                         i-cache-size = <0xc000>;
  32                         i-cache-line-size = <64>;
  33                         i-cache-sets = <256>;
  34                         next-level-cache = <&cluster0_l2>;
  35                 };
  36
  37                 cpu@1 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a72";
  40                         reg = <0x1>;
  41                         enable-method = "psci";
  42                         d-cache-size = <0x8000>;
  43                         d-cache-line-size = <64>;
  44                         d-cache-sets = <256>;
  45                         i-cache-size = <0xc000>;
  46                         i-cache-line-size = <64>;
  47                         i-cache-sets = <256>;
  48                         next-level-cache = <&cluster0_l2>;
  49                 };
  50
  51                 cpu@2 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a72";
  54                         reg = <0x2>;
  55                         enable-method = "psci";
  56                         d-cache-size = <0x8000>;
  57                         d-cache-line-size = <64>;
  58                         d-cache-sets = <256>;
  59                         i-cache-size = <0xc000>;
  60                         i-cache-line-size = <64>;
  61                         i-cache-sets = <256>;
  62                         next-level-cache = <&cluster0_l2>;
  63                 };
  64
  65                 cpu@3 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a72";
  68                         reg = <0x3>;
  69                         enable-method = "psci";
  70                         d-cache-size = <0x8000>;
  71                         d-cache-line-size = <64>;
  72                         d-cache-sets = <256>;
  73                         i-cache-size = <0xc000>;
  74                         i-cache-line-size = <64>;
  75                         i-cache-sets = <256>;
  76                         next-level-cache = <&cluster0_l2>;
  77                 };
  78
  79                 cpu@100 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a72";
  82                         reg = <0x100>;
  83                         enable-method = "psci";
  84                         d-cache-size = <0x8000>;
  85                         d-cache-line-size = <64>;
  86                         d-cache-sets = <256>;
  87                         i-cache-size = <0xc000>;
  88                         i-cache-line-size = <64>;
  89                         i-cache-sets = <256>;
  90                         next-level-cache = <&cluster1_l2>;
  91                 };
  92
  93                 cpu@101 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a72";
  96                         reg = <0x101>;
  97                         enable-method = "psci";
  98                         d-cache-size = <0x8000>;
  99                         d-cache-line-size = <64>;
 100                         d-cache-sets = <256>;
 101                         i-cache-size = <0xc000>;
 102                         i-cache-line-size = <64>;
 103                         i-cache-sets = <256>;
 104                         next-level-cache = <&cluster1_l2>;
 105                 };
 106
 107                 cpu@102 {
 108                         device_type = "cpu";
 109                         compatible = "arm,cortex-a72";
 110                         reg = <0x102>;
 111                         enable-method = "psci";
 112                         d-cache-size = <0x8000>;
 113                         d-cache-line-size = <64>;
 114                         d-cache-sets = <256>;
 115                         i-cache-size = <0xc000>;
 116                         i-cache-line-size = <64>;
 117                         i-cache-sets = <256>;
 118                         next-level-cache = <&cluster1_l2>;
 119                 };
 120
 121                 cpu@103 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a72";
 124                         reg = <0x103>;
 125                         enable-method = "psci";
 126                         d-cache-size = <0x8000>;
 127                         d-cache-line-size = <64>;
 128                         d-cache-sets = <256>;
 129                         i-cache-size = <0xc000>;
 130                         i-cache-line-size = <64>;
 131                         i-cache-sets = <256>;
 132                         next-level-cache = <&cluster1_l2>;
 133                 };
 134
 135                 cpu@200 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a72";
 138                         reg = <0x200>;
 139                         enable-method = "psci";
 140                         d-cache-size = <0x8000>;
 141                         d-cache-line-size = <64>;
 142                         d-cache-sets = <256>;
 143                         i-cache-size = <0xc000>;
 144                         i-cache-line-size = <64>;
 145                         i-cache-sets = <256>;
 146                         next-level-cache = <&cluster2_l2>;
 147                 };
 148
 149                 cpu@201 {
 150                         device_type = "cpu";
 151                         compatible = "arm,cortex-a72";
 152                         reg = <0x201>;
 153                         enable-method = "psci";
 154                         d-cache-size = <0x8000>;
 155                         d-cache-line-size = <64>;
 156                         d-cache-sets = <256>;
 157                         i-cache-size = <0xc000>;
 158                         i-cache-line-size = <64>;
 159                         i-cache-sets = <256>;
 160                         next-level-cache = <&cluster2_l2>;
 161                 };
 162
 163                 cpu@202 {
 164                         device_type = "cpu";
 165                         compatible = "arm,cortex-a72";
 166                         reg = <0x202>;
 167                         enable-method = "psci";
 168                         d-cache-size = <0x8000>;
 169                         d-cache-line-size = <64>;
 170                         d-cache-sets = <256>;
 171                         i-cache-size = <0xc000>;
 172                         i-cache-line-size = <64>;
 173                         i-cache-sets = <256>;
 174                         next-level-cache = <&cluster2_l2>;
 175                 };
 176
 177                 cpu@203 {
 178                         device_type = "cpu";
 179                         compatible = "arm,cortex-a72";
 180                         reg = <0x203>;
 181                         enable-method = "psci";
 182                         d-cache-size = <0x8000>;
 183                         d-cache-line-size = <64>;
 184                         d-cache-sets = <256>;
 185                         i-cache-size = <0xc000>;
 186                         i-cache-line-size = <64>;
 187                         i-cache-sets = <256>;
 188                         next-level-cache = <&cluster2_l2>;
 189                 };
 190
 191                 cpu@300 {
 192                         device_type = "cpu";
 193                         compatible = "arm,cortex-a72";
 194                         reg = <0x300>;
 195                         enable-method = "psci";
 196                         d-cache-size = <0x8000>;
 197                         d-cache-line-size = <64>;
 198                         d-cache-sets = <256>;
 199                         i-cache-size = <0xc000>;
 200                         i-cache-line-size = <64>;
 201                         i-cache-sets = <256>;
 202                         next-level-cache = <&cluster3_l2>;
 203                 };
 204
 205                 cpu@301 {
 206                         device_type = "cpu";
 207                         compatible = "arm,cortex-a72";
 208                         reg = <0x301>;
 209                         enable-method = "psci";
 210                         d-cache-size = <0x8000>;
 211                         d-cache-line-size = <64>;
 212                         d-cache-sets = <256>;
 213                         i-cache-size = <0xc000>;
 214                         i-cache-line-size = <64>;
 215                         i-cache-sets = <256>;
 216                         next-level-cache = <&cluster3_l2>;
 217                 };
 218
 219                 cpu@302 {
 220                         device_type = "cpu";
 221                         compatible = "arm,cortex-a72";
 222                         reg = <0x302>;
 223                         enable-method = "psci";
 224                         d-cache-size = <0x8000>;
 225                         d-cache-line-size = <64>;
 226                         d-cache-sets = <256>;
 227                         i-cache-size = <0xc000>;
 228                         i-cache-line-size = <64>;
 229                         i-cache-sets = <256>;
 230                         next-level-cache = <&cluster3_l2>;
 231                 };
 232
 233                 cpu@303 {
 234                         device_type = "cpu";
 235                         compatible = "arm,cortex-a72";
 236                         reg = <0x303>;
 237                         enable-method = "psci";
 238                         d-cache-size = <0x8000>;
 239                         d-cache-line-size = <64>;
 240                         d-cache-sets = <256>;
 241                         i-cache-size = <0xc000>;
 242                         i-cache-line-size = <64>;
 243                         i-cache-sets = <256>;
 244                         next-level-cache = <&cluster3_l2>;
 245                 };
 246
 247                 cluster0_l2: cache@0 {
 248                         compatible = "cache";
 249                         cache-size = <0x200000>;
 250                         cache-line-size = <64>;
 251                         cache-sets = <2048>;
 252                         cache-level = <2>;
 253                         cache-unified;
 254                 };
 255
 256                 cluster1_l2: cache@100 {
 257                         compatible = "cache";
 258                         cache-size = <0x200000>;
 259                         cache-line-size = <64>;
 260                         cache-sets = <2048>;
 261                         cache-level = <2>;
 262                         cache-unified;
 263                 };
 264
 265                 cluster2_l2: cache@200 {
 266                         compatible = "cache";
 267                         cache-size = <0x200000>;
 268                         cache-line-size = <64>;
 269                         cache-sets = <2048>;
 270                         cache-level = <2>;
 271                         cache-unified;
 272                 };
 273
 274                 cluster3_l2: cache@300 {
 275                         compatible = "cache";
 276                         cache-size = <0x200000>;
 277                         cache-line-size = <64>;
 278                         cache-sets = <2048>;
 279                         cache-level = <2>;
 280                         cache-unified;
 281                 };
 282
 283         };
 284
 285         reserved-memory {
 286                 #address-cells = <2>;
 287                 #size-cells = <2>;
 288                 ranges;
 289
 290                 secmon@0 {
 291                         reg = <0x0 0x0 0x0 0x100000>;
 292                         no-map;
 293                 };
 294         };
 295
 296         psci {
 297                 compatible = "arm,psci-0.2";
 298                 method = "smc";
 299         };
 300
 301         timer {
 302                 compatible = "arm,armv8-timer";
 303                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 304                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 305                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 306                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 307         };
 308
 309         pmu {
 310                 compatible = "arm,cortex-a72-pmu";
 311                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 312         };
 313
 314
 315         soc {
 316                 compatible = "simple-bus";
 317                 #address-cells = <2>;
 318                 #size-cells = <2>;
 319                 ranges;
 320
 321                 gic: interrupt-controller@f0000000 {
 322                         compatible = "arm,gic-v3";
 323                         #interrupt-cells = <3>;
 324                         interrupt-controller;
 325                         reg = <0x0 0xf0800000 0 0x10000>,       /* GICD */
 326                               <0x0 0xf0a00000 0 0x200000>,      /* GICR */
 327                               <0x0 0xf0000000 0 0x2000>,        /* GICC */
 328                               <0x0 0xf0010000 0 0x1000>,        /* GICH */
 329                               <0x0 0xf0020000 0 0x2000>;        /* GICV */
 330                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 331                 };
 332
 333                 pcie@fbd00000 {
 334                         compatible = "pci-host-ecam-generic";
 335                         device_type = "pci";
 336                         #size-cells = <2>;
 337                         #address-cells = <3>;
 338                         #interrupt-cells = <1>;
 339                         reg = <0x0 0xfbd00000 0x0 0x100000>;
 340                         interrupt-map-mask = <0xf800 0 0 7>;
 341                         /* 8 x legacy interrupts for SATA only */
 342                         interrupt-map = <0x4000 0 0 1 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
 343                                         <0x4800 0 0 1 &gic 0 58 IRQ_TYPE_LEVEL_HIGH>,
 344                                         <0x5000 0 0 1 &gic 0 59 IRQ_TYPE_LEVEL_HIGH>,
 345                                         <0x5800 0 0 1 &gic 0 60 IRQ_TYPE_LEVEL_HIGH>,
 346                                         <0x6000 0 0 1 &gic 0 61 IRQ_TYPE_LEVEL_HIGH>,
 347                                         <0x6800 0 0 1 &gic 0 62 IRQ_TYPE_LEVEL_HIGH>,
 348                                         <0x7000 0 0 1 &gic 0 63 IRQ_TYPE_LEVEL_HIGH>,
 349                                         <0x7800 0 0 1 &gic 0 64 IRQ_TYPE_LEVEL_HIGH>;
 350                         ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
 351                         bus-range = <0x00 0x00>;
 352                         msi-parent = <&msix>;
 353                 };
 354
 355                 msix: msix@fbe00000 {
 356                         compatible = "al,alpine-msix";
 357                         reg = <0x0 0xfbe00000 0x0 0x100000>;
 358                         interrupt-controller;
 359                         msi-controller;
 360                         al,msi-base-spi = <336>;
 361                         al,msi-num-spis = <959>;
 362                         interrupt-parent = <&gic>;
 363                 };
 364
 365                 io-fabric {
 366                         compatible = "simple-bus";
 367                         #address-cells = <1>;
 368                         #size-cells = <1>;
 369                         ranges = <0x0 0x0 0xfc000000 0x2000000>;
 370
 371                         uart0: serial@1883000 {
 372                                 compatible = "ns16550a";
 373                                 reg = <0x1883000 0x1000>;
 374                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 375                                 clock-frequency = <0>; /* Filled by firmware */
 376                                 reg-shift = <2>;
 377                                 reg-io-width = <4>;
 378                                 status = "disabled";
 379                         };
 380
 381                         uart1: serial@1884000 {
 382                                 compatible = "ns16550a";
 383                                 reg = <0x1884000 0x1000>;
 384                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 385                                 clock-frequency = <0>; /* Filled by firmware */
 386                                 reg-shift = <2>;
 387                                 reg-io-width = <4>;
 388                                 status = "disabled";
 389                         };
 390
 391                         uart2: serial@1885000 {
 392                                 compatible = "ns16550a";
 393                                 reg = <0x1885000 0x1000>;
 394                                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 395                                 clock-frequency = <0>; /* Filled by firmware */
 396                                 reg-shift = <2>;
 397                                 reg-io-width = <4>;
 398                                 status = "disabled";
 399                         };
 400
 401                         uart3: serial@1886000 {
 402                                 compatible = "ns16550a";
 403                                 reg = <0x1886000 0x1000>;
 404                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 405                                 clock-frequency = <0>; /* Filled by firmware */
 406                                 reg-shift = <2>;
 407                                 reg-io-width = <4>;
 408                                 status = "disabled";
 409                         };
 410                 };
 411         };
 412 };