src/arm64/amlogic/meson-gxbb.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2016 Andreas Färber
   4  */
   5
   6 #include "meson-gx.dtsi"
   7 #include "meson-gx-mali450.dtsi"
   8 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
   9 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
  10 #include <dt-bindings/clock/gxbb-clkc.h>
  11 #include <dt-bindings/clock/gxbb-aoclkc.h>
  12 #include <dt-bindings/reset/gxbb-aoclkc.h>
  13
  14 / {
  15         compatible = "amlogic,meson-gxbb";
  16
  17         soc {
  18                 usb0_phy: phy@c0000000 {
  19                         compatible = "amlogic,meson-gxbb-usb2-phy";
  20                         #phy-cells = <0>;
  21                         reg = <0x0 0xc0000000 0x0 0x20>;
  22                         resets = <&reset RESET_USB_OTG>;
  23                         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
  24                         clock-names = "usb_general", "usb";
  25                         status = "disabled";
  26                 };
  27
  28                 usb1_phy: phy@c0000020 {
  29                         compatible = "amlogic,meson-gxbb-usb2-phy";
  30                         #phy-cells = <0>;
  31                         reg = <0x0 0xc0000020 0x0 0x20>;
  32                         resets = <&reset RESET_USB_OTG>;
  33                         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
  34                         clock-names = "usb_general", "usb";
  35                         status = "disabled";
  36                 };
  37
  38                 usb0: usb@c9000000 {
  39                         compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
  40                         reg = <0x0 0xc9000000 0x0 0x40000>;
  41                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  42                         clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
  43                         clock-names = "otg";
  44                         phys = <&usb0_phy>;
  45                         phy-names = "usb2-phy";
  46                         dr_mode = "host";
  47                         status = "disabled";
  48                 };
  49
  50                 usb1: usb@c9100000 {
  51                         compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
  52                         reg = <0x0 0xc9100000 0x0 0x40000>;
  53                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  54                         clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
  55                         clock-names = "otg";
  56                         phys = <&usb1_phy>;
  57                         phy-names = "usb2-phy";
  58                         dr_mode = "host";
  59                         status = "disabled";
  60                 };
  61         };
  62 };
  63
  64 &aiu {
  65         compatible = "amlogic,aiu-gxbb", "amlogic,aiu";
  66         clocks = <&clkc CLKID_AIU_GLUE>,
  67                  <&clkc CLKID_I2S_OUT>,
  68                  <&clkc CLKID_AOCLK_GATE>,
  69                  <&clkc CLKID_CTS_AMCLK>,
  70                  <&clkc CLKID_MIXER_IFACE>,
  71                  <&clkc CLKID_IEC958>,
  72                  <&clkc CLKID_IEC958_GATE>,
  73                  <&clkc CLKID_CTS_MCLK_I958>,
  74                  <&clkc CLKID_CTS_I958>;
  75         clock-names = "pclk",
  76                       "i2s_pclk",
  77                       "i2s_aoclk",
  78                       "i2s_mclk",
  79                       "i2s_mixer",
  80                       "spdif_pclk",
  81                       "spdif_aoclk",
  82                       "spdif_mclk",
  83                       "spdif_mclk_sel";
  84         resets = <&reset RESET_AIU>;
  85 };
  86
  87 &aobus {
  88         pinctrl_aobus: pinctrl@14 {
  89                 compatible = "amlogic,meson-gxbb-aobus-pinctrl";
  90                 #address-cells = <2>;
  91                 #size-cells = <2>;
  92                 ranges;
  93
  94                 gpio_ao: bank@14 {
  95                         reg = <0x0 0x00014 0x0 0x8>,
  96                               <0x0 0x0002c 0x0 0x4>,
  97                               <0x0 0x00024 0x0 0x8>;
  98                         reg-names = "mux", "pull", "gpio";
  99                         gpio-controller;
 100                         #gpio-cells = <2>;
 101                         gpio-ranges = <&pinctrl_aobus 0 0 14>;
 102                 };
 103
 104                 uart_ao_a_pins: uart_ao_a {
 105                         mux {
 106                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 107                                 function = "uart_ao";
 108                                 bias-disable;
 109                         };
 110                 };
 111
 112                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
 113                         mux {
 114                                 groups = "uart_cts_ao_a",
 115                                        "uart_rts_ao_a";
 116                                 function = "uart_ao";
 117                                 bias-disable;
 118                         };
 119                 };
 120
 121                 uart_ao_b_pins: uart_ao_b {
 122                         mux {
 123                                 groups = "uart_tx_ao_b", "uart_rx_ao_b";
 124                                 function = "uart_ao_b";
 125                                 bias-disable;
 126                         };
 127                 };
 128
 129                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
 130                         mux {
 131                                 groups = "uart_cts_ao_b",
 132                                        "uart_rts_ao_b";
 133                                 function = "uart_ao_b";
 134                                 bias-disable;
 135                         };
 136                 };
 137
 138                 remote_input_ao_pins: remote_input_ao {
 139                         mux {
 140                                 groups = "remote_input_ao";
 141                                 function = "remote_input_ao";
 142                                 bias-disable;
 143                         };
 144                 };
 145
 146                 i2c_ao_pins: i2c_ao {
 147                         mux {
 148                                 groups = "i2c_sck_ao",
 149                                        "i2c_sda_ao";
 150                                 function = "i2c_ao";
 151                                 bias-disable;
 152                         };
 153                 };
 154
 155                 pwm_ao_a_3_pins: pwm_ao_a_3 {
 156                         mux {
 157                                 groups = "pwm_ao_a_3";
 158                                 function = "pwm_ao_a_3";
 159                                 bias-disable;
 160                         };
 161                 };
 162
 163                 pwm_ao_a_6_pins: pwm_ao_a_6 {
 164                         mux {
 165                                 groups = "pwm_ao_a_6";
 166                                 function = "pwm_ao_a_6";
 167                                 bias-disable;
 168                         };
 169                 };
 170
 171                 pwm_ao_a_12_pins: pwm_ao_a_12 {
 172                         mux {
 173                                 groups = "pwm_ao_a_12";
 174                                 function = "pwm_ao_a_12";
 175                                 bias-disable;
 176                         };
 177                 };
 178
 179                 pwm_ao_b_pins: pwm_ao_b {
 180                         mux {
 181                                 groups = "pwm_ao_b";
 182                                 function = "pwm_ao_b";
 183                                 bias-disable;
 184                         };
 185                 };
 186
 187                 i2s_am_clk_pins: i2s_am_clk {
 188                         mux {
 189                                 groups = "i2s_am_clk";
 190                                 function = "i2s_out_ao";
 191                                 bias-disable;
 192                         };
 193                 };
 194
 195                 i2s_out_ao_clk_pins: i2s_out_ao_clk {
 196                         mux {
 197                                 groups = "i2s_out_ao_clk";
 198                                 function = "i2s_out_ao";
 199                                 bias-disable;
 200                         };
 201                 };
 202
 203                 i2s_out_lr_clk_pins: i2s_out_lr_clk {
 204                         mux {
 205                                 groups = "i2s_out_lr_clk";
 206                                 function = "i2s_out_ao";
 207                                 bias-disable;
 208                         };
 209                 };
 210
 211                 i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
 212                         mux {
 213                                 groups = "i2s_out_ch01_ao";
 214                                 function = "i2s_out_ao";
 215                                 bias-disable;
 216                         };
 217                 };
 218
 219                 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
 220                         mux {
 221                                 groups = "i2s_out_ch23_ao";
 222                                 function = "i2s_out_ao";
 223                                 bias-disable;
 224                         };
 225                 };
 226
 227                 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
 228                         mux {
 229                                 groups = "i2s_out_ch45_ao";
 230                                 function = "i2s_out_ao";
 231                                 bias-disable;
 232                         };
 233                 };
 234
 235                 spdif_out_ao_6_pins: spdif_out_ao_6 {
 236                         mux {
 237                                 groups = "spdif_out_ao_6";
 238                                 function = "spdif_out_ao";
 239                         };
 240                 };
 241
 242                 spdif_out_ao_13_pins: spdif_out_ao_13 {
 243                         mux {
 244                                 groups = "spdif_out_ao_13";
 245                                 function = "spdif_out_ao";
 246                                 bias-disable;
 247                         };
 248                 };
 249
 250                 ao_cec_pins: ao_cec {
 251                         mux {
 252                                 groups = "ao_cec";
 253                                 function = "cec_ao";
 254                                 bias-disable;
 255                         };
 256                 };
 257
 258                 ee_cec_pins: ee_cec {
 259                         mux {
 260                                 groups = "ee_cec";
 261                                 function = "cec_ao";
 262                                 bias-disable;
 263                         };
 264                 };
 265         };
 266 };
 267
 268 &cbus {
 269         spifc: spi@8c80 {
 270                 compatible = "amlogic,meson-gxbb-spifc";
 271                 reg = <0x0 0x08c80 0x0 0x80>;
 272                 #address-cells = <1>;
 273                 #size-cells = <0>;
 274                 clocks = <&clkc CLKID_SPI>;
 275                 status = "disabled";
 276         };
 277 };
 278
 279 &cec_AO {
 280         clocks = <&clkc_AO CLKID_AO_CEC_32K>;
 281         clock-names = "core";
 282 };
 283
 284 &clkc_AO {
 285         compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
 286         clocks = <&xtal>, <&clkc CLKID_CLK81>;
 287         clock-names = "xtal", "mpeg-clk";
 288 };
 289
 290 &efuse {
 291         clocks = <&clkc CLKID_EFUSE>;
 292 };
 293
 294 &ethmac {
 295         clocks = <&clkc CLKID_ETH>,
 296                  <&clkc CLKID_FCLK_DIV2>,
 297                  <&clkc CLKID_MPLL2>,
 298                  <&clkc CLKID_FCLK_DIV2>;
 299         clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
 300 };
 301
 302 &gpio_intc {
 303         compatible = "amlogic,meson-gxbb-gpio-intc",
 304                      "amlogic,meson-gpio-intc";
 305         status = "okay";
 306 };
 307
 308 &hdmi_tx {
 309         compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
 310         resets = <&reset RESET_HDMITX_CAPB3>,
 311                  <&reset RESET_HDMI_SYSTEM_RESET>,
 312                  <&reset RESET_HDMI_TX>;
 313         reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
 314         clocks = <&clkc CLKID_HDMI_PCLK>,
 315                  <&clkc CLKID_CLK81>,
 316                  <&clkc CLKID_GCLK_VENCI_INT0>;
 317         clock-names = "isfr", "iahb", "venci";
 318 };
 319
 320 &sysctrl {
 321         clkc: clock-controller {
 322                 compatible = "amlogic,gxbb-clkc";
 323                 #clock-cells = <1>;
 324                 clocks = <&xtal>;
 325                 clock-names = "xtal";
 326         };
 327 };
 328
 329 &hwrng {
 330         clocks = <&clkc CLKID_RNG0>;
 331         clock-names = "core";
 332 };
 333
 334 &i2c_A {
 335         clocks = <&clkc CLKID_I2C>;
 336 };
 337
 338 &i2c_AO {
 339         clocks = <&clkc CLKID_AO_I2C>;
 340 };
 341
 342 &i2c_B {
 343         clocks = <&clkc CLKID_I2C>;
 344 };
 345
 346 &i2c_C {
 347         clocks = <&clkc CLKID_I2C>;
 348 };
 349
 350 &mali {
 351         compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
 352
 353         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
 354         clock-names = "bus", "core";
 355
 356         assigned-clocks = <&clkc CLKID_GP0_PLL>;
 357         assigned-clock-rates = <744000000>;
 358 };
 359
 360 &periphs {
 361         pinctrl_periphs: pinctrl@4b0 {
 362                 compatible = "amlogic,meson-gxbb-periphs-pinctrl";
 363                 #address-cells = <2>;
 364                 #size-cells = <2>;
 365                 ranges;
 366
 367                 gpio: bank@4b0 {
 368                         reg = <0x0 0x004b0 0x0 0x28>,
 369                               <0x0 0x004e8 0x0 0x14>,
 370                               <0x0 0x00520 0x0 0x14>,
 371                               <0x0 0x00430 0x0 0x40>;
 372                         reg-names = "mux", "pull", "pull-enable", "gpio";
 373                         gpio-controller;
 374                         #gpio-cells = <2>;
 375                         gpio-ranges = <&pinctrl_periphs 0 0 119>;
 376                 };
 377
 378                 emmc_pins: emmc {
 379                         mux-0 {
 380                                 groups = "emmc_nand_d07",
 381                                        "emmc_cmd";
 382                                 function = "emmc";
 383                                 bias-pull-up;
 384                         };
 385
 386                         mux-1 {
 387                                 groups = "emmc_clk";
 388                                 function = "emmc";
 389                                 bias-disable;
 390                         };
 391                 };
 392
 393                 emmc_ds_pins: emmc-ds {
 394                         mux {
 395                                 groups = "emmc_ds";
 396                                 function = "emmc";
 397                                 bias-pull-down;
 398                         };
 399                 };
 400
 401                 emmc_clk_gate_pins: emmc_clk_gate {
 402                         mux {
 403                                 groups = "BOOT_8";
 404                                 function = "gpio_periphs";
 405                                 bias-pull-down;
 406                         };
 407                 };
 408
 409                 nor_pins: nor {
 410                         mux {
 411                                 groups = "nor_d",
 412                                        "nor_q",
 413                                        "nor_c",
 414                                        "nor_cs";
 415                                 function = "nor";
 416                                 bias-disable;
 417                         };
 418                 };
 419
 420                 spi_pins: spi-pins {
 421                         mux {
 422                                 groups = "spi_miso",
 423                                         "spi_mosi",
 424                                         "spi_sclk";
 425                                 function = "spi";
 426                                 bias-disable;
 427                         };
 428                 };
 429
 430                 spi_idle_high_pins: spi-idle-high-pins {
 431                         mux {
 432                                 groups = "spi_sclk";
 433                                 bias-pull-up;
 434                         };
 435                 };
 436
 437                 spi_idle_low_pins: spi-idle-low-pins {
 438                         mux {
 439                                 groups = "spi_sclk";
 440                                 bias-pull-down;
 441                         };
 442                 };
 443
 444                 spi_ss0_pins: spi-ss0 {
 445                         mux {
 446                                 groups = "spi_ss0";
 447                                 function = "spi";
 448                                 bias-disable;
 449                         };
 450                 };
 451
 452                 sdcard_pins: sdcard {
 453                         mux-0 {
 454                                 groups = "sdcard_d0",
 455                                        "sdcard_d1",
 456                                        "sdcard_d2",
 457                                        "sdcard_d3",
 458                                        "sdcard_cmd";
 459                                 function = "sdcard";
 460                                 bias-pull-up;
 461                         };
 462
 463                         mux-1 {
 464                                 groups = "sdcard_clk";
 465                                 function = "sdcard";
 466                                 bias-disable;
 467                         };
 468                 };
 469
 470                 sdcard_clk_gate_pins: sdcard_clk_gate {
 471                         mux {
 472                                 groups = "CARD_2";
 473                                 function = "gpio_periphs";
 474                                 bias-pull-down;
 475                         };
 476                 };
 477
 478                 sdio_pins: sdio {
 479                         mux-0 {
 480                                 groups = "sdio_d0",
 481                                        "sdio_d1",
 482                                        "sdio_d2",
 483                                        "sdio_d3",
 484                                        "sdio_cmd";
 485                                 function = "sdio";
 486                                 bias-pull-up;
 487                         };
 488
 489                         mux-1 {
 490                                 groups = "sdio_clk";
 491                                 function = "sdio";
 492                                 bias-disable;
 493                         };
 494                 };
 495
 496                 sdio_clk_gate_pins: sdio_clk_gate {
 497                         mux {
 498                                 groups = "GPIOX_4";
 499                                 function = "gpio_periphs";
 500                                 bias-pull-down;
 501                         };
 502                 };
 503
 504                 sdio_irq_pins: sdio_irq {
 505                         mux {
 506                                 groups = "sdio_irq";
 507                                 function = "sdio";
 508                                 bias-disable;
 509                         };
 510                 };
 511
 512                 uart_a_pins: uart_a {
 513                         mux {
 514                                 groups = "uart_tx_a",
 515                                        "uart_rx_a";
 516                                 function = "uart_a";
 517                                 bias-disable;
 518                         };
 519                 };
 520
 521                 uart_a_cts_rts_pins: uart_a_cts_rts {
 522                         mux {
 523                                 groups = "uart_cts_a",
 524                                        "uart_rts_a";
 525                                 function = "uart_a";
 526                                 bias-disable;
 527                         };
 528                 };
 529
 530                 uart_b_pins: uart_b {
 531                         mux {
 532                                 groups = "uart_tx_b",
 533                                        "uart_rx_b";
 534                                 function = "uart_b";
 535                                 bias-disable;
 536                         };
 537                 };
 538
 539                 uart_b_cts_rts_pins: uart_b_cts_rts {
 540                         mux {
 541                                 groups = "uart_cts_b",
 542                                        "uart_rts_b";
 543                                 function = "uart_b";
 544                                 bias-disable;
 545                         };
 546                 };
 547
 548                 uart_c_pins: uart_c {
 549                         mux {
 550                                 groups = "uart_tx_c",
 551                                        "uart_rx_c";
 552                                 function = "uart_c";
 553                                 bias-disable;
 554                         };
 555                 };
 556
 557                 uart_c_cts_rts_pins: uart_c_cts_rts {
 558                         mux {
 559                                 groups = "uart_cts_c",
 560                                        "uart_rts_c";
 561                                 function = "uart_c";
 562                                 bias-disable;
 563                         };
 564                 };
 565
 566                 i2c_a_pins: i2c_a {
 567                         mux {
 568                                 groups = "i2c_sck_a",
 569                                        "i2c_sda_a";
 570                                 function = "i2c_a";
 571                                 bias-disable;
 572                         };
 573                 };
 574
 575                 i2c_b_pins: i2c_b {
 576                         mux {
 577                                 groups = "i2c_sck_b",
 578                                        "i2c_sda_b";
 579                                 function = "i2c_b";
 580                                 bias-disable;
 581                         };
 582                 };
 583
 584                 i2c_c_pins: i2c_c {
 585                         mux {
 586                                 groups = "i2c_sck_c",
 587                                        "i2c_sda_c";
 588                                 function = "i2c_c";
 589                                 bias-disable;
 590                         };
 591                 };
 592
 593                 eth_rgmii_pins: eth-rgmii {
 594                         mux {
 595                                 groups = "eth_mdio",
 596                                        "eth_mdc",
 597                                        "eth_clk_rx_clk",
 598                                        "eth_rx_dv",
 599                                        "eth_rxd0",
 600                                        "eth_rxd1",
 601                                        "eth_rxd2",
 602                                        "eth_rxd3",
 603                                        "eth_rgmii_tx_clk",
 604                                        "eth_tx_en",
 605                                        "eth_txd0",
 606                                        "eth_txd1",
 607                                        "eth_txd2",
 608                                        "eth_txd3";
 609                                 function = "eth";
 610                                 bias-disable;
 611                         };
 612                 };
 613
 614                 eth_rmii_pins: eth-rmii {
 615                         mux {
 616                                 groups = "eth_mdio",
 617                                        "eth_mdc",
 618                                        "eth_clk_rx_clk",
 619                                        "eth_rx_dv",
 620                                        "eth_rxd0",
 621                                        "eth_rxd1",
 622                                        "eth_tx_en",
 623                                        "eth_txd0",
 624                                        "eth_txd1";
 625                                 function = "eth";
 626                                 bias-disable;
 627                         };
 628                 };
 629
 630                 pwm_a_x_pins: pwm_a_x {
 631                         mux {
 632                                 groups = "pwm_a_x";
 633                                 function = "pwm_a_x";
 634                                 bias-disable;
 635                         };
 636                 };
 637
 638                 pwm_a_y_pins: pwm_a_y {
 639                         mux {
 640                                 groups = "pwm_a_y";
 641                                 function = "pwm_a_y";
 642                                 bias-disable;
 643                         };
 644                 };
 645
 646                 pwm_b_pins: pwm_b {
 647                         mux {
 648                                 groups = "pwm_b";
 649                                 function = "pwm_b";
 650                                 bias-disable;
 651                         };
 652                 };
 653
 654                 pwm_d_pins: pwm_d {
 655                         mux {
 656                                 groups = "pwm_d";
 657                                 function = "pwm_d";
 658                                 bias-disable;
 659                         };
 660                 };
 661
 662                 pwm_e_pins: pwm_e {
 663                         mux {
 664                                 groups = "pwm_e";
 665                                 function = "pwm_e";
 666                                 bias-disable;
 667                         };
 668                 };
 669
 670                 pwm_f_x_pins: pwm_f_x {
 671                         mux {
 672                                 groups = "pwm_f_x";
 673                                 function = "pwm_f_x";
 674                                 bias-disable;
 675                         };
 676                 };
 677
 678                 pwm_f_y_pins: pwm_f_y {
 679                         mux {
 680                                 groups = "pwm_f_y";
 681                                 function = "pwm_f_y";
 682                                 bias-disable;
 683                         };
 684                 };
 685
 686                 hdmi_hpd_pins: hdmi_hpd {
 687                         mux {
 688                                 groups = "hdmi_hpd";
 689                                 function = "hdmi_hpd";
 690                                 bias-disable;
 691                         };
 692                 };
 693
 694                 hdmi_i2c_pins: hdmi_i2c {
 695                         mux {
 696                                 groups = "hdmi_sda", "hdmi_scl";
 697                                 function = "hdmi_i2c";
 698                                 bias-disable;
 699                         };
 700                 };
 701
 702                 i2sout_ch23_y_pins: i2sout_ch23_y {
 703                         mux {
 704                                 groups = "i2sout_ch23_y";
 705                                 function = "i2s_out";
 706                                 bias-disable;
 707                         };
 708                 };
 709
 710                 i2sout_ch45_y_pins: i2sout_ch45_y {
 711                         mux {
 712                                 groups = "i2sout_ch45_y";
 713                                 function = "i2s_out";
 714                                 bias-disable;
 715                         };
 716                 };
 717
 718                 i2sout_ch67_y_pins: i2sout_ch67_y {
 719                         mux {
 720                                 groups = "i2sout_ch67_y";
 721                                 function = "i2s_out";
 722                                 bias-disable;
 723                         };
 724                 };
 725
 726                 spdif_out_y_pins: spdif_out_y {
 727                         mux {
 728                                 groups = "spdif_out_y";
 729                                 function = "spdif_out";
 730                                 bias-disable;
 731                         };
 732                 };
 733         };
 734 };
 735
 736 &pwrc {
 737         resets = <&reset RESET_VIU>,
 738                  <&reset RESET_VENC>,
 739                  <&reset RESET_VCBUS>,
 740                  <&reset RESET_BT656>,
 741                  <&reset RESET_DVIN_RESET>,
 742                  <&reset RESET_RDMA>,
 743                  <&reset RESET_VENCI>,
 744                  <&reset RESET_VENCP>,
 745                  <&reset RESET_VDAC>,
 746                  <&reset RESET_VDI6>,
 747                  <&reset RESET_VENCL>,
 748                  <&reset RESET_VID_LOCK>;
 749         reset-names = "viu", "venc", "vcbus", "bt656",
 750                       "dvin", "rdma", "venci", "vencp",
 751                       "vdac", "vdi6", "vencl", "vid_lock";
 752         clocks = <&clkc CLKID_VPU>,
 753                  <&clkc CLKID_VAPB>;
 754         clock-names = "vpu", "vapb";
 755         /*
 756          * VPU clocking is provided by two identical clock paths
 757          * VPU_0 and VPU_1 muxed to a single clock by a glitch
 758          * free mux to safely change frequency while running.
 759          * Same for VAPB but with a final gate after the glitch free mux.
 760          */
 761         assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
 762                           <&clkc CLKID_VPU_0>,
 763                           <&clkc CLKID_VPU>, /* Glitch free mux */
 764                           <&clkc CLKID_VAPB_0_SEL>,
 765                           <&clkc CLKID_VAPB_0>,
 766                           <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
 767         assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
 768                                  <0>, /* Do Nothing */
 769                                  <&clkc CLKID_VPU_0>,
 770                                  <&clkc CLKID_FCLK_DIV4>,
 771                                  <0>, /* Do Nothing */
 772                                  <&clkc CLKID_VAPB_0>;
 773         assigned-clock-rates = <0>, /* Do Nothing */
 774                                <666666666>,
 775                                <0>, /* Do Nothing */
 776                                <0>, /* Do Nothing */
 777                                <250000000>,
 778                                <0>; /* Do Nothing */
 779 };
 780
 781 &saradc {
 782         compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
 783         clocks = <&xtal>,
 784                  <&clkc CLKID_SAR_ADC>,
 785                  <&clkc CLKID_SAR_ADC_CLK>,
 786                  <&clkc CLKID_SAR_ADC_SEL>;
 787         clock-names = "clkin", "core", "adc_clk", "adc_sel";
 788 };
 789
 790 &sd_emmc_a {
 791         clocks = <&clkc CLKID_SD_EMMC_A>,
 792                  <&clkc CLKID_SD_EMMC_A_CLK0>,
 793                  <&clkc CLKID_FCLK_DIV2>;
 794         clock-names = "core", "clkin0", "clkin1";
 795         resets = <&reset RESET_SD_EMMC_A>;
 796 };
 797
 798 &sd_emmc_b {
 799         clocks = <&clkc CLKID_SD_EMMC_B>,
 800                  <&clkc CLKID_SD_EMMC_B_CLK0>,
 801                  <&clkc CLKID_FCLK_DIV2>;
 802         clock-names = "core", "clkin0", "clkin1";
 803         resets = <&reset RESET_SD_EMMC_B>;
 804 };
 805
 806 &sd_emmc_c {
 807         clocks = <&clkc CLKID_SD_EMMC_C>,
 808                  <&clkc CLKID_SD_EMMC_C_CLK0>,
 809                  <&clkc CLKID_FCLK_DIV2>;
 810         clock-names = "core", "clkin0", "clkin1";
 811         resets = <&reset RESET_SD_EMMC_C>;
 812 };
 813
 814 &simplefb_hdmi {
 815         clocks = <&clkc CLKID_HDMI_PCLK>,
 816                  <&clkc CLKID_CLK81>,
 817                  <&clkc CLKID_GCLK_VENCI_INT0>;
 818 };
 819
 820 &spicc {
 821         clocks = <&clkc CLKID_SPICC>;
 822         clock-names = "core";
 823         resets = <&reset RESET_PERIPHS_SPICC>;
 824         num-cs = <1>;
 825 };
 826
 827 &spifc {
 828         clocks = <&clkc CLKID_SPI>;
 829 };
 830
 831 &uart_A {
 832         clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
 833         clock-names = "xtal", "pclk", "baud";
 834 };
 835
 836 &uart_AO {
 837         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
 838         clock-names = "xtal", "pclk", "baud";
 839 };
 840
 841 &uart_AO_B {
 842         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
 843         clock-names = "xtal", "pclk", "baud";
 844 };
 845
 846 &uart_B {
 847         clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
 848         clock-names = "xtal", "pclk", "baud";
 849 };
 850
 851 &uart_C {
 852         clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
 853         clock-names = "xtal", "pclk", "baud";
 854 };
 855
 856 &vpu {
 857         compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
 858         power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
 859 };
 860
 861 &vdec {
 862         compatible = "amlogic,gxbb-vdec", "amlogic,gx-vdec";
 863         clocks = <&clkc CLKID_DOS_PARSER>,
 864                  <&clkc CLKID_DOS>,
 865                  <&clkc CLKID_VDEC_1>,
 866                  <&clkc CLKID_VDEC_HEVC>;
 867         clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
 868         resets = <&reset RESET_PARSER>;
 869         reset-names = "esparser";
 870 };