src/arm64/apm/apm-shadowcat.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
   4  *
   5  * Copyright (C) 2015, Applied Micro Circuits Corporation
   6  */
   7
   8 / {
   9         compatible = "apm,xgene-shadowcat";
  10         interrupt-parent = <&gic>;
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13
  14         cpus {
  15                 #address-cells = <2>;
  16                 #size-cells = <0>;
  17
  18                 cpu@0 {
  19                         device_type = "cpu";
  20                         compatible = "apm,strega";
  21                         reg = <0x0 0x000>;
  22                         enable-method = "spin-table";
  23                         cpu-release-addr = <0x1 0x0000fff8>;
  24                         next-level-cache = <&xgene_L2_0>;
  25                         #clock-cells = <1>;
  26                         clocks = <&pmd0clk 0>;
  27                 };
  28                 cpu@1 {
  29                         device_type = "cpu";
  30                         compatible = "apm,strega";
  31                         reg = <0x0 0x001>;
  32                         enable-method = "spin-table";
  33                         cpu-release-addr = <0x1 0x0000fff8>;
  34                         next-level-cache = <&xgene_L2_0>;
  35                         #clock-cells = <1>;
  36                         clocks = <&pmd0clk 0>;
  37                 };
  38                 cpu@100 {
  39                         device_type = "cpu";
  40                         compatible = "apm,strega";
  41                         reg = <0x0 0x100>;
  42                         enable-method = "spin-table";
  43                         cpu-release-addr = <0x1 0x0000fff8>;
  44                         next-level-cache = <&xgene_L2_1>;
  45                         #clock-cells = <1>;
  46                         clocks = <&pmd1clk 0>;
  47                 };
  48                 cpu@101 {
  49                         device_type = "cpu";
  50                         compatible = "apm,strega";
  51                         reg = <0x0 0x101>;
  52                         enable-method = "spin-table";
  53                         cpu-release-addr = <0x1 0x0000fff8>;
  54                         next-level-cache = <&xgene_L2_1>;
  55                         #clock-cells = <1>;
  56                         clocks = <&pmd1clk 0>;
  57                 };
  58                 cpu@200 {
  59                         device_type = "cpu";
  60                         compatible = "apm,strega";
  61                         reg = <0x0 0x200>;
  62                         enable-method = "spin-table";
  63                         cpu-release-addr = <0x1 0x0000fff8>;
  64                         next-level-cache = <&xgene_L2_2>;
  65                         #clock-cells = <1>;
  66                         clocks = <&pmd2clk 0>;
  67                 };
  68                 cpu@201 {
  69                         device_type = "cpu";
  70                         compatible = "apm,strega";
  71                         reg = <0x0 0x201>;
  72                         enable-method = "spin-table";
  73                         cpu-release-addr = <0x1 0x0000fff8>;
  74                         next-level-cache = <&xgene_L2_2>;
  75                         #clock-cells = <1>;
  76                         clocks = <&pmd2clk 0>;
  77                 };
  78                 cpu@300 {
  79                         device_type = "cpu";
  80                         compatible = "apm,strega";
  81                         reg = <0x0 0x300>;
  82                         enable-method = "spin-table";
  83                         cpu-release-addr = <0x1 0x0000fff8>;
  84                         next-level-cache = <&xgene_L2_3>;
  85                         #clock-cells = <1>;
  86                         clocks = <&pmd3clk 0>;
  87                 };
  88                 cpu@301 {
  89                         device_type = "cpu";
  90                         compatible = "apm,strega";
  91                         reg = <0x0 0x301>;
  92                         enable-method = "spin-table";
  93                         cpu-release-addr = <0x1 0x0000fff8>;
  94                         next-level-cache = <&xgene_L2_3>;
  95                         #clock-cells = <1>;
  96                         clocks = <&pmd3clk 0>;
  97                 };
  98                 xgene_L2_0: l2-cache-0 {
  99                         compatible = "cache";
 100                         cache-level = <2>;
 101                         cache-unified;
 102                 };
 103                 xgene_L2_1: l2-cache-1 {
 104                         compatible = "cache";
 105                         cache-level = <2>;
 106                         cache-unified;
 107                 };
 108                 xgene_L2_2: l2-cache-2 {
 109                         compatible = "cache";
 110                         cache-level = <2>;
 111                         cache-unified;
 112                 };
 113                 xgene_L2_3: l2-cache-3 {
 114                         compatible = "cache";
 115                         cache-level = <2>;
 116                         cache-unified;
 117                 };
 118         };
 119
 120         gic: interrupt-controller@78090000 {
 121                 compatible = "arm,cortex-a15-gic";
 122                 #interrupt-cells = <3>;
 123                 #address-cells = <2>;
 124                 #size-cells = <2>;
 125                 interrupt-controller;
 126                 interrupts = <1 9 0xf04>;       /* GIC Maintenence IRQ */
 127                 ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */
 128                 reg = <0x0 0x78090000 0x0 0x10000>,     /* GIC Dist */
 129                       <0x0 0x780a0000 0x0 0x20000>,     /* GIC CPU */
 130                       <0x0 0x780c0000 0x0 0x10000>,     /* GIC VCPU Control */
 131                       <0x0 0x780e0000 0x0 0x20000>;     /* GIC VCPU */
 132                 v2m0: v2m@0 {
 133                         compatible = "arm,gic-v2m-frame";
 134                         msi-controller;
 135                         reg = <0x0 0x0 0x0 0x1000>;
 136                 };
 137                 v2m1: v2m@10000 {
 138                         compatible = "arm,gic-v2m-frame";
 139                         msi-controller;
 140                         reg = <0x0 0x10000 0x0 0x1000>;
 141                 };
 142                 v2m2: v2m@20000 {
 143                         compatible = "arm,gic-v2m-frame";
 144                         msi-controller;
 145                         reg = <0x0 0x20000 0x0 0x1000>;
 146                 };
 147                 v2m3: v2m@30000 {
 148                         compatible = "arm,gic-v2m-frame";
 149                         msi-controller;
 150                         reg = <0x0 0x30000 0x0 0x1000>;
 151                 };
 152                 v2m4: v2m@40000 {
 153                         compatible = "arm,gic-v2m-frame";
 154                         msi-controller;
 155                         reg = <0x0 0x40000 0x0 0x1000>;
 156                 };
 157                 v2m5: v2m@50000 {
 158                         compatible = "arm,gic-v2m-frame";
 159                         msi-controller;
 160                         reg = <0x0 0x50000 0x0 0x1000>;
 161                 };
 162                 v2m6: v2m@60000 {
 163                         compatible = "arm,gic-v2m-frame";
 164                         msi-controller;
 165                         reg = <0x0 0x60000 0x0 0x1000>;
 166                 };
 167                 v2m7: v2m@70000 {
 168                         compatible = "arm,gic-v2m-frame";
 169                         msi-controller;
 170                         reg = <0x0 0x70000 0x0 0x1000>;
 171                 };
 172                 v2m8: v2m@80000 {
 173                         compatible = "arm,gic-v2m-frame";
 174                         msi-controller;
 175                         reg = <0x0 0x80000 0x0 0x1000>;
 176                 };
 177                 v2m9: v2m@90000 {
 178                         compatible = "arm,gic-v2m-frame";
 179                         msi-controller;
 180                         reg = <0x0 0x90000 0x0 0x1000>;
 181                 };
 182                 v2m10: v2m@a0000 {
 183                         compatible = "arm,gic-v2m-frame";
 184                         msi-controller;
 185                         reg = <0x0 0xa0000 0x0 0x1000>;
 186                 };
 187                 v2m11: v2m@b0000 {
 188                         compatible = "arm,gic-v2m-frame";
 189                         msi-controller;
 190                         reg = <0x0 0xb0000 0x0 0x1000>;
 191                 };
 192                 v2m12: v2m@c0000 {
 193                         compatible = "arm,gic-v2m-frame";
 194                         msi-controller;
 195                         reg = <0x0 0xc0000 0x0 0x1000>;
 196                 };
 197                 v2m13: v2m@d0000 {
 198                         compatible = "arm,gic-v2m-frame";
 199                         msi-controller;
 200                         reg = <0x0 0xd0000 0x0 0x1000>;
 201                 };
 202                 v2m14: v2m@e0000 {
 203                         compatible = "arm,gic-v2m-frame";
 204                         msi-controller;
 205                         reg = <0x0 0xe0000 0x0 0x1000>;
 206                 };
 207                 v2m15: v2m@f0000 {
 208                         compatible = "arm,gic-v2m-frame";
 209                         msi-controller;
 210                         reg = <0x0 0xf0000 0x0 0x1000>;
 211                 };
 212         };
 213
 214         pmu {
 215                 compatible = "arm,armv8-pmuv3";
 216                 interrupts = <1 12 0xff04>;
 217         };
 218
 219         timer {
 220                 compatible = "arm,armv8-timer";
 221                 interrupts = <1 0 0xff08>,      /* Secure Phys IRQ */
 222                              <1 13 0xff08>,     /* Non-secure Phys IRQ */
 223                              <1 14 0xff08>,     /* Virt IRQ */
 224                              <1 15 0xff08>;     /* Hyp IRQ */
 225                 clock-frequency = <50000000>;
 226         };
 227
 228         soc {
 229                 compatible = "simple-bus";
 230                 #address-cells = <2>;
 231                 #size-cells = <2>;
 232                 ranges;
 233
 234                 clocks {
 235                         #address-cells = <2>;
 236                         #size-cells = <2>;
 237                         ranges;
 238
 239                         refclk: refclk {
 240                                 compatible = "fixed-clock";
 241                                 #clock-cells = <1>;
 242                                 clock-frequency = <100000000>;
 243                                 clock-output-names = "refclk";
 244                         };
 245
 246                         pmdpll: pmdpll@170000f0 {
 247                                 compatible = "apm,xgene-pcppll-v2-clock";
 248                                 #clock-cells = <1>;
 249                                 clocks = <&refclk 0>;
 250                                 reg = <0x0 0x170000f0 0x0 0x10>;
 251                                 clock-output-names = "pmdpll";
 252                         };
 253
 254                         pmd0clk: pmd0clk@7e200200 {
 255                                 compatible = "apm,xgene-pmd-clock";
 256                                 #clock-cells = <1>;
 257                                 clocks = <&pmdpll 0>;
 258                                 reg = <0x0 0x7e200200 0x0 0x10>;
 259                                 clock-output-names = "pmd0clk";
 260                         };
 261
 262                         pmd1clk: pmd1clk@7e200210 {
 263                                 compatible = "apm,xgene-pmd-clock";
 264                                 #clock-cells = <1>;
 265                                 clocks = <&pmdpll 0>;
 266                                 reg = <0x0 0x7e200210 0x0 0x10>;
 267                                 clock-output-names = "pmd1clk";
 268                         };
 269
 270                         pmd2clk: pmd2clk@7e200220 {
 271                                 compatible = "apm,xgene-pmd-clock";
 272                                 #clock-cells = <1>;
 273                                 clocks = <&pmdpll 0>;
 274                                 reg = <0x0 0x7e200220 0x0 0x10>;
 275                                 clock-output-names = "pmd2clk";
 276                         };
 277
 278                         pmd3clk: pmd3clk@7e200230 {
 279                                 compatible = "apm,xgene-pmd-clock";
 280                                 #clock-cells = <1>;
 281                                 clocks = <&pmdpll 0>;
 282                                 reg = <0x0 0x7e200230 0x0 0x10>;
 283                                 clock-output-names = "pmd3clk";
 284                         };
 285
 286                         socpll: socpll@17000120 {
 287                                 compatible = "apm,xgene-socpll-v2-clock";
 288                                 #clock-cells = <1>;
 289                                 clocks = <&refclk 0>;
 290                                 reg = <0x0 0x17000120 0x0 0x1000>;
 291                                 clock-output-names = "socpll";
 292                         };
 293
 294                         socplldiv2: socplldiv2  {
 295                                 compatible = "fixed-factor-clock";
 296                                 #clock-cells = <1>;
 297                                 clocks = <&socpll 0>;
 298                                 clock-mult = <1>;
 299                                 clock-div = <2>;
 300                                 clock-output-names = "socplldiv2";
 301                         };
 302
 303                         ahbclk: ahbclk@17000000 {
 304                                 compatible = "apm,xgene-device-clock";
 305                                 #clock-cells = <1>;
 306                                 clocks = <&socplldiv2 0>;
 307                                 reg = <0x0 0x17000000 0x0 0x2000>;
 308                                 reg-names = "div-reg";
 309                                 divider-offset = <0x164>;
 310                                 divider-width = <0x5>;
 311                                 divider-shift = <0x0>;
 312                                 clock-output-names = "ahbclk";
 313                         };
 314
 315                         sbapbclk: sbapbclk@1704c000 {
 316                                 compatible = "apm,xgene-device-clock";
 317                                 #clock-cells = <1>;
 318                                 clocks = <&ahbclk 0>;
 319                                 reg = <0x0 0x1704c000 0x0 0x2000>;
 320                                 reg-names = "div-reg";
 321                                 divider-offset = <0x10>;
 322                                 divider-width = <0x2>;
 323                                 divider-shift = <0x0>;
 324                                 clock-output-names = "sbapbclk";
 325                         };
 326
 327                         sdioclk: sdioclk@1f2ac000 {
 328                                 compatible = "apm,xgene-device-clock";
 329                                 #clock-cells = <1>;
 330                                 clocks = <&socplldiv2 0>;
 331                                 reg = <0x0 0x1f2ac000 0x0 0x1000
 332                                         0x0 0x17000000 0x0 0x2000>;
 333                                 reg-names = "csr-reg", "div-reg";
 334                                 csr-offset = <0x0>;
 335                                 csr-mask = <0x2>;
 336                                 enable-offset = <0x8>;
 337                                 enable-mask = <0x2>;
 338                                 divider-offset = <0x178>;
 339                                 divider-width = <0x8>;
 340                                 divider-shift = <0x0>;
 341                                 clock-output-names = "sdioclk";
 342                         };
 343
 344                         pcie0clk: pcie0clk@1f2bc000 {
 345                                 compatible = "apm,xgene-device-clock";
 346                                 #clock-cells = <1>;
 347                                 clocks = <&socplldiv2 0>;
 348                                 reg = <0x0 0x1f2bc000 0x0 0x1000>;
 349                                 reg-names = "csr-reg";
 350                                 clock-output-names = "pcie0clk";
 351                         };
 352
 353                         pcie1clk: pcie1clk@1f2cc000 {
 354                                 compatible = "apm,xgene-device-clock";
 355                                 #clock-cells = <1>;
 356                                 clocks = <&socplldiv2 0>;
 357                                 reg = <0x0 0x1f2cc000 0x0 0x1000>;
 358                                 reg-names = "csr-reg";
 359                                 clock-output-names = "pcie1clk";
 360                         };
 361
 362                         xge0clk: xge0clk@1f61c000 {
 363                                 compatible = "apm,xgene-device-clock";
 364                                 #clock-cells = <1>;
 365                                 clocks = <&socplldiv2 0>;
 366                                 reg = <0x0 0x1f61c000 0x0 0x1000>;
 367                                 reg-names = "csr-reg";
 368                                 enable-mask = <0x3>;
 369                                 csr-mask = <0x3>;
 370                                 clock-output-names = "xge0clk";
 371                         };
 372
 373                         xge1clk: xge1clk@1f62c000 {
 374                                 compatible = "apm,xgene-device-clock";
 375                                 #clock-cells = <1>;
 376                                 clocks = <&socplldiv2 0>;
 377                                 reg = <0x0 0x1f62c000 0x0 0x1000>;
 378                                 reg-names = "csr-reg";
 379                                 enable-mask = <0x3>;
 380                                 csr-mask = <0x3>;
 381                                 clock-output-names = "xge1clk";
 382                         };
 383
 384                         rngpkaclk: rngpkaclk@17000000 {
 385                                 compatible = "apm,xgene-device-clock";
 386                                 #clock-cells = <1>;
 387                                 clocks = <&socplldiv2 0>;
 388                                 reg = <0x0 0x17000000 0x0 0x2000>;
 389                                 reg-names = "csr-reg";
 390                                 csr-offset = <0xc>;
 391                                 csr-mask = <0x10>;
 392                                 enable-offset = <0x10>;
 393                                 enable-mask = <0x10>;
 394                                 clock-output-names = "rngpkaclk";
 395                         };
 396
 397                         i2c4clk: i2c4clk@1704c000 {
 398                                 compatible = "apm,xgene-device-clock";
 399                                 #clock-cells = <1>;
 400                                 clocks = <&sbapbclk 0>;
 401                                 reg = <0x0 0x1704c000 0x0 0x1000>;
 402                                 reg-names = "csr-reg";
 403                                 csr-offset = <0x0>;
 404                                 csr-mask = <0x40>;
 405                                 enable-offset = <0x8>;
 406                                 enable-mask = <0x40>;
 407                                 clock-output-names = "i2c4clk";
 408                         };
 409                 };
 410
 411                 scu: system-clk-controller@17000000 {
 412                         compatible = "apm,xgene-scu","syscon";
 413                         reg = <0x0 0x17000000 0x0 0x400>;
 414                 };
 415
 416                 reboot: reboot@17000014 {
 417                         compatible = "syscon-reboot";
 418                         regmap = <&scu>;
 419                         offset = <0x14>;
 420                         mask = <0x1>;
 421                 };
 422
 423                 csw: csw@7e200000 {
 424                         compatible = "apm,xgene-csw", "syscon";
 425                         reg = <0x0 0x7e200000 0x0 0x1000>;
 426                 };
 427
 428                 mcba: mcba@7e700000 {
 429                         compatible = "apm,xgene-mcb", "syscon";
 430                         reg = <0x0 0x7e700000 0x0 0x1000>;
 431                 };
 432
 433                 mcbb: mcbb@7e720000 {
 434                         compatible = "apm,xgene-mcb", "syscon";
 435                         reg = <0x0 0x7e720000 0x0 0x1000>;
 436                 };
 437
 438                 efuse: efuse@1054a000 {
 439                         compatible = "apm,xgene-efuse", "syscon";
 440                         reg = <0x0 0x1054a000 0x0 0x20>;
 441                 };
 442
 443                 edac@78800000 {
 444                         compatible = "apm,xgene-edac";
 445                         #address-cells = <2>;
 446                         #size-cells = <2>;
 447                         ranges;
 448                         regmap-csw = <&csw>;
 449                         regmap-mcba = <&mcba>;
 450                         regmap-mcbb = <&mcbb>;
 451                         regmap-efuse = <&efuse>;
 452                         reg = <0x0 0x78800000 0x0 0x100>;
 453                         interrupts = <0x0 0x20 0x4>,
 454                                      <0x0 0x21 0x4>,
 455                                      <0x0 0x27 0x4>;
 456
 457                         edacmc@7e800000 {
 458                                 compatible = "apm,xgene-edac-mc";
 459                                 reg = <0x0 0x7e800000 0x0 0x1000>;
 460                                 memory-controller = <0>;
 461                         };
 462
 463                         edacmc@7e840000 {
 464                                 compatible = "apm,xgene-edac-mc";
 465                                 reg = <0x0 0x7e840000 0x0 0x1000>;
 466                                 memory-controller = <1>;
 467                         };
 468
 469                         edacmc@7e880000 {
 470                                 compatible = "apm,xgene-edac-mc";
 471                                 reg = <0x0 0x7e880000 0x0 0x1000>;
 472                                 memory-controller = <2>;
 473                         };
 474
 475                         edacmc@7e8c0000 {
 476                                 compatible = "apm,xgene-edac-mc";
 477                                 reg = <0x0 0x7e8c0000 0x0 0x1000>;
 478                                 memory-controller = <3>;
 479                         };
 480
 481                         edacpmd@7c000000 {
 482                                 compatible = "apm,xgene-edac-pmd";
 483                                 reg = <0x0 0x7c000000 0x0 0x200000>;
 484                                 pmd-controller = <0>;
 485                         };
 486
 487                         edacpmd@7c200000 {
 488                                 compatible = "apm,xgene-edac-pmd";
 489                                 reg = <0x0 0x7c200000 0x0 0x200000>;
 490                                 pmd-controller = <1>;
 491                         };
 492
 493                         edacpmd@7c400000 {
 494                                 compatible = "apm,xgene-edac-pmd";
 495                                 reg = <0x0 0x7c400000 0x0 0x200000>;
 496                                 pmd-controller = <2>;
 497                         };
 498
 499                         edacpmd@7c600000 {
 500                                 compatible = "apm,xgene-edac-pmd";
 501                                 reg = <0x0 0x7c600000 0x0 0x200000>;
 502                                 pmd-controller = <3>;
 503                         };
 504
 505                         edacl3@7e600000 {
 506                                 compatible = "apm,xgene-edac-l3-v2";
 507                                 reg = <0x0 0x7e600000 0x0 0x1000>;
 508                         };
 509
 510                         edacsoc@7e930000 {
 511                                 compatible = "apm,xgene-edac-soc";
 512                                 reg = <0x0 0x7e930000 0x0 0x1000>;
 513                         };
 514                 };
 515
 516                 pmu: pmu@78810000 {
 517                         compatible = "apm,xgene-pmu-v2";
 518                         #address-cells = <2>;
 519                         #size-cells = <2>;
 520                         ranges;
 521                         regmap-csw = <&csw>;
 522                         regmap-mcba = <&mcba>;
 523                         regmap-mcbb = <&mcbb>;
 524                         reg = <0x0 0x78810000 0x0 0x1000>;
 525                         interrupts = <0x0 0x22 0x4>;
 526
 527                         pmul3c@7e610000 {
 528                                 compatible = "apm,xgene-pmu-l3c";
 529                                 reg = <0x0 0x7e610000 0x0 0x1000>;
 530                         };
 531
 532                         pmuiob@7e940000 {
 533                                 compatible = "apm,xgene-pmu-iob";
 534                                 reg = <0x0 0x7e940000 0x0 0x1000>;
 535                         };
 536
 537                         pmucmcb@7e710000 {
 538                                 compatible = "apm,xgene-pmu-mcb";
 539                                 reg = <0x0 0x7e710000 0x0 0x1000>;
 540                                 enable-bit-index = <0>;
 541                         };
 542
 543                         pmucmcb@7e730000 {
 544                                 compatible = "apm,xgene-pmu-mcb";
 545                                 reg = <0x0 0x7e730000 0x0 0x1000>;
 546                                 enable-bit-index = <1>;
 547                         };
 548
 549                         pmucmc@7e810000 {
 550                                 compatible = "apm,xgene-pmu-mc";
 551                                 reg = <0x0 0x7e810000 0x0 0x1000>;
 552                                 enable-bit-index = <0>;
 553                         };
 554
 555                         pmucmc@7e850000 {
 556                                 compatible = "apm,xgene-pmu-mc";
 557                                 reg = <0x0 0x7e850000 0x0 0x1000>;
 558                                 enable-bit-index = <1>;
 559                         };
 560
 561                         pmucmc@7e890000 {
 562                                 compatible = "apm,xgene-pmu-mc";
 563                                 reg = <0x0 0x7e890000 0x0 0x1000>;
 564                                 enable-bit-index = <2>;
 565                         };
 566
 567                         pmucmc@7e8d0000 {
 568                                 compatible = "apm,xgene-pmu-mc";
 569                                 reg = <0x0 0x7e8d0000 0x0 0x1000>;
 570                                 enable-bit-index = <3>;
 571                         };
 572                 };
 573
 574                 mailbox: mailbox@10540000 {
 575                         compatible = "apm,xgene-slimpro-mbox";
 576                         reg = <0x0 0x10540000 0x0 0x8000>;
 577                         #mbox-cells = <1>;
 578                         interrupts =   <0x0 0x0 0x4
 579                                         0x0 0x1 0x4
 580                                         0x0 0x2 0x4
 581                                         0x0 0x3 0x4
 582                                         0x0 0x4 0x4
 583                                         0x0 0x5 0x4
 584                                         0x0 0x6 0x4
 585                                         0x0 0x7 0x4>;
 586                 };
 587
 588                 i2cslimpro {
 589                         compatible = "apm,xgene-slimpro-i2c";
 590                         mboxes = <&mailbox 0>;
 591                 };
 592
 593                 hwmonslimpro {
 594                         compatible = "apm,xgene-slimpro-hwmon";
 595                         mboxes = <&mailbox 7>;
 596                 };
 597
 598                 serial0: serial@10600000 {
 599                         compatible = "ns16550";
 600                         reg = <0 0x10600000 0x0 0x1000>;
 601                         reg-shift = <2>;
 602                         clock-frequency = <10000000>;
 603                         interrupt-parent = <&gic>;
 604                         interrupts = <0x0 0x4c 0x4>;
 605                 };
 606
 607                 /* Node-name might need to be coded as dwusb for backward compatibility */
 608                 usb0: usb@19000000 {
 609                         status = "disabled";
 610                         compatible = "snps,dwc3";
 611                         reg = <0x0 0x19000000 0x0 0x100000>;
 612                         interrupts = <0x0 0x5d 0x4>;
 613                         dma-coherent;
 614                         dr_mode = "host";
 615                 };
 616
 617                 pcie0: pcie@1f2b0000 {
 618                         status = "disabled";
 619                         device_type = "pci";
 620                         compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
 621                         #interrupt-cells = <1>;
 622                         #size-cells = <2>;
 623                         #address-cells = <3>;
 624                         reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
 625                                 0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 626                         reg-names = "csr", "cfg";
 627                         ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000   /* io */
 628                                   0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000   /* mem */
 629                                   0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */
 630                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 631                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 632                         bus-range = <0x00 0xff>;
 633                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 634                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4
 635                                          0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4
 636                                          0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x4
 637                                          0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x4>;
 638                         dma-coherent;
 639                         clocks = <&pcie0clk 0>;
 640                         msi-parent = <&v2m0>;
 641                 };
 642
 643                 pcie1: pcie@1f2c0000 {
 644                         status = "disabled";
 645                         device_type = "pci";
 646                         compatible = "apm,xgene-pcie", "apm,xgene2-pcie";
 647                         #interrupt-cells = <1>;
 648                         #size-cells = <2>;
 649                         #address-cells = <3>;
 650                         reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */
 651                                 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 652                         reg-names = "csr", "cfg";
 653                         ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000   /* io */
 654                                   0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000   /* mem */
 655                                   0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
 656                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 657                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 658                         bus-range = <0x00 0xff>;
 659                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 660                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4
 661                                          0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4
 662                                          0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x4
 663                                          0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x4>;
 664                         dma-coherent;
 665                         clocks = <&pcie1clk 0>;
 666                         msi-parent = <&v2m0>;
 667                 };
 668
 669                 sata1: sata@1a000000 {
 670                         compatible = "apm,xgene-ahci-v2";
 671                         reg = <0x0 0x1a000000 0x0 0x1000>,
 672                               <0x0 0x1f200000 0x0 0x1000>,
 673                               <0x0 0x1f20d000 0x0 0x1000>,
 674                               <0x0 0x1f20e000 0x0 0x1000>;
 675                         interrupts = <0x0 0x5a 0x4>;
 676                         dma-coherent;
 677                 };
 678
 679                 sata2: sata@1a200000 {
 680                         compatible = "apm,xgene-ahci-v2";
 681                         reg = <0x0 0x1a200000 0x0 0x1000>,
 682                               <0x0 0x1f210000 0x0 0x1000>,
 683                               <0x0 0x1f21d000 0x0 0x1000>,
 684                               <0x0 0x1f21e000 0x0 0x1000>;
 685                         interrupts = <0x0 0x5b 0x4>;
 686                         dma-coherent;
 687                 };
 688
 689                 sata3: sata@1a400000 {
 690                         compatible = "apm,xgene-ahci-v2";
 691                         reg = <0x0 0x1a400000 0x0 0x1000>,
 692                               <0x0 0x1f220000 0x0 0x1000>,
 693                               <0x0 0x1f22d000 0x0 0x1000>,
 694                               <0x0 0x1f22e000 0x0 0x1000>;
 695                         interrupts = <0x0 0x5c 0x4>;
 696                         dma-coherent;
 697                 };
 698
 699                 mmc0: mmc@1c000000 {
 700                         compatible = "arasan,sdhci-4.9a";
 701                         reg = <0x0 0x1c000000 0x0 0x100>;
 702                         interrupts = <0x0 0x49 0x4>;
 703                         dma-coherent;
 704                         no-1-8-v;
 705                         clock-names = "clk_xin", "clk_ahb";
 706                         clocks = <&sdioclk 0>, <&ahbclk 0>;
 707                 };
 708
 709                 gfcgpio: gpio@1f63c000 {
 710                         compatible = "apm,xgene-gpio";
 711                         reg = <0x0 0x1f63c000 0x0 0x40>;
 712                         gpio-controller;
 713                         #gpio-cells = <2>;
 714                 };
 715
 716                 dwgpio: gpio@1c024000 {
 717                         compatible = "snps,dw-apb-gpio";
 718                         reg = <0x0 0x1c024000 0x0 0x1000>;
 719                         #address-cells = <1>;
 720                         #size-cells = <0>;
 721
 722                         porta: gpio-controller@0 {
 723                                 compatible = "snps,dw-apb-gpio-port";
 724                                 gpio-controller;
 725                                 #gpio-cells = <2>;
 726                                 snps,nr-gpios = <32>;
 727                                 reg = <0>;
 728                         };
 729                 };
 730
 731                 sbgpio: gpio@17001000 {
 732                         compatible = "apm,xgene-gpio-sb";
 733                         reg = <0x0 0x17001000 0x0 0x400>;
 734                         #gpio-cells = <2>;
 735                         gpio-controller;
 736                         interrupts = <0x0 0x28 0x1>,
 737                                      <0x0 0x29 0x1>,
 738                                      <0x0 0x2a 0x1>,
 739                                      <0x0 0x2b 0x1>,
 740                                      <0x0 0x2c 0x1>,
 741                                      <0x0 0x2d 0x1>,
 742                                      <0x0 0x2e 0x1>,
 743                                      <0x0 0x2f 0x1>;
 744                         interrupt-parent = <&gic>;
 745                         #interrupt-cells = <2>;
 746                         interrupt-controller;
 747                         apm,nr-gpios = <22>;
 748                         apm,nr-irqs = <8>;
 749                         apm,irq-start = <8>;
 750                 };
 751
 752                 mdio: mdio@1f610000 {
 753                         compatible = "apm,xgene-mdio-xfi";
 754                         #address-cells = <1>;
 755                         #size-cells = <0>;
 756                         reg = <0x0 0x1f610000 0x0 0xd100>;
 757                         clocks = <&xge0clk 0>;
 758                 };
 759
 760                 sgenet0: ethernet@1f610000 {
 761                         compatible = "apm,xgene2-sgenet";
 762                         status = "disabled";
 763                         reg = <0x0 0x1f610000 0x0 0xd100>,
 764                               <0x0 0x1f600000 0x0 0xd100>,
 765                               <0x0 0x20000000 0x0 0x20000>;
 766                         interrupts = <0 96 4>,
 767                                      <0 97 4>;
 768                         dma-coherent;
 769                         clocks = <&xge0clk 0>;
 770                         local-mac-address = [00 01 73 00 00 01];
 771                         phy-connection-type = "sgmii";
 772                         phy-handle = <&sgenet0phy>;
 773                 };
 774
 775                 xgenet1: ethernet@1f620000 {
 776                         compatible = "apm,xgene2-xgenet";
 777                         status = "disabled";
 778                         reg = <0x0 0x1f620000 0x0 0x10000>,
 779                               <0x0 0x1f600000 0x0 0xd100>,
 780                               <0x0 0x20000000 0x0 0x220000>;
 781                         interrupts = <0 108 4>,
 782                                      <0 109 4>,
 783                                      <0 110 4>,
 784                                      <0 111 4>,
 785                                      <0 112 4>,
 786                                      <0 113 4>,
 787                                      <0 114 4>,
 788                                      <0 115 4>;
 789                         channel = <12>;
 790                         port-id = <1>;
 791                         dma-coherent;
 792                         clocks = <&xge1clk 0>;
 793                         local-mac-address = [00 01 73 00 00 02];
 794                         phy-connection-type = "xgmii";
 795                 };
 796
 797                 rng: rng@10520000 {
 798                         compatible = "apm,xgene-rng";
 799                         reg = <0x0 0x10520000 0x0 0x100>;
 800                         interrupts = <0x0 0x41 0x4>;
 801                         clocks = <&rngpkaclk 0>;
 802                 };
 803
 804                 i2c1: i2c@10511000 {
 805                         #address-cells = <1>;
 806                         #size-cells = <0>;
 807                         compatible = "snps,designware-i2c";
 808                         reg = <0x0 0x10511000 0x0 0x1000>;
 809                         interrupts = <0 0x45 0x4>;
 810                         #clock-cells = <1>;
 811                         clocks = <&sbapbclk 0>;
 812                         bus_num = <1>;
 813                 };
 814
 815                 i2c4: i2c@10640000 {
 816                         #address-cells = <1>;
 817                         #size-cells = <0>;
 818                         compatible = "snps,designware-i2c";
 819                         reg = <0x0 0x10640000 0x0 0x1000>;
 820                         interrupts = <0 0x3a 0x4>;
 821                         clocks = <&i2c4clk 0>;
 822                         bus_num = <4>;
 823                 };
 824         };
 825 };