src/arm64/broadcom/stingray/stingray-clock.dtsi

   1 /*
   2  *  BSD LICENSE
   3  *
   4  *  Copyright(c) 2016-2017 Broadcom.  All rights reserved.
   5  *
   6  *  Redistribution and use in source and binary forms, with or without
   7  *  modification, are permitted provided that the following conditions
   8  *  are met:
   9  *
  10  *    * Redistributions of source code must retain the above copyright
  11  *      notice, this list of conditions and the following disclaimer.
  12  *    * Redistributions in binary form must reproduce the above copyright
  13  *      notice, this list of conditions and the following disclaimer in
  14  *      the documentation and/or other materials provided with the
  15  *      distribution.
  16  *    * Neither the name of Broadcom nor the names of its
  17  *      contributors may be used to endorse or promote products derived
  18  *      from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <dt-bindings/clock/bcm-sr.h>
  34
  35                 osc: oscillator {
  36                         #clock-cells = <0>;
  37                         compatible = "fixed-clock";
  38                         clock-frequency = <50000000>;
  39                 };
  40
  41                 crmu_ref25m: crmu_ref25m {
  42                         #clock-cells = <0>;
  43                         compatible = "fixed-factor-clock";
  44                         clocks = <&osc>;
  45                         clock-div = <2>;
  46                         clock-mult = <1>;
  47                 };
  48
  49                 genpll0: genpll0@1d104 {
  50                         #clock-cells = <1>;
  51                         compatible = "brcm,sr-genpll0";
  52                         reg = <0x0001d104 0x32>,
  53                               <0x0001c854 0x4>;
  54                         clocks = <&osc>;
  55                         clock-output-names = "genpll0", "clk_125m", "clk_scr",
  56                                              "clk_250", "clk_pcie_axi",
  57                                              "clk_paxc_axi_x2",
  58                                              "clk_paxc_axi";
  59                 };
  60
  61                 genpll2: genpll2@1d1ac {
  62                         #clock-cells = <1>;
  63                         compatible = "brcm,sr-genpll2";
  64                         reg = <0x0001d1ac 0x32>,
  65                               <0x0001c854 0x4>;
  66                         clocks = <&osc>;
  67                         clock-output-names = "genpll2", "clk_nic",
  68                                              "clk_ts_500_ref", "clk_125_nitro",
  69                                              "clk_chimp", "clk_nic_flash",
  70                                              "clk_fs";
  71                 };
  72
  73                 genpll3: genpll3@1d1e0 {
  74                         #clock-cells = <1>;
  75                         compatible = "brcm,sr-genpll3";
  76                         reg = <0x0001d1e0 0x32>,
  77                               <0x0001c854 0x4>;
  78                         clocks = <&osc>;
  79                         clock-output-names = "genpll3", "clk_hsls",
  80                                              "clk_sdio";
  81                 };
  82
  83                 genpll4: genpll4@1d214 {
  84                         #clock-cells = <1>;
  85                         compatible = "brcm,sr-genpll4";
  86                         reg = <0x0001d214 0x32>,
  87                               <0x0001c854 0x4>;
  88                         clocks = <&osc>;
  89                         clock-output-names = "genpll4", "clk_ccn",
  90                                              "clk_tpiu_pll", "clk_noc",
  91                                              "clk_chclk_fs4",
  92                                              "clk_bridge_fscpu";
  93                 };
  94
  95                 genpll5: genpll5@1d248 {
  96                         #clock-cells = <1>;
  97                         compatible = "brcm,sr-genpll5";
  98                         reg = <0x0001d248 0x32>,
  99                               <0x0001c870 0x4>;
 100                         clocks = <&osc>;
 101                         clock-output-names = "genpll5", "clk_fs4_hf",
 102                                              "clk_crypto_ae", "clk_raid_ae";
 103                 };
 104
 105                 lcpll0: lcpll0@1d0c4 {
 106                         #clock-cells = <1>;
 107                         compatible = "brcm,sr-lcpll0";
 108                         reg = <0x0001d0c4 0x3c>,
 109                               <0x0001c870 0x4>;
 110                         clocks = <&osc>;
 111                         clock-output-names = "lcpll0", "clk_sata_refp",
 112                                              "clk_sata_refn", "clk_sata_350",
 113                                              "clk_sata_500";
 114                 };
 115
 116                 lcpll1: lcpll1@1d138 {
 117                         #clock-cells = <1>;
 118                         compatible = "brcm,sr-lcpll1";
 119                         reg = <0x0001d138 0x3c>,
 120                               <0x0001c870 0x4>;
 121                         clocks = <&osc>;
 122                         clock-output-names = "lcpll1", "clk_wan",
 123                                              "clk_usb_ref",
 124                                              "clk_crmu_ts";
 125                 };
 126
 127                 hsls_clk: hsls_clk {
 128                         #clock-cells = <0>;
 129                         compatible = "fixed-factor-clock";
 130                         clocks = <&genpll3 1>;
 131                         clock-div = <1>;
 132                         clock-mult = <1>;
 133                 };
 134
 135                 hsls_div2_clk: hsls_div2_clk {
 136                         #clock-cells = <0>;
 137                         compatible = "fixed-factor-clock";
 138                         clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>;
 139                         clock-div = <2>;
 140                         clock-mult = <1>;
 141
 142                 };
 143
 144                 hsls_div4_clk: hsls_div4_clk {
 145                         #clock-cells = <0>;
 146                         compatible = "fixed-factor-clock";
 147                         clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>;
 148                         clock-div = <4>;
 149                         clock-mult = <1>;
 150                 };
 151
 152                 hsls_25m_clk: hsls_25m_clk {
 153                         #clock-cells = <0>;
 154                         compatible = "fixed-factor-clock";
 155                         clocks = <&crmu_ref25m>;
 156                         clock-div = <1>;
 157                         clock-mult = <1>;
 158                 };
 159
 160                 hsls_25m_div2_clk: hsls_25m_div2_clk {
 161                         #clock-cells = <0>;
 162                         compatible = "fixed-factor-clock";
 163                         clocks = <&hsls_25m_clk>;
 164                         clock-div = <2>;
 165                         clock-mult = <1>;
 166                 };
 167
 168                 sdio0_clk: sdio0_clk {
 169                         #clock-cells = <0>;
 170                         compatible = "fixed-factor-clock";
 171                         clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>;
 172                         clock-div = <1>;
 173                         clock-mult = <1>;
 174                 };
 175
 176                 sdio1_clk: sdio1_clk {
 177                         #clock-cells = <0>;
 178                         compatible = "fixed-factor-clock";
 179                         clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>;
 180                         clock-div = <1>;
 181                         clock-mult = <1>;
 182                 };