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Squashed 'dts/upstream/' changes from aaba2d45dc2a..b35b9bd1d4ee
[thirdparty/u-boot.git] / src / arm64 / freescale / fsl-ls1028a.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
4 *
5 * Copyright 2018-2020 NXP
6 *
7 * Harninder Rai <harninder.rai@nxp.com>
8 *
9 */
10
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14
15 / {
16 compatible = "fsl,ls1028a";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu0: cpu@0 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a72";
28 reg = <0x0>;
29 enable-method = "psci";
30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
31 i-cache-size = <0xc000>;
32 i-cache-line-size = <64>;
33 i-cache-sets = <256>;
34 d-cache-size = <0x8000>;
35 d-cache-line-size = <64>;
36 d-cache-sets = <256>;
37 next-level-cache = <&l2>;
38 cpu-idle-states = <&CPU_PW20>;
39 #cooling-cells = <2>;
40 };
41
42 cpu1: cpu@1 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a72";
45 reg = <0x1>;
46 enable-method = "psci";
47 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
48 i-cache-size = <0xc000>;
49 i-cache-line-size = <64>;
50 i-cache-sets = <256>;
51 d-cache-size = <0x8000>;
52 d-cache-line-size = <64>;
53 d-cache-sets = <256>;
54 next-level-cache = <&l2>;
55 cpu-idle-states = <&CPU_PW20>;
56 #cooling-cells = <2>;
57 };
58
59 l2: l2-cache {
60 compatible = "cache";
61 cache-level = <2>;
62 cache-unified;
63 cache-size = <0x100000>;
64 cache-line-size = <64>;
65 cache-sets = <1024>;
66 };
67 };
68
69 idle-states {
70 /*
71 * PSCI node is not added default, U-boot will add missing
72 * parts if it determines to use PSCI.
73 */
74 entry-method = "psci";
75
76 CPU_PW20: cpu-pw20 {
77 compatible = "arm,idle-state";
78 idle-state-name = "PW20";
79 arm,psci-suspend-param = <0x0>;
80 entry-latency-us = <2000>;
81 exit-latency-us = <2000>;
82 min-residency-us = <6000>;
83 };
84 };
85
86 rtc_clk: rtc-clk {
87 compatible = "fixed-clock";
88 #clock-cells = <0>;
89 clock-frequency = <32768>;
90 clock-output-names = "rtc_clk";
91 };
92
93 sysclk: sysclk {
94 compatible = "fixed-clock";
95 #clock-cells = <0>;
96 clock-frequency = <100000000>;
97 clock-output-names = "sysclk";
98 };
99
100 osc_27m: clock-osc-27m {
101 compatible = "fixed-clock";
102 #clock-cells = <0>;
103 clock-frequency = <27000000>;
104 clock-output-names = "phy_27m";
105 };
106
107 firmware {
108 optee: optee {
109 compatible = "linaro,optee-tz";
110 method = "smc";
111 status = "disabled";
112 };
113 };
114
115 reboot {
116 compatible = "syscon-reboot";
117 regmap = <&rst>;
118 offset = <0>;
119 mask = <0x02>;
120 };
121
122 timer {
123 compatible = "arm,armv8-timer";
124 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
125 IRQ_TYPE_LEVEL_LOW)>,
126 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
127 IRQ_TYPE_LEVEL_LOW)>,
128 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
129 IRQ_TYPE_LEVEL_LOW)>,
130 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
131 IRQ_TYPE_LEVEL_LOW)>;
132 };
133
134 pmu {
135 compatible = "arm,cortex-a72-pmu";
136 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
137 };
138
139 gic: interrupt-controller@6000000 {
140 compatible = "arm,gic-v3";
141 #address-cells = <2>;
142 #size-cells = <2>;
143 ranges;
144 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
145 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
146 #interrupt-cells = <3>;
147 interrupt-controller;
148 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
149 IRQ_TYPE_LEVEL_LOW)>;
150 its: msi-controller@6020000 {
151 compatible = "arm,gic-v3-its";
152 msi-controller;
153 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
154 };
155 };
156
157 thermal-zones {
158 ddr-controller {
159 polling-delay-passive = <1000>;
160 polling-delay = <5000>;
161 thermal-sensors = <&tmu 0>;
162
163 trips {
164 ddr-ctrler-alert {
165 temperature = <85000>;
166 hysteresis = <2000>;
167 type = "passive";
168 };
169
170 ddr-ctrler-crit {
171 temperature = <95000>;
172 hysteresis = <2000>;
173 type = "critical";
174 };
175 };
176 };
177
178 core-cluster {
179 polling-delay-passive = <1000>;
180 polling-delay = <5000>;
181 thermal-sensors = <&tmu 1>;
182
183 trips {
184 core_cluster_alert: core-cluster-alert {
185 temperature = <85000>;
186 hysteresis = <2000>;
187 type = "passive";
188 };
189
190 core_cluster_crit: core-cluster-crit {
191 temperature = <95000>;
192 hysteresis = <2000>;
193 type = "critical";
194 };
195 };
196
197 cooling-maps {
198 map0 {
199 trip = <&core_cluster_alert>;
200 cooling-device =
201 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
202 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
203 };
204 };
205 };
206 };
207
208 soc: soc {
209 compatible = "simple-bus";
210 #address-cells = <2>;
211 #size-cells = <2>;
212 ranges;
213
214 ddr: memory-controller@1080000 {
215 compatible = "fsl,qoriq-memory-controller";
216 reg = <0x0 0x1080000 0x0 0x1000>;
217 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
218 little-endian;
219 };
220
221 dcfg: syscon@1e00000 {
222 #address-cells = <1>;
223 #size-cells = <1>;
224 compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd";
225 reg = <0x0 0x1e00000 0x0 0x10000>;
226 ranges = <0x0 0x0 0x1e00000 0x10000>;
227 little-endian;
228
229 fspi_clk: clock-controller@900 {
230 compatible = "fsl,ls1028a-flexspi-clk";
231 reg = <0x900 0x4>;
232 #clock-cells = <0>;
233 clocks = <&clockgen QORIQ_CLK_HWACCEL 0>;
234 clock-output-names = "fspi_clk";
235 };
236 };
237
238 rst: syscon@1e60000 {
239 compatible = "syscon";
240 reg = <0x0 0x1e60000 0x0 0x10000>;
241 little-endian;
242 };
243
244 sfp: efuse@1e80000 {
245 compatible = "fsl,ls1028a-sfp";
246 reg = <0x0 0x1e80000 0x0 0x10000>;
247 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
248 QORIQ_CLK_PLL_DIV(4)>;
249 clock-names = "sfp";
250 #address-cells = <1>;
251 #size-cells = <1>;
252
253 ls1028a_uid: unique-id@1c {
254 reg = <0x1c 0x8>;
255 };
256 };
257
258 scfg: syscon@1fc0000 {
259 compatible = "fsl,ls1028a-scfg", "syscon";
260 reg = <0x0 0x1fc0000 0x0 0x10000>;
261 big-endian;
262 };
263
264 clockgen: clock-controller@1300000 {
265 compatible = "fsl,ls1028a-clockgen";
266 reg = <0x0 0x1300000 0x0 0xa0000>;
267 #clock-cells = <2>;
268 clocks = <&sysclk>;
269 };
270
271 i2c0: i2c@2000000 {
272 compatible = "fsl,vf610-i2c";
273 #address-cells = <1>;
274 #size-cells = <0>;
275 reg = <0x0 0x2000000 0x0 0x10000>;
276 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
278 QORIQ_CLK_PLL_DIV(4)>;
279 status = "disabled";
280 };
281
282 i2c1: i2c@2010000 {
283 compatible = "fsl,vf610-i2c";
284 #address-cells = <1>;
285 #size-cells = <0>;
286 reg = <0x0 0x2010000 0x0 0x10000>;
287 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
289 QORIQ_CLK_PLL_DIV(4)>;
290 status = "disabled";
291 };
292
293 i2c2: i2c@2020000 {
294 compatible = "fsl,vf610-i2c";
295 #address-cells = <1>;
296 #size-cells = <0>;
297 reg = <0x0 0x2020000 0x0 0x10000>;
298 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
300 QORIQ_CLK_PLL_DIV(4)>;
301 status = "disabled";
302 };
303
304 i2c3: i2c@2030000 {
305 compatible = "fsl,vf610-i2c";
306 #address-cells = <1>;
307 #size-cells = <0>;
308 reg = <0x0 0x2030000 0x0 0x10000>;
309 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
311 QORIQ_CLK_PLL_DIV(4)>;
312 status = "disabled";
313 };
314
315 i2c4: i2c@2040000 {
316 compatible = "fsl,vf610-i2c";
317 #address-cells = <1>;
318 #size-cells = <0>;
319 reg = <0x0 0x2040000 0x0 0x10000>;
320 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
322 QORIQ_CLK_PLL_DIV(4)>;
323 status = "disabled";
324 };
325
326 i2c5: i2c@2050000 {
327 compatible = "fsl,vf610-i2c";
328 #address-cells = <1>;
329 #size-cells = <0>;
330 reg = <0x0 0x2050000 0x0 0x10000>;
331 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
333 QORIQ_CLK_PLL_DIV(4)>;
334 status = "disabled";
335 };
336
337 i2c6: i2c@2060000 {
338 compatible = "fsl,vf610-i2c";
339 #address-cells = <1>;
340 #size-cells = <0>;
341 reg = <0x0 0x2060000 0x0 0x10000>;
342 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
344 QORIQ_CLK_PLL_DIV(4)>;
345 status = "disabled";
346 };
347
348 i2c7: i2c@2070000 {
349 compatible = "fsl,vf610-i2c";
350 #address-cells = <1>;
351 #size-cells = <0>;
352 reg = <0x0 0x2070000 0x0 0x10000>;
353 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
355 QORIQ_CLK_PLL_DIV(4)>;
356 status = "disabled";
357 };
358
359 fspi: spi@20c0000 {
360 compatible = "nxp,lx2160a-fspi";
361 #address-cells = <1>;
362 #size-cells = <0>;
363 reg = <0x0 0x20c0000 0x0 0x10000>,
364 <0x0 0x20000000 0x0 0x10000000>;
365 reg-names = "fspi_base", "fspi_mmap";
366 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&fspi_clk>, <&fspi_clk>;
368 clock-names = "fspi_en", "fspi";
369 status = "disabled";
370 };
371
372 dspi0: spi@2100000 {
373 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
374 #address-cells = <1>;
375 #size-cells = <0>;
376 reg = <0x0 0x2100000 0x0 0x10000>;
377 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
378 clock-names = "dspi";
379 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
380 QORIQ_CLK_PLL_DIV(2)>;
381 dmas = <&edma0 0 62>, <&edma0 0 60>;
382 dma-names = "tx", "rx";
383 spi-num-chipselects = <4>;
384 little-endian;
385 status = "disabled";
386 };
387
388 dspi1: spi@2110000 {
389 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
390 #address-cells = <1>;
391 #size-cells = <0>;
392 reg = <0x0 0x2110000 0x0 0x10000>;
393 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
394 clock-names = "dspi";
395 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
396 QORIQ_CLK_PLL_DIV(2)>;
397 dmas = <&edma0 0 58>, <&edma0 0 56>;
398 dma-names = "tx", "rx";
399 spi-num-chipselects = <4>;
400 little-endian;
401 status = "disabled";
402 };
403
404 dspi2: spi@2120000 {
405 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
406 #address-cells = <1>;
407 #size-cells = <0>;
408 reg = <0x0 0x2120000 0x0 0x10000>;
409 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
410 clock-names = "dspi";
411 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
412 QORIQ_CLK_PLL_DIV(2)>;
413 dmas = <&edma0 0 54>, <&edma0 0 2>;
414 dma-names = "tx", "rx";
415 spi-num-chipselects = <3>;
416 little-endian;
417 status = "disabled";
418 };
419
420 esdhc: mmc@2140000 {
421 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
422 reg = <0x0 0x2140000 0x0 0x10000>;
423 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
424 clock-frequency = <0>; /* fixed up by bootloader */
425 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
426 voltage-ranges = <1800 1800 3300 3300>;
427 sdhci,auto-cmd12;
428 little-endian;
429 bus-width = <4>;
430 status = "disabled";
431 };
432
433 esdhc1: mmc@2150000 {
434 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
435 reg = <0x0 0x2150000 0x0 0x10000>;
436 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
437 clock-frequency = <0>; /* fixed up by bootloader */
438 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
439 voltage-ranges = <1800 1800>;
440 sdhci,auto-cmd12;
441 non-removable;
442 little-endian;
443 bus-width = <4>;
444 status = "disabled";
445 };
446
447 can0: can@2180000 {
448 compatible = "fsl,lx2160ar1-flexcan";
449 reg = <0x0 0x2180000 0x0 0x10000>;
450 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
452 QORIQ_CLK_PLL_DIV(2)>,
453 <&clockgen QORIQ_CLK_PLATFORM_PLL
454 QORIQ_CLK_PLL_DIV(2)>;
455 clock-names = "ipg", "per";
456 status = "disabled";
457 };
458
459 can1: can@2190000 {
460 compatible = "fsl,lx2160ar1-flexcan";
461 reg = <0x0 0x2190000 0x0 0x10000>;
462 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
464 QORIQ_CLK_PLL_DIV(2)>,
465 <&clockgen QORIQ_CLK_PLATFORM_PLL
466 QORIQ_CLK_PLL_DIV(2)>;
467 clock-names = "ipg", "per";
468 status = "disabled";
469 };
470
471 duart0: serial@21c0500 {
472 compatible = "fsl,ns16550", "ns16550a";
473 reg = <0x00 0x21c0500 0x0 0x100>;
474 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
476 QORIQ_CLK_PLL_DIV(2)>;
477 status = "disabled";
478 };
479
480 duart1: serial@21c0600 {
481 compatible = "fsl,ns16550", "ns16550a";
482 reg = <0x00 0x21c0600 0x0 0x100>;
483 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
485 QORIQ_CLK_PLL_DIV(2)>;
486 status = "disabled";
487 };
488
489
490 lpuart0: serial@2260000 {
491 compatible = "fsl,ls1028a-lpuart";
492 reg = <0x0 0x2260000 0x0 0x1000>;
493 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
495 QORIQ_CLK_PLL_DIV(2)>;
496 clock-names = "ipg";
497 dma-names = "rx","tx";
498 dmas = <&edma0 1 32>,
499 <&edma0 1 33>;
500 status = "disabled";
501 };
502
503 lpuart1: serial@2270000 {
504 compatible = "fsl,ls1028a-lpuart";
505 reg = <0x0 0x2270000 0x0 0x1000>;
506 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
508 QORIQ_CLK_PLL_DIV(2)>;
509 clock-names = "ipg";
510 dma-names = "rx","tx";
511 dmas = <&edma0 1 30>,
512 <&edma0 1 31>;
513 status = "disabled";
514 };
515
516 lpuart2: serial@2280000 {
517 compatible = "fsl,ls1028a-lpuart";
518 reg = <0x0 0x2280000 0x0 0x1000>;
519 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
521 QORIQ_CLK_PLL_DIV(2)>;
522 clock-names = "ipg";
523 dma-names = "rx","tx";
524 dmas = <&edma0 1 28>,
525 <&edma0 1 29>;
526 status = "disabled";
527 };
528
529 lpuart3: serial@2290000 {
530 compatible = "fsl,ls1028a-lpuart";
531 reg = <0x0 0x2290000 0x0 0x1000>;
532 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
534 QORIQ_CLK_PLL_DIV(2)>;
535 clock-names = "ipg";
536 dma-names = "rx","tx";
537 dmas = <&edma0 1 26>,
538 <&edma0 1 27>;
539 status = "disabled";
540 };
541
542 lpuart4: serial@22a0000 {
543 compatible = "fsl,ls1028a-lpuart";
544 reg = <0x0 0x22a0000 0x0 0x1000>;
545 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
547 QORIQ_CLK_PLL_DIV(2)>;
548 clock-names = "ipg";
549 dma-names = "rx","tx";
550 dmas = <&edma0 1 24>,
551 <&edma0 1 25>;
552 status = "disabled";
553 };
554
555 lpuart5: serial@22b0000 {
556 compatible = "fsl,ls1028a-lpuart";
557 reg = <0x0 0x22b0000 0x0 0x1000>;
558 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
560 QORIQ_CLK_PLL_DIV(2)>;
561 clock-names = "ipg";
562 dma-names = "rx","tx";
563 dmas = <&edma0 1 22>,
564 <&edma0 1 23>;
565 status = "disabled";
566 };
567
568 edma0: dma-controller@22c0000 {
569 #dma-cells = <2>;
570 compatible = "fsl,ls1028a-edma", "fsl,vf610-edma";
571 reg = <0x0 0x22c0000 0x0 0x10000>,
572 <0x0 0x22d0000 0x0 0x10000>,
573 <0x0 0x22e0000 0x0 0x10000>;
574 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
576 interrupt-names = "edma-tx", "edma-err";
577 dma-channels = <32>;
578 clock-names = "dmamux0", "dmamux1";
579 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
580 QORIQ_CLK_PLL_DIV(2)>,
581 <&clockgen QORIQ_CLK_PLATFORM_PLL
582 QORIQ_CLK_PLL_DIV(2)>;
583 };
584
585 gpio1: gpio@2300000 {
586 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
587 reg = <0x0 0x2300000 0x0 0x10000>;
588 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
589 gpio-controller;
590 #gpio-cells = <2>;
591 interrupt-controller;
592 #interrupt-cells = <2>;
593 little-endian;
594 };
595
596 gpio2: gpio@2310000 {
597 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
598 reg = <0x0 0x2310000 0x0 0x10000>;
599 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
600 gpio-controller;
601 #gpio-cells = <2>;
602 interrupt-controller;
603 #interrupt-cells = <2>;
604 little-endian;
605 };
606
607 gpio3: gpio@2320000 {
608 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
609 reg = <0x0 0x2320000 0x0 0x10000>;
610 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
611 gpio-controller;
612 #gpio-cells = <2>;
613 interrupt-controller;
614 #interrupt-cells = <2>;
615 little-endian;
616 };
617
618 usb0: usb@3100000 {
619 compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
620 reg = <0x0 0x3100000 0x0 0x10000>;
621 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
622 snps,dis_rxdet_inp3_quirk;
623 snps,quirk-frame-length-adjustment = <0x20>;
624 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
625 status = "disabled";
626 };
627
628 usb1: usb@3110000 {
629 compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
630 reg = <0x0 0x3110000 0x0 0x10000>;
631 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
632 snps,dis_rxdet_inp3_quirk;
633 snps,quirk-frame-length-adjustment = <0x20>;
634 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
635 status = "disabled";
636 };
637
638 sata: sata@3200000 {
639 compatible = "fsl,ls1028a-ahci";
640 reg = <0x0 0x3200000 0x0 0x10000>,
641 <0x7 0x100520 0x0 0x4>;
642 reg-names = "ahci", "sata-ecc";
643 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
645 QORIQ_CLK_PLL_DIV(2)>;
646 status = "disabled";
647 };
648
649 pcie1: pcie@3400000 {
650 compatible = "fsl,ls1028a-pcie";
651 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
652 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
653 reg-names = "regs", "config";
654 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
655 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
656 interrupt-names = "pme", "aer";
657 #address-cells = <3>;
658 #size-cells = <2>;
659 device_type = "pci";
660 dma-coherent;
661 num-viewport = <8>;
662 bus-range = <0x0 0xff>;
663 ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */
664 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
665 msi-parent = <&its>;
666 #interrupt-cells = <1>;
667 interrupt-map-mask = <0 0 0 7>;
668 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
669 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
670 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
671 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
672 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
673 status = "disabled";
674 };
675
676 pcie_ep1: pcie-ep@3400000 {
677 compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
678 reg = <0x00 0x03400000 0x0 0x00100000
679 0x80 0x00000000 0x8 0x00000000>;
680 reg-names = "regs", "addr_space";
681 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
682 interrupt-names = "pme";
683 num-ib-windows = <6>;
684 num-ob-windows = <8>;
685 status = "disabled";
686 };
687
688 pcie2: pcie@3500000 {
689 compatible = "fsl,ls1028a-pcie";
690 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
691 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
692 reg-names = "regs", "config";
693 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
694 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
695 interrupt-names = "pme", "aer";
696 #address-cells = <3>;
697 #size-cells = <2>;
698 device_type = "pci";
699 dma-coherent;
700 num-viewport = <8>;
701 bus-range = <0x0 0xff>;
702 ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */
703 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
704 msi-parent = <&its>;
705 #interrupt-cells = <1>;
706 interrupt-map-mask = <0 0 0 7>;
707 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
708 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
709 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
710 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
711 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
712 status = "disabled";
713 };
714
715 pcie_ep2: pcie-ep@3500000 {
716 compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
717 reg = <0x00 0x03500000 0x0 0x00100000
718 0x88 0x00000000 0x8 0x00000000>;
719 reg-names = "regs", "addr_space";
720 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
721 interrupt-names = "pme";
722 num-ib-windows = <6>;
723 num-ob-windows = <8>;
724 status = "disabled";
725 };
726
727 smmu: iommu@5000000 {
728 compatible = "arm,mmu-500";
729 reg = <0 0x5000000 0 0x800000>;
730 #global-interrupts = <8>;
731 #iommu-cells = <1>;
732 dma-coherent;
733 stream-match-mask = <0x7c00>;
734 /* global secure fault */
735 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
736 /* combined secure interrupt */
737 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
738 /* global non-secure fault */
739 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
740 /* combined non-secure interrupt */
741 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
742 /* performance counter interrupts 0-7 */
743 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
745 /* per context interrupt, 64 interrupts */
746 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
754 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
755 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
756 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
757 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
758 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
759 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
761 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
765 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
767 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
768 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
769 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
770 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
772 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
773 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
774 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
775 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
776 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
777 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
778 };
779
780 crypto: crypto@8000000 {
781 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
782 fsl,sec-era = <10>;
783 #address-cells = <1>;
784 #size-cells = <1>;
785 ranges = <0x0 0x00 0x8000000 0x100000>;
786 reg = <0x00 0x8000000 0x0 0x100000>;
787 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
788 dma-coherent;
789
790 sec_jr0: jr@10000 {
791 compatible = "fsl,sec-v5.0-job-ring",
792 "fsl,sec-v4.0-job-ring";
793 reg = <0x10000 0x10000>;
794 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
795 };
796
797 sec_jr1: jr@20000 {
798 compatible = "fsl,sec-v5.0-job-ring",
799 "fsl,sec-v4.0-job-ring";
800 reg = <0x20000 0x10000>;
801 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
802 };
803
804 sec_jr2: jr@30000 {
805 compatible = "fsl,sec-v5.0-job-ring",
806 "fsl,sec-v4.0-job-ring";
807 reg = <0x30000 0x10000>;
808 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
809 };
810
811 sec_jr3: jr@40000 {
812 compatible = "fsl,sec-v5.0-job-ring",
813 "fsl,sec-v4.0-job-ring";
814 reg = <0x40000 0x10000>;
815 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
816 };
817 };
818
819 qdma: dma-controller@8380000 {
820 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma";
821 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
822 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
823 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
824 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
825 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
826 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
827 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
828 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
829 interrupt-names = "qdma-error", "qdma-queue0",
830 "qdma-queue1", "qdma-queue2", "qdma-queue3";
831 dma-channels = <8>;
832 block-number = <1>;
833 block-offset = <0x10000>;
834 fsl,dma-queues = <2>;
835 status-sizes = <64>;
836 queue-sizes = <64 64>;
837 };
838
839 cluster1_core0_watchdog: watchdog@c000000 {
840 compatible = "arm,sp805", "arm,primecell";
841 reg = <0x0 0xc000000 0x0 0x1000>;
842 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
843 QORIQ_CLK_PLL_DIV(16)>,
844 <&clockgen QORIQ_CLK_PLATFORM_PLL
845 QORIQ_CLK_PLL_DIV(16)>;
846 clock-names = "wdog_clk", "apb_pclk";
847 };
848
849 cluster1_core1_watchdog: watchdog@c010000 {
850 compatible = "arm,sp805", "arm,primecell";
851 reg = <0x0 0xc010000 0x0 0x1000>;
852 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
853 QORIQ_CLK_PLL_DIV(16)>,
854 <&clockgen QORIQ_CLK_PLATFORM_PLL
855 QORIQ_CLK_PLL_DIV(16)>;
856 clock-names = "wdog_clk", "apb_pclk";
857 };
858
859 malidp0: display@f080000 {
860 compatible = "arm,mali-dp500";
861 reg = <0x0 0xf080000 0x0 0x10000>;
862 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
863 <0 223 IRQ_TYPE_LEVEL_HIGH>;
864 interrupt-names = "DE", "SE";
865 clocks = <&dpclk>,
866 <&clockgen QORIQ_CLK_HWACCEL 2>,
867 <&clockgen QORIQ_CLK_HWACCEL 2>,
868 <&clockgen QORIQ_CLK_HWACCEL 2>;
869 clock-names = "pxlclk", "mclk", "aclk", "pclk";
870 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
871 arm,malidp-arqos-value = <0xd000d000>;
872
873 port {
874 dpi0_out: endpoint {
875
876 };
877 };
878 };
879
880 gpu: gpu@f0c0000 {
881 compatible = "vivante,gc";
882 reg = <0x0 0xf0c0000 0x0 0x10000>;
883 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
884 clocks = <&clockgen QORIQ_CLK_HWACCEL 2>,
885 <&clockgen QORIQ_CLK_HWACCEL 2>,
886 <&clockgen QORIQ_CLK_HWACCEL 2>;
887 clock-names = "core", "shader", "bus";
888 #cooling-cells = <2>;
889 };
890
891 sai1: audio-controller@f100000 {
892 #sound-dai-cells = <0>;
893 compatible = "fsl,vf610-sai";
894 reg = <0x0 0xf100000 0x0 0x10000>;
895 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
897 QORIQ_CLK_PLL_DIV(2)>,
898 <&clockgen QORIQ_CLK_PLATFORM_PLL
899 QORIQ_CLK_PLL_DIV(2)>,
900 <&clockgen QORIQ_CLK_PLATFORM_PLL
901 QORIQ_CLK_PLL_DIV(2)>,
902 <&clockgen QORIQ_CLK_PLATFORM_PLL
903 QORIQ_CLK_PLL_DIV(2)>;
904 clock-names = "bus", "mclk1", "mclk2", "mclk3";
905 dma-names = "tx", "rx";
906 dmas = <&edma0 1 4>,
907 <&edma0 1 3>;
908 fsl,sai-asynchronous;
909 status = "disabled";
910 };
911
912 sai2: audio-controller@f110000 {
913 #sound-dai-cells = <0>;
914 compatible = "fsl,vf610-sai";
915 reg = <0x0 0xf110000 0x0 0x10000>;
916 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
917 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
918 QORIQ_CLK_PLL_DIV(2)>,
919 <&clockgen QORIQ_CLK_PLATFORM_PLL
920 QORIQ_CLK_PLL_DIV(2)>,
921 <&clockgen QORIQ_CLK_PLATFORM_PLL
922 QORIQ_CLK_PLL_DIV(2)>,
923 <&clockgen QORIQ_CLK_PLATFORM_PLL
924 QORIQ_CLK_PLL_DIV(2)>;
925 clock-names = "bus", "mclk1", "mclk2", "mclk3";
926 dma-names = "tx", "rx";
927 dmas = <&edma0 1 6>,
928 <&edma0 1 5>;
929 fsl,sai-asynchronous;
930 status = "disabled";
931 };
932
933 sai3: audio-controller@f120000 {
934 #sound-dai-cells = <0>;
935 compatible = "fsl,vf610-sai";
936 reg = <0x0 0xf120000 0x0 0x10000>;
937 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
938 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
939 QORIQ_CLK_PLL_DIV(2)>,
940 <&clockgen QORIQ_CLK_PLATFORM_PLL
941 QORIQ_CLK_PLL_DIV(2)>,
942 <&clockgen QORIQ_CLK_PLATFORM_PLL
943 QORIQ_CLK_PLL_DIV(2)>,
944 <&clockgen QORIQ_CLK_PLATFORM_PLL
945 QORIQ_CLK_PLL_DIV(2)>;
946 clock-names = "bus", "mclk1", "mclk2", "mclk3";
947 dma-names = "tx", "rx";
948 dmas = <&edma0 1 8>,
949 <&edma0 1 7>;
950 fsl,sai-asynchronous;
951 status = "disabled";
952 };
953
954 sai4: audio-controller@f130000 {
955 #sound-dai-cells = <0>;
956 compatible = "fsl,vf610-sai";
957 reg = <0x0 0xf130000 0x0 0x10000>;
958 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
959 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
960 QORIQ_CLK_PLL_DIV(2)>,
961 <&clockgen QORIQ_CLK_PLATFORM_PLL
962 QORIQ_CLK_PLL_DIV(2)>,
963 <&clockgen QORIQ_CLK_PLATFORM_PLL
964 QORIQ_CLK_PLL_DIV(2)>,
965 <&clockgen QORIQ_CLK_PLATFORM_PLL
966 QORIQ_CLK_PLL_DIV(2)>;
967 clock-names = "bus", "mclk1", "mclk2", "mclk3";
968 dma-names = "tx", "rx";
969 dmas = <&edma0 1 10>,
970 <&edma0 1 9>;
971 fsl,sai-asynchronous;
972 status = "disabled";
973 };
974
975 sai5: audio-controller@f140000 {
976 #sound-dai-cells = <0>;
977 compatible = "fsl,vf610-sai";
978 reg = <0x0 0xf140000 0x0 0x10000>;
979 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
980 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
981 QORIQ_CLK_PLL_DIV(2)>,
982 <&clockgen QORIQ_CLK_PLATFORM_PLL
983 QORIQ_CLK_PLL_DIV(2)>,
984 <&clockgen QORIQ_CLK_PLATFORM_PLL
985 QORIQ_CLK_PLL_DIV(2)>,
986 <&clockgen QORIQ_CLK_PLATFORM_PLL
987 QORIQ_CLK_PLL_DIV(2)>;
988 clock-names = "bus", "mclk1", "mclk2", "mclk3";
989 dma-names = "tx", "rx";
990 dmas = <&edma0 1 12>,
991 <&edma0 1 11>;
992 fsl,sai-asynchronous;
993 status = "disabled";
994 };
995
996 sai6: audio-controller@f150000 {
997 #sound-dai-cells = <0>;
998 compatible = "fsl,vf610-sai";
999 reg = <0x0 0xf150000 0x0 0x10000>;
1000 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1001 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1002 QORIQ_CLK_PLL_DIV(2)>,
1003 <&clockgen QORIQ_CLK_PLATFORM_PLL
1004 QORIQ_CLK_PLL_DIV(2)>,
1005 <&clockgen QORIQ_CLK_PLATFORM_PLL
1006 QORIQ_CLK_PLL_DIV(2)>,
1007 <&clockgen QORIQ_CLK_PLATFORM_PLL
1008 QORIQ_CLK_PLL_DIV(2)>;
1009 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1010 dma-names = "tx", "rx";
1011 dmas = <&edma0 1 14>,
1012 <&edma0 1 13>;
1013 fsl,sai-asynchronous;
1014 status = "disabled";
1015 };
1016
1017 dpclk: clock-controller@f1f0000 {
1018 compatible = "fsl,ls1028a-plldig";
1019 reg = <0x0 0xf1f0000 0x0 0x10000>;
1020 #clock-cells = <0>;
1021 clocks = <&osc_27m>;
1022 };
1023
1024 tmu: tmu@1f80000 {
1025 compatible = "fsl,qoriq-tmu";
1026 reg = <0x0 0x1f80000 0x0 0x10000>;
1027 interrupts = <0 23 0x4>;
1028 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
1029 fsl,tmu-calibration =
1030 <0x00000000 0x00000024>,
1031 <0x00000001 0x0000002b>,
1032 <0x00000002 0x00000031>,
1033 <0x00000003 0x00000038>,
1034 <0x00000004 0x0000003f>,
1035 <0x00000005 0x00000045>,
1036 <0x00000006 0x0000004c>,
1037 <0x00000007 0x00000053>,
1038 <0x00000008 0x00000059>,
1039 <0x00000009 0x00000060>,
1040 <0x0000000a 0x00000066>,
1041 <0x0000000b 0x0000006d>,
1042
1043 <0x00010000 0x0000001c>,
1044 <0x00010001 0x00000024>,
1045 <0x00010002 0x0000002c>,
1046 <0x00010003 0x00000035>,
1047 <0x00010004 0x0000003d>,
1048 <0x00010005 0x00000045>,
1049 <0x00010006 0x0000004d>,
1050 <0x00010007 0x00000055>,
1051 <0x00010008 0x0000005e>,
1052 <0x00010009 0x00000066>,
1053 <0x0001000a 0x0000006e>,
1054
1055 <0x00020000 0x00000018>,
1056 <0x00020001 0x00000022>,
1057 <0x00020002 0x0000002d>,
1058 <0x00020003 0x00000038>,
1059 <0x00020004 0x00000043>,
1060 <0x00020005 0x0000004d>,
1061 <0x00020006 0x00000058>,
1062 <0x00020007 0x00000063>,
1063 <0x00020008 0x0000006e>,
1064
1065 <0x00030000 0x00000010>,
1066 <0x00030001 0x0000001c>,
1067 <0x00030002 0x00000029>,
1068 <0x00030003 0x00000036>,
1069 <0x00030004 0x00000042>,
1070 <0x00030005 0x0000004f>,
1071 <0x00030006 0x0000005b>,
1072 <0x00030007 0x00000068>;
1073 little-endian;
1074 #thermal-sensor-cells = <1>;
1075 };
1076
1077 pcie@1f0000000 { /* Integrated Endpoint Root Complex */
1078 compatible = "pci-host-ecam-generic";
1079 reg = <0x01 0xf0000000 0x0 0x100000>;
1080 #address-cells = <3>;
1081 #size-cells = <2>;
1082 msi-parent = <&its>;
1083 device_type = "pci";
1084 bus-range = <0x0 0x0>;
1085 dma-coherent;
1086 msi-map = <0 &its 0x17 0xe>;
1087 iommu-map = <0 &smmu 0x17 0xe>;
1088 /* PF0-6 BAR0 - non-prefetchable memory */
1089 ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000
1090 /* PF0-6 BAR2 - prefetchable memory */
1091 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000
1092 /* PF0: VF0-1 BAR0 - non-prefetchable memory */
1093 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000
1094 /* PF0: VF0-1 BAR2 - prefetchable memory */
1095 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000
1096 /* PF1: VF0-1 BAR0 - non-prefetchable memory */
1097 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000
1098 /* PF1: VF0-1 BAR2 - prefetchable memory */
1099 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000
1100 /* BAR4 (PF5) - non-prefetchable memory */
1101 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>;
1102
1103 enetc_port0: ethernet@0,0 {
1104 compatible = "fsl,enetc";
1105 reg = <0x000000 0 0 0 0>;
1106 status = "disabled";
1107 };
1108
1109 enetc_port1: ethernet@0,1 {
1110 compatible = "fsl,enetc";
1111 reg = <0x000100 0 0 0 0>;
1112 status = "disabled";
1113 };
1114
1115 enetc_port2: ethernet@0,2 {
1116 compatible = "fsl,enetc";
1117 reg = <0x000200 0 0 0 0>;
1118 phy-mode = "internal";
1119 status = "disabled";
1120
1121 fixed-link {
1122 speed = <2500>;
1123 full-duplex;
1124 pause;
1125 };
1126 };
1127
1128 enetc_mdio_pf3: mdio@0,3 {
1129 compatible = "fsl,enetc-mdio";
1130 reg = <0x000300 0 0 0 0>;
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1133 };
1134
1135 ethernet@0,4 {
1136 compatible = "fsl,enetc-ptp";
1137 reg = <0x000400 0 0 0 0>;
1138 clocks = <&clockgen QORIQ_CLK_HWACCEL 3>;
1139 little-endian;
1140 fsl,extts-fifo;
1141 };
1142
1143 mscc_felix: ethernet-switch@0,5 {
1144 reg = <0x000500 0 0 0 0>;
1145 /* IEP INT_B */
1146 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1147 status = "disabled";
1148
1149 mscc_felix_ports: ports {
1150 #address-cells = <1>;
1151 #size-cells = <0>;
1152
1153 /* External ports */
1154 mscc_felix_port0: port@0 {
1155 reg = <0>;
1156 status = "disabled";
1157 };
1158
1159 mscc_felix_port1: port@1 {
1160 reg = <1>;
1161 status = "disabled";
1162 };
1163
1164 mscc_felix_port2: port@2 {
1165 reg = <2>;
1166 status = "disabled";
1167 };
1168
1169 mscc_felix_port3: port@3 {
1170 reg = <3>;
1171 status = "disabled";
1172 };
1173
1174 /* Internal ports */
1175 mscc_felix_port4: port@4 {
1176 reg = <4>;
1177 phy-mode = "internal";
1178 ethernet = <&enetc_port2>;
1179 status = "disabled";
1180
1181 fixed-link {
1182 speed = <2500>;
1183 full-duplex;
1184 pause;
1185 };
1186 };
1187
1188 mscc_felix_port5: port@5 {
1189 reg = <5>;
1190 phy-mode = "internal";
1191 ethernet = <&enetc_port3>;
1192 status = "disabled";
1193
1194 fixed-link {
1195 speed = <1000>;
1196 full-duplex;
1197 pause;
1198 };
1199 };
1200 };
1201 };
1202
1203 enetc_port3: ethernet@0,6 {
1204 compatible = "fsl,enetc";
1205 reg = <0x000600 0 0 0 0>;
1206 phy-mode = "internal";
1207 status = "disabled";
1208
1209 fixed-link {
1210 speed = <1000>;
1211 full-duplex;
1212 pause;
1213 };
1214 };
1215
1216 rcec@1f,0 {
1217 reg = <0x00f800 0 0 0 0>;
1218 /* IEP INT_A */
1219 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1220 };
1221 };
1222
1223 /* Integrated Endpoint Register Block */
1224 ierb@1f0800000 {
1225 compatible = "fsl,ls1028a-enetc-ierb";
1226 reg = <0x01 0xf0800000 0x0 0x10000>;
1227 };
1228
1229 pwm0: pwm@2800000 {
1230 compatible = "fsl,vf610-ftm-pwm";
1231 #pwm-cells = <3>;
1232 reg = <0x0 0x2800000 0x0 0x10000>;
1233 clock-names = "ftm_sys", "ftm_ext",
1234 "ftm_fix", "ftm_cnt_clk_en";
1235 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1236 <&rtc_clk>, <&clockgen 4 1>;
1237 status = "disabled";
1238 };
1239
1240 pwm1: pwm@2810000 {
1241 compatible = "fsl,vf610-ftm-pwm";
1242 #pwm-cells = <3>;
1243 reg = <0x0 0x2810000 0x0 0x10000>;
1244 clock-names = "ftm_sys", "ftm_ext",
1245 "ftm_fix", "ftm_cnt_clk_en";
1246 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1247 <&rtc_clk>, <&clockgen 4 1>;
1248 status = "disabled";
1249 };
1250
1251 pwm2: pwm@2820000 {
1252 compatible = "fsl,vf610-ftm-pwm";
1253 #pwm-cells = <3>;
1254 reg = <0x0 0x2820000 0x0 0x10000>;
1255 clock-names = "ftm_sys", "ftm_ext",
1256 "ftm_fix", "ftm_cnt_clk_en";
1257 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1258 <&rtc_clk>, <&clockgen 4 1>;
1259 status = "disabled";
1260 };
1261
1262 pwm3: pwm@2830000 {
1263 compatible = "fsl,vf610-ftm-pwm";
1264 #pwm-cells = <3>;
1265 reg = <0x0 0x2830000 0x0 0x10000>;
1266 clock-names = "ftm_sys", "ftm_ext",
1267 "ftm_fix", "ftm_cnt_clk_en";
1268 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1269 <&rtc_clk>, <&clockgen 4 1>;
1270 status = "disabled";
1271 };
1272
1273 pwm4: pwm@2840000 {
1274 compatible = "fsl,vf610-ftm-pwm";
1275 #pwm-cells = <3>;
1276 reg = <0x0 0x2840000 0x0 0x10000>;
1277 clock-names = "ftm_sys", "ftm_ext",
1278 "ftm_fix", "ftm_cnt_clk_en";
1279 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1280 <&rtc_clk>, <&clockgen 4 1>;
1281 status = "disabled";
1282 };
1283
1284 pwm5: pwm@2850000 {
1285 compatible = "fsl,vf610-ftm-pwm";
1286 #pwm-cells = <3>;
1287 reg = <0x0 0x2850000 0x0 0x10000>;
1288 clock-names = "ftm_sys", "ftm_ext",
1289 "ftm_fix", "ftm_cnt_clk_en";
1290 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1291 <&rtc_clk>, <&clockgen 4 1>;
1292 status = "disabled";
1293 };
1294
1295 pwm6: pwm@2860000 {
1296 compatible = "fsl,vf610-ftm-pwm";
1297 #pwm-cells = <3>;
1298 reg = <0x0 0x2860000 0x0 0x10000>;
1299 clock-names = "ftm_sys", "ftm_ext",
1300 "ftm_fix", "ftm_cnt_clk_en";
1301 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1302 <&rtc_clk>, <&clockgen 4 1>;
1303 status = "disabled";
1304 };
1305
1306 pwm7: pwm@2870000 {
1307 compatible = "fsl,vf610-ftm-pwm";
1308 #pwm-cells = <3>;
1309 reg = <0x0 0x2870000 0x0 0x10000>;
1310 clock-names = "ftm_sys", "ftm_ext",
1311 "ftm_fix", "ftm_cnt_clk_en";
1312 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
1313 <&rtc_clk>, <&clockgen 4 1>;
1314 status = "disabled";
1315 };
1316
1317 rcpm: power-controller@1e34040 {
1318 compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+";
1319 reg = <0x0 0x1e34040 0x0 0x1c>;
1320 #fsl,rcpm-wakeup-cells = <7>;
1321 little-endian;
1322 };
1323
1324 ftm_alarm0: timer@2800000 {
1325 compatible = "fsl,ls1028a-ftm-alarm";
1326 reg = <0x0 0x2800000 0x0 0x10000>;
1327 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
1328 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1329 status = "disabled";
1330 };
1331
1332 ftm_alarm1: timer@2810000 {
1333 compatible = "fsl,ls1028a-ftm-alarm";
1334 reg = <0x0 0x2810000 0x0 0x10000>;
1335 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
1336 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1337 status = "disabled";
1338 };
1339 };
1340
1341 };
"Das U-Boot" Source Tree