src/arm64/freescale/imx8mq-tqma8mq-mba8mx.dts

   1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
   2 /*
   3  * Copyright 2019-2021 TQ-Systems GmbH
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "imx8mq-tqma8mq.dtsi"
   9 #include "mba8mx.dtsi"
  10
  11 / {
  12         model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ on MBa8Mx";
  13         compatible = "tq,imx8mq-tqma8mq-mba8mx", "tq,imx8mq-tqma8mq", "fsl,imx8mq";
  14
  15         aliases {
  16                 eeprom0 = &eeprom3;
  17                 mmc0 = &usdhc1;
  18                 mmc1 = &usdhc2;
  19                 rtc0 = &pcf85063;
  20                 rtc1 = &snvs_rtc;
  21         };
  22
  23         extcon_usbotg: extcon-usbotg0 {
  24                 compatible = "linux,extcon-usb-gpio";
  25                 pinctrl-names = "default";
  26                 pinctrl-0 = <&pinctrl_usbcon0>;
  27                 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
  28         };
  29
  30         pcie0_refclk: pcie0-refclk {
  31                 compatible = "fixed-clock";
  32                 #clock-cells = <0>;
  33                 clock-frequency = <100000000>;
  34         };
  35
  36         pcie1_refclk: pcie1-refclk {
  37                 compatible = "fixed-clock";
  38                 #clock-cells = <0>;
  39                 clock-frequency = <100000000>;
  40         };
  41
  42         reg_otg_vbus: regulator-otg-vbus {
  43                 compatible = "regulator-fixed";
  44                 pinctrl-names = "default";
  45                 pinctrl-0 = <&pinctrl_regotgvbus>;
  46                 regulator-name = "MBA8MQ_OTG_VBUS";
  47                 regulator-min-microvolt = <5000000>;
  48                 regulator-max-microvolt = <5000000>;
  49                 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  50                 enable-active-high;
  51         };
  52
  53         reg_usdhc2_vmmc: regulator-vmmc {
  54                 compatible = "regulator-fixed";
  55                 regulator-name = "VSD_3V3";
  56                 regulator-min-microvolt = <3300000>;
  57                 regulator-max-microvolt = <3300000>;
  58                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  59                 enable-active-high;
  60         };
  61 };
  62
  63 &btn2 {
  64         gpios = <&gpio3 17 GPIO_ACTIVE_LOW>;
  65 };
  66
  67 &gpio_leds {
  68         led3 {
  69                 label = "led3";
  70                 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
  71         };
  72 };
  73
  74 &i2c1 {
  75         expander2: gpio@25 {
  76                 compatible = "nxp,pca9555";
  77                 reg = <0x25>;
  78                 gpio-controller;
  79                 #gpio-cells = <2>;
  80                 vcc-supply = <&reg_vcc_3v3>;
  81                 pinctrl-names = "default";
  82                 pinctrl-0 = <&pinctrl_expander>;
  83                 interrupt-parent = <&gpio1>;
  84                 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
  85                 interrupt-controller;
  86                 #interrupt-cells = <2>;
  87
  88                 mpcie-rst-hog {
  89                         gpio-hog;
  90                         gpios = <13 0>;
  91                         output-high;
  92                         line-name = "MPCIE_RST#";
  93                 };
  94         };
  95 };
  96
  97 &irqsteer {
  98         status = "okay";
  99 };
 100
 101 &led2 {
 102         gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
 103 };
 104
 105 &pcie0 {
 106         reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
 107         clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
 108                  <&pcie0_refclk>,
 109                  <&clk IMX8MQ_CLK_PCIE1_PHY>,
 110                  <&clk IMX8MQ_CLK_PCIE1_AUX>;
 111         status = "okay";
 112 };
 113
 114 /*
 115  * miniPCIe, also usable for cards with USB. Therefore configure the reset as
 116  * static gpio hog.
 117  */
 118 &pcie1 {
 119         clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
 120                  <&pcie1_refclk>,
 121                  <&clk IMX8MQ_CLK_PCIE2_PHY>,
 122                  <&clk IMX8MQ_CLK_PCIE2_AUX>;
 123         status = "okay";
 124 };
 125
 126 &sai3 {
 127         assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
 128         assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
 129         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
 130         clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, <&clk IMX8MQ_CLK_DUMMY>,
 131                 <&clk IMX8MQ_CLK_SAI3_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
 132                 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>,
 133                 <&clk IMX8MQ_AUDIO_PLL2_OUT>;
 134 };
 135
 136 &tlv320aic3x04 {
 137         clock-names = "mclk";
 138         clocks = <&clk IMX8MQ_CLK_SAI3_ROOT>;
 139 };
 140
 141 &uart1 {
 142         assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
 143         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
 144 };
 145
 146 &uart2 {
 147         assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
 148         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
 149 };
 150
 151 /* console */
 152 &uart3 {
 153         assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
 154         assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
 155 };
 156
 157 &usb3_phy0 {
 158         vbus-supply = <&reg_otg_vbus>;
 159         status = "okay";
 160 };
 161
 162 &usb_dwc3_0 {
 163         /* we implement dual role but not full featured OTG */
 164         extcon = <&extcon_usbotg>;
 165         hnp-disable;
 166         srp-disable;
 167         adp-disable;
 168         dr_mode = "otg";
 169         status = "okay";
 170 };
 171
 172 &usb3_phy1 {
 173         status = "okay";
 174 };
 175
 176 &usb_dwc3_1 {
 177         status = "okay";
 178         dr_mode = "host";
 179 };
 180
 181 &wdog1 {
 182         pinctrl-names = "default";
 183         pinctrl-0 = <&pinctrl_wdog>;
 184         fsl,ext-reset-output;
 185         status = "okay";
 186 };
 187
 188 &iomuxc {
 189         pinctrl_ecspi1: ecspi1grp {
 190                 fsl,pins = <MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK        0x0000004e>,
 191                            <MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI        0x0000004e>,
 192                            <MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO        0x0000004e>,
 193                            <MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9           0x0000004e>;
 194         };
 195
 196         pinctrl_ecspi2: ecspi2grp {
 197                 fsl,pins = <MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK        0x0000004e>,
 198                            <MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI        0x0000004e>,
 199                            <MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO        0x0000004e>,
 200                            <MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13          0x0000004e>;
 201         };
 202
 203         pinctrl_expander: expandergrp {
 204                 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9           0xd6>;
 205         };
 206
 207         pinctrl_fec1: fec1grp {
 208                 fsl,pins = <MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC             0x3>,
 209                            <MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO           0x23>,
 210                            <MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3       0x1f>,
 211                            <MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2       0x1f>,
 212                            <MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1       0x1f>,
 213                            <MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0       0x1f>,
 214                            <MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3       0x91>,
 215                            <MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2       0x91>,
 216                            <MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1       0x91>,
 217                            <MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0       0x91>,
 218                            <MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC       0x1f>,
 219                            <MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC       0x91>,
 220                            <MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
 221                            <MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>;
 222         };
 223
 224         pinctrl_gpiobutton: gpiobuttongrp {
 225                 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5           0x41>,
 226                            <MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7           0x41>,
 227                            <MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17           0x41>;
 228         };
 229
 230         pinctrl_gpioled: gpioledgrp {
 231                 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0           0x41>,
 232                            <MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8           0x41>,
 233                            <MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16        0x41>;
 234         };
 235
 236         pinctrl_i2c2: i2c2grp {
 237                 fsl,pins = <MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL              0x40000067>,
 238                            <MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA              0x40000067>;
 239         };
 240
 241         pinctrl_i2c2_gpio: i2c2gpiogrp {
 242                 fsl,pins = <MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16            0x40000067>,
 243                            <MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17            0x40000067>;
 244         };
 245
 246         pinctrl_i2c3: i2c3grp {
 247                 fsl,pins = <MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL              0x40000067>,
 248                            <MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA              0x40000067>;
 249         };
 250
 251         pinctrl_i2c3_gpio: i2c3gpiogrp {
 252                 fsl,pins = <MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18            0x40000067>,
 253                            <MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19            0x40000067>;
 254         };
 255
 256         pinctrl_pwm3: pwm3grp {
 257                 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT            0x16>;
 258         };
 259
 260         pinctrl_pwm4: pwm4grp {
 261                 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT            0x16>;
 262         };
 263
 264         pinctrl_regotgvbus: reggotgvbusgrp {
 265                 /* USB1 OTG PWR as GPIO */
 266                 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12          0x06>;
 267         };
 268
 269         pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 270                 fsl,pins = <MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19         0xc1>;
 271         };
 272
 273         pinctrl_sai3: sai3grp {
 274                 fsl,pins = <MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK            0xd6>,
 275                            <MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK          0xd6>,
 276                            <MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC         0xd6>,
 277                            <MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0         0xd6>,
 278                            <MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC         0xd6>,
 279                            <MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0         0xd6>,
 280                            <MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK          0xd6>;
 281         };
 282
 283         pinctrl_uart1: uart1grp {
 284                 fsl,pins = <MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX         0x79>,
 285                            <MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX         0x79>;
 286         };
 287
 288         pinctrl_uart2: uart2grp {
 289                 fsl,pins = <MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX         0x79>,
 290                            <MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX         0x79>;
 291         };
 292
 293         pinctrl_uart3: uart3grp {
 294                 fsl,pins = <MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX         0x79>,
 295                            <MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX         0x79>;
 296         };
 297
 298         pinctrl_uart4: uart4grp {
 299                 fsl,pins = <MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX         0x79>,
 300                            <MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX         0x79>;
 301         };
 302
 303         pinctrl_usbcon0: usb0congrp {
 304                 /* ID: floating / high: device, low: host -> use PU */
 305                 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10          0xe6>;
 306         };
 307
 308         pinctrl_usdhc2: usdhc2grp {
 309                 fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK             0x83>,
 310                            <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD             0xc3>,
 311                            <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0         0xc3>,
 312                            <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1         0xc3>,
 313                            <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2         0xc3>,
 314                            <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3         0xc3>,
 315                            <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT      0xc1>;
 316         };
 317
 318         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 319                 fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK             0x85>,
 320                            <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD             0xc5>,
 321                            <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0         0xc5>,
 322                            <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1         0xc5>,
 323                            <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2         0xc5>,
 324                            <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3         0xc5>,
 325                            <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT      0xc1>;
 326         };
 327
 328         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 329                 fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK             0x9f>,
 330                            <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD             0xc7>,
 331                            <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0         0xc7>,
 332                            <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1         0xc7>,
 333                            <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2         0xc7>,
 334                            <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3         0xc7>,
 335                            <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT      0xc1>;
 336         };
 337
 338         pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
 339                 fsl,pins = <MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12            0x41>;
 340         };
 341 };