src/arm64/hisilicon/hip07-d05.dts

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /**
   3  * dts file for Hisilicon D05 Development Board
   4  *
   5  * Copyright (C) 2016 HiSilicon Ltd.
   6  */
   7
   8 /dts-v1/;
   9
  10 #include "hip07.dtsi"
  11
  12 / {
  13         model = "Hisilicon Hip07 D05 Development Board";
  14         compatible = "hisilicon,hip07-d05";
  15
  16         /* the mem node will be updated by UEFI. */
  17         memory@0 {
  18                 device_type = "memory";
  19                 reg = <0x0 0x00000000 0x0 0x40000000>;
  20                 numa-node-id = <0>;
  21         };
  22
  23         distance-map {
  24                 compatible = "numa-distance-map-v1";
  25                 distance-matrix = <0 0 10>,
  26                                   <0 1 15>,
  27                                   <0 2 20>,
  28                                   <0 3 25>,
  29                                   <1 0 15>,
  30                                   <1 1 10>,
  31                                   <1 2 25>,
  32                                   <1 3 30>,
  33                                   <2 0 20>,
  34                                   <2 1 25>,
  35                                   <2 2 10>,
  36                                   <2 3 15>,
  37                                   <3 0 25>,
  38                                   <3 1 30>,
  39                                   <3 2 15>,
  40                                   <3 3 10>;
  41         };
  42
  43         aliases {
  44                 serial0 = &uart0;
  45         };
  46
  47         chosen {
  48                 stdout-path = "serial0:115200n8";
  49         };
  50 };
  51
  52 &uart0 {
  53         status = "okay";
  54 };
  55
  56 &ipmi0 {
  57         status = "okay";
  58 };
  59
  60 &usb_ohci {
  61         status = "okay";
  62 };
  63
  64 &usb_ehci {
  65         status = "okay";
  66 };
  67
  68 &eth0 {
  69         status = "okay";
  70 };
  71
  72 &eth1 {
  73         status = "okay";
  74 };
  75
  76 &eth2 {
  77         status = "okay";
  78 };
  79
  80 &eth3 {
  81         status = "okay";
  82 };
  83
  84 &sas1 {
  85         status = "okay";
  86 };
  87
  88 &p0_pcie2_a {
  89         status = "okay";
  90 };