src/arm64/intel/socfpga_agilex5.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2023, Intel Corporation
   4  */
   5
   6 /dts-v1/;
   7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
  12
  13 / {
  14         compatible = "intel,socfpga-agilex5";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         reserved-memory {
  19                 #address-cells = <2>;
  20                 #size-cells = <2>;
  21                 ranges;
  22
  23                 service_reserved: svcbuffer@0 {
  24                         compatible = "shared-dma-pool";
  25                         reg = <0x0 0x80000000 0x0 0x2000000>;
  26                         alignment = <0x1000>;
  27                         no-map;
  28                 };
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 cpu0: cpu@0 {
  36                         compatible = "arm,cortex-a55";
  37                         reg = <0x0>;
  38                         device_type = "cpu";
  39                         enable-method = "psci";
  40                 };
  41
  42                 cpu1: cpu@1 {
  43                         compatible = "arm,cortex-a55";
  44                         reg = <0x100>;
  45                         device_type = "cpu";
  46                         enable-method = "psci";
  47                 };
  48
  49                 cpu2: cpu@2 {
  50                         compatible = "arm,cortex-a76";
  51                         reg = <0x200>;
  52                         device_type = "cpu";
  53                         enable-method = "psci";
  54                 };
  55
  56                 cpu3: cpu@3 {
  57                         compatible = "arm,cortex-a76";
  58                         reg = <0x300>;
  59                         device_type = "cpu";
  60                         enable-method = "psci";
  61                 };
  62         };
  63
  64         psci {
  65                 compatible = "arm,psci-0.2";
  66                 method = "smc";
  67         };
  68
  69         intc: interrupt-controller@1d000000 {
  70                 compatible = "arm,gic-v3";
  71                 reg = <0x0 0x1d000000 0 0x10000>,
  72                         <0x0 0x1d060000 0 0x100000>;
  73                 ranges;
  74                 #interrupt-cells = <3>;
  75                 #address-cells = <2>;
  76                 #size-cells = <2>;
  77                 interrupt-controller;
  78                 #redistributor-regions = <1>;
  79                 redistributor-stride = <0x0 0x20000>;
  80
  81                 its: msi-controller@1d040000 {
  82                         compatible = "arm,gic-v3-its";
  83                         reg = <0x0 0x1d040000 0x0 0x20000>;
  84                         msi-controller;
  85                         #msi-cells = <1>;
  86                 };
  87         };
  88
  89         /* Clock tree 5 main sources*/
  90         clocks {
  91                 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
  92                         #clock-cells = <0>;
  93                         compatible = "fixed-clock";
  94                         clock-frequency = <0>;
  95                 };
  96
  97                 cb_intosc_ls_clk: cb-intosc-ls-clk {
  98                         #clock-cells = <0>;
  99                         compatible = "fixed-clock";
 100                         clock-frequency = <0>;
 101                 };
 102
 103                 f2s_free_clk: f2s-free-clk {
 104                         #clock-cells = <0>;
 105                         compatible = "fixed-clock";
 106                         clock-frequency = <0>;
 107                 };
 108
 109                 osc1: osc1 {
 110                         #clock-cells = <0>;
 111                         compatible = "fixed-clock";
 112                         clock-frequency = <0>;
 113                 };
 114
 115                 qspi_clk: qspi-clk {
 116                         #clock-cells = <0>;
 117                         compatible = "fixed-clock";
 118                         clock-frequency = <200000000>;
 119                 };
 120         };
 121
 122         timer {
 123                 compatible = "arm,armv8-timer";
 124                 interrupt-parent = <&intc>;
 125                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 126                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 127                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 128                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 129         };
 130
 131         usbphy0: usbphy {
 132                 #phy-cells = <0>;
 133                 compatible = "usb-nop-xceiv";
 134         };
 135
 136         soc: soc@0 {
 137                 compatible = "simple-bus";
 138                 ranges = <0 0 0 0xffffffff>;
 139                 #address-cells = <1>;
 140                 #size-cells = <1>;
 141                 device_type = "soc";
 142                 interrupt-parent = <&intc>;
 143
 144                 clkmgr: clock-controller@10d10000 {
 145                         compatible = "intel,agilex5-clkmgr";
 146                         reg = <0x10d10000 0x1000>;
 147                         #clock-cells = <1>;
 148                 };
 149
 150                 i2c0: i2c@10c02800 {
 151                         compatible = "snps,designware-i2c";
 152                         reg = <0x10c02800 0x100>;
 153                         #address-cells = <1>;
 154                         #size-cells = <0>;
 155                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 156                         resets = <&rst I2C0_RESET>;
 157                         clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
 158                         status = "disabled";
 159                 };
 160
 161                 i2c1: i2c@10c02900 {
 162                         compatible = "snps,designware-i2c";
 163                         reg = <0x10c02900 0x100>;
 164                         #address-cells = <1>;
 165                         #size-cells = <0>;
 166                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 167                         resets = <&rst I2C1_RESET>;
 168                         clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
 169                         status = "disabled";
 170                 };
 171
 172                 i2c2: i2c@10c02a00 {
 173                         compatible = "snps,designware-i2c";
 174                         reg = <0x10c02a00 0x100>;
 175                         #address-cells = <1>;
 176                         #size-cells = <0>;
 177                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 178                         resets = <&rst I2C2_RESET>;
 179                         clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
 180                         status = "disabled";
 181                 };
 182
 183                 i2c3: i2c@10c02b00 {
 184                         compatible = "snps,designware-i2c";
 185                         reg = <0x10c02b00 0x100>;
 186                         #address-cells = <1>;
 187                         #size-cells = <0>;
 188                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 189                         resets = <&rst I2C3_RESET>;
 190                         clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
 191                         status = "disabled";
 192                 };
 193
 194                 i2c4: i2c@10c02c00 {
 195                         compatible = "snps,designware-i2c";
 196                         reg = <0x10c02c00 0x100>;
 197                         #address-cells = <1>;
 198                         #size-cells = <0>;
 199                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 200                         resets = <&rst I2C4_RESET>;
 201                         clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
 202                         status = "disabled";
 203                 };
 204
 205                 i3c0: i3c-master@10da0000 {
 206                         compatible = "snps,dw-i3c-master-1.00a";
 207                         reg = <0x10da0000 0x1000>;
 208                         #address-cells = <3>;
 209                         #size-cells = <0>;
 210                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 211                         clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
 212                         status = "disabled";
 213                 };
 214
 215                 i3c1: i3c-master@10da1000 {
 216                         compatible = "snps,dw-i3c-master-1.00a";
 217                         reg = <0x10da1000 0x1000>;
 218                         #address-cells = <3>;
 219                         #size-cells = <0>;
 220                         interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 221                         clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
 222                         status = "disabled";
 223                 };
 224
 225                 gpio1: gpio@10c03300 {
 226                         compatible = "snps,dw-apb-gpio";
 227                         reg = <0x10c03300 0x100>;
 228                         #address-cells = <1>;
 229                         #size-cells = <0>;
 230                         resets = <&rst GPIO1_RESET>;
 231                         status = "disabled";
 232
 233                         portb: gpio-controller@0 {
 234                                 compatible = "snps,dw-apb-gpio-port";
 235                                 reg = <0>;
 236                                 gpio-controller;
 237                                 #gpio-cells = <2>;
 238                                 snps,nr-gpios = <24>;
 239                                 interrupt-controller;
 240                                 #interrupt-cells = <2>;
 241                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 242                         };
 243                 };
 244
 245                 nand: nand-controller@10b80000 {
 246                         compatible = "cdns,hp-nfc";
 247                         reg = <0x10b80000 0x10000>,
 248                                         <0x10840000 0x10000>;
 249                         reg-names = "reg", "sdma";
 250                         #address-cells = <1>;
 251                         #size-cells = <0>;
 252                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 253                         clocks = <&clkmgr AGILEX5_NAND_NF_CLK>;
 254                         cdns,board-delay-ps = <4830>;
 255                         status = "disabled";
 256                 };
 257
 258                 ocram: sram@0 {
 259                         compatible = "mmio-sram";
 260                         reg = <0x00000000 0x80000>;
 261                         ranges = <0 0 0x80000>;
 262                         #address-cells = <1>;
 263                         #size-cells = <1>;
 264                 };
 265
 266                 dmac0: dma-controller@10db0000 {
 267                         compatible = "snps,axi-dma-1.01a";
 268                         reg = <0x10db0000 0x500>;
 269                         clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
 270                                  <&clkmgr AGILEX5_L4_MP_CLK>;
 271                         clock-names = "core-clk", "cfgr-clk";
 272                         interrupt-parent = <&intc>;
 273                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 274                         #dma-cells = <1>;
 275                         dma-channels = <4>;
 276                         snps,dma-masters = <1>;
 277                         snps,data-width = <2>;
 278                         snps,block-size = <32767 32767 32767 32767>;
 279                         snps,priority = <0 1 2 3>;
 280                         snps,axi-max-burst-len = <8>;
 281                 };
 282
 283                 dmac1: dma-controller@10dc0000 {
 284                         compatible = "snps,axi-dma-1.01a";
 285                         reg = <0x10dc0000 0x500>;
 286                         clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
 287                                  <&clkmgr AGILEX5_L4_MP_CLK>;
 288                         clock-names = "core-clk", "cfgr-clk";
 289                         interrupt-parent = <&intc>;
 290                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 291                         #dma-cells = <1>;
 292                         dma-channels = <4>;
 293                         snps,dma-masters = <1>;
 294                         snps,data-width = <2>;
 295                         snps,block-size = <32767 32767 32767 32767>;
 296                         snps,priority = <0 1 2 3>;
 297                         snps,axi-max-burst-len = <8>;
 298                 };
 299
 300                 rst: rstmgr@10d11000 {
 301                         compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";
 302                         reg = <0x10d11000 0x1000>;
 303                         #reset-cells = <1>;
 304                 };
 305
 306                 spi0: spi@10da4000 {
 307                         compatible = "snps,dw-apb-ssi";
 308                         reg = <0x10da4000 0x1000>;
 309                         #address-cells = <1>;
 310                         #size-cells = <0>;
 311                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 312                         resets = <&rst SPIM0_RESET>;
 313                         reset-names = "spi";
 314                         reg-io-width = <4>;
 315                         num-cs = <4>;
 316                         clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
 317                         dmas = <&dmac0 2>, <&dmac0 3>;
 318                         dma-names = "tx", "rx";
 319                         status = "disabled";
 320
 321                 };
 322
 323                 spi1: spi@10da5000 {
 324                         compatible = "snps,dw-apb-ssi";
 325                         reg = <0x10da5000 0x1000>;
 326                         #address-cells = <1>;
 327                         #size-cells = <0>;
 328                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 329                         resets = <&rst SPIM1_RESET>;
 330                         reset-names = "spi";
 331                         reg-io-width = <4>;
 332                         num-cs = <4>;
 333                         clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
 334                         status = "disabled";
 335                 };
 336
 337                 sysmgr: sysmgr@10d12000 {
 338                         compatible = "altr,sys-mgr-s10","altr,sys-mgr";
 339                         reg = <0x10d12000 0x500>;
 340                 };
 341
 342                 timer0: timer0@10c03000 {
 343                         compatible = "snps,dw-apb-timer";
 344                         reg = <0x10c03000 0x100>;
 345                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 346                         clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
 347                         clock-names = "timer";
 348                 };
 349
 350                 timer1: timer1@10c03100 {
 351                         compatible = "snps,dw-apb-timer";
 352                         reg = <0x10c03100 0x100>;
 353                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 354                         clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
 355                         clock-names = "timer";
 356                 };
 357
 358                 timer2: timer2@10d00000 {
 359                         compatible = "snps,dw-apb-timer";
 360                         reg = <0x10d00000 0x100>;
 361                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 362                         clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
 363                         clock-names = "timer";
 364                 };
 365
 366                 timer3: timer3@10d00100 {
 367                         compatible = "snps,dw-apb-timer";
 368                         reg = <0x10d00100 0x100>;
 369                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 370                         clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
 371                         clock-names = "timer";
 372                 };
 373
 374                 uart0: serial@10c02000 {
 375                         compatible = "snps,dw-apb-uart";
 376                         reg = <0x10c02000 0x100>;
 377                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 378                         reg-shift = <2>;
 379                         reg-io-width = <4>;
 380                         resets = <&rst UART0_RESET>;
 381                         status = "disabled";
 382                         clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
 383                 };
 384
 385                 uart1: serial@10c02100 {
 386                         compatible = "snps,dw-apb-uart";
 387                         reg = <0x10c02100 0x100>;
 388                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 389                         reg-shift = <2>;
 390                         reg-io-width = <4>;
 391                         resets = <&rst UART1_RESET>;
 392                         status = "disabled";
 393                         clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
 394                 };
 395
 396                 usb0: usb@10b00000 {
 397                         compatible = "snps,dwc2";
 398                         reg = <0x10b00000 0x40000>;
 399                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 400                         phys = <&usbphy0>;
 401                         phy-names = "usb2-phy";
 402                         resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
 403                         reset-names = "dwc2", "dwc2-ecc";
 404                         clocks = <&clkmgr AGILEX5_USB2OTG_HCLK>;
 405                         clock-names = "otg";
 406                         status = "disabled";
 407                 };
 408
 409                 watchdog0: watchdog@10d00200 {
 410                         compatible = "snps,dw-wdt";
 411                         reg = <0x10d00200 0x100>;
 412                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 413                         resets = <&rst WATCHDOG0_RESET>;
 414                         clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
 415                         status = "disabled";
 416                 };
 417
 418                 watchdog1: watchdog@10d00300 {
 419                         compatible = "snps,dw-wdt";
 420                         reg = <0x10d00300 0x100>;
 421                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 422                         resets = <&rst WATCHDOG1_RESET>;
 423                         clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
 424                         status = "disabled";
 425                 };
 426
 427                 watchdog2: watchdog@10d00400 {
 428                         compatible = "snps,dw-wdt";
 429                         reg = <0x10d00400 0x100>;
 430                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 431                         resets = <&rst WATCHDOG2_RESET>;
 432                         clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
 433                         status = "disabled";
 434                 };
 435
 436                 watchdog3: watchdog@10d00500 {
 437                         compatible = "snps,dw-wdt";
 438                         reg = <0x10d00500 0x100>;
 439                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 440                         resets = <&rst WATCHDOG3_RESET>;
 441                         clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
 442                         status = "disabled";
 443                 };
 444
 445                 watchdog4: watchdog@10d00600 {
 446                         compatible = "snps,dw-wdt";
 447                         reg = <0x10d00600 0x100>;
 448                         interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 449                         resets = <&rst WATCHDOG4_RESET>;
 450                         clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
 451                         status = "disabled";
 452                 };
 453
 454                 qspi: spi@108d2000 {
 455                         compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
 456                         reg = <0x108d2000 0x100>,
 457                               <0x10900000 0x100000>;
 458                         #address-cells = <1>;
 459                         #size-cells = <0>;
 460                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 461                         cdns,fifo-depth = <128>;
 462                         cdns,fifo-width = <4>;
 463                         cdns,trigger-address = <0x00000000>;
 464                         clocks = <&qspi_clk>;
 465                         status = "disabled";
 466                 };
 467         };
 468 };