]> git.ipfire.org Git - thirdparty/u-boot.git/blob - src/arm64/mediatek/mt7986b-rfb.dts
Squashed 'dts/upstream/' content from commit aaba2d45dc2a
[thirdparty/u-boot.git] / src / arm64 / mediatek / mt7986b-rfb.dts
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7 /dts-v1/;
8 #include "mt7986b.dtsi"
9
10 / {
11 model = "MediaTek MT7986b RFB";
12 chassis-type = "embedded";
13 compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
14
15 aliases {
16 serial0 = &uart0;
17 };
18
19 chosen {
20 stdout-path = "serial0:115200n8";
21 };
22
23 memory@40000000 {
24 device_type = "memory";
25 reg = <0 0x40000000 0 0x40000000>;
26 };
27 };
28
29 &crypto {
30 status = "okay";
31 };
32
33 &eth {
34 status = "okay";
35
36 gmac0: mac@0 {
37 compatible = "mediatek,eth-mac";
38 reg = <0>;
39 phy-mode = "2500base-x";
40
41 fixed-link {
42 speed = <2500>;
43 full-duplex;
44 pause;
45 };
46 };
47
48 mdio: mdio-bus {
49 #address-cells = <1>;
50 #size-cells = <0>;
51
52 switch@0 {
53 compatible = "mediatek,mt7531";
54 reg = <31>;
55 reset-gpios = <&pio 5 0>;
56
57 ports {
58 #address-cells = <1>;
59 #size-cells = <0>;
60
61 port@0 {
62 reg = <0>;
63 label = "lan0";
64 };
65
66 port@1 {
67 reg = <1>;
68 label = "lan1";
69 };
70
71 port@2 {
72 reg = <2>;
73 label = "lan2";
74 };
75
76 port@3 {
77 reg = <3>;
78 label = "lan3";
79 };
80
81 port@4 {
82 reg = <4>;
83 label = "lan4";
84 };
85
86 port@6 {
87 reg = <6>;
88 label = "cpu";
89 ethernet = <&gmac0>;
90 phy-mode = "2500base-x";
91
92 fixed-link {
93 speed = <2500>;
94 full-duplex;
95 pause;
96 };
97 };
98 };
99 };
100 };
101 };
102
103 &pio {
104 spi_flash_pins: spi-flash-pins {
105 mux {
106 function = "spi";
107 groups = "spi0", "spi0_wp_hold";
108 };
109 };
110
111 spic_pins: spic-pins {
112 mux {
113 function = "spi";
114 groups = "spi1_2";
115 };
116 };
117
118 wf_2g_5g_pins: wf-2g-5g-pins {
119 mux {
120 function = "wifi";
121 groups = "wf_2g", "wf_5g";
122 };
123 conf {
124 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
125 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
126 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
127 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
128 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
129 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
130 "WF1_TOP_CLK", "WF1_TOP_DATA";
131 drive-strength = <4>;
132 };
133 };
134
135 wf_dbdc_pins: wf-dbdc-pins {
136 mux {
137 function = "wifi";
138 groups = "wf_dbdc";
139 };
140 conf {
141 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
142 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
143 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
144 "WF0_TOP_CLK", "WF0_TOP_DATA";
145 drive-strength = <4>;
146 };
147 };
148 };
149
150 &spi0 {
151 pinctrl-names = "default";
152 pinctrl-0 = <&spi_flash_pins>;
153 cs-gpios = <0>, <0>;
154 status = "okay";
155 spi_nand: spi_nand@0 {
156 compatible = "spi-nand";
157 reg = <0>;
158 spi-max-frequency = <10000000>;
159 spi-tx-buswidth = <4>;
160 spi-rx-buswidth = <4>;
161 };
162 };
163
164 &spi1 {
165 pinctrl-names = "default";
166 pinctrl-0 = <&spic_pins>;
167 cs-gpios = <0>, <0>;
168 status = "okay";
169 };
170
171 &ssusb {
172 status = "okay";
173 };
174
175 &uart0 {
176 status = "okay";
177 };
178
179 &usb_phy {
180 status = "okay";
181 };
182
183 &wifi {
184 status = "okay";
185 pinctrl-names = "default", "dbdc";
186 pinctrl-0 = <&wf_2g_5g_pins>;
187 pinctrl-1 = <&wf_dbdc_pins>;
188 };