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[thirdparty/u-boot.git] / src / arm64 / qcom / qdu1000.dtsi
1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13
14 / {
15 interrupt-parent = <&intc>;
16
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 chosen: chosen { };
21
22 cpus {
23 #address-cells = <2>;
24 #size-cells = <0>;
25
26 CPU0: cpu@0 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a55";
29 reg = <0x0 0x0>;
30 clocks = <&cpufreq_hw 0>;
31 enable-method = "psci";
32 power-domains = <&CPU_PD0>;
33 power-domain-names = "psci";
34 qcom,freq-domains = <&cpufreq_hw 0>;
35 next-level-cache = <&L2_0>;
36 L2_0: l2-cache {
37 compatible = "cache";
38 cache-level = <2>;
39 cache-unified;
40 next-level-cache = <&L3_0>;
41 L3_0: l3-cache {
42 compatible = "cache";
43 cache-level = <3>;
44 cache-unified;
45 };
46 };
47 };
48
49 CPU1: cpu@100 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a55";
52 reg = <0x0 0x100>;
53 clocks = <&cpufreq_hw 0>;
54 enable-method = "psci";
55 power-domains = <&CPU_PD1>;
56 power-domain-names = "psci";
57 qcom,freq-domains = <&cpufreq_hw 0>;
58 next-level-cache = <&L2_100>;
59 L2_100: l2-cache {
60 compatible = "cache";
61 cache-level = <2>;
62 cache-unified;
63 next-level-cache = <&L3_0>;
64 };
65 };
66
67 CPU2: cpu@200 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a55";
70 reg = <0x0 0x200>;
71 clocks = <&cpufreq_hw 0>;
72 enable-method = "psci";
73 power-domains = <&CPU_PD2>;
74 power-domain-names = "psci";
75 qcom,freq-domains = <&cpufreq_hw 0>;
76 next-level-cache = <&L2_200>;
77 L2_200: l2-cache {
78 compatible = "cache";
79 cache-level = <2>;
80 cache-unified;
81 next-level-cache = <&L3_0>;
82 };
83 };
84
85 CPU3: cpu@300 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a55";
88 reg = <0x0 0x300>;
89 clocks = <&cpufreq_hw 0>;
90 enable-method = "psci";
91 power-domains = <&CPU_PD3>;
92 power-domain-names = "psci";
93 qcom,freq-domains = <&cpufreq_hw 0>;
94 next-level-cache = <&L2_300>;
95 L2_300: l2-cache {
96 compatible = "cache";
97 cache-level = <2>;
98 cache-unified;
99 next-level-cache = <&L3_0>;
100 };
101 };
102
103 cpu-map {
104 cluster0 {
105 core0 {
106 cpu = <&CPU0>;
107 };
108
109 core1 {
110 cpu = <&CPU1>;
111 };
112
113 core2 {
114 cpu = <&CPU2>;
115 };
116
117 core3 {
118 cpu = <&CPU3>;
119 };
120 };
121 };
122 };
123
124 idle-states {
125 entry-method = "psci";
126
127 CPU_OFF: cpu-sleep-0 {
128 compatible = "arm,idle-state";
129 entry-latency-us = <274>;
130 exit-latency-us = <480>;
131 min-residency-us = <3934>;
132 arm,psci-suspend-param = <0x40000004>;
133 local-timer-stop;
134 };
135 };
136
137 domain-idle-states {
138 CLUSTER_SLEEP_0: cluster-sleep-0 {
139 compatible = "domain-idle-state";
140 entry-latency-us = <584>;
141 exit-latency-us = <2332>;
142 min-residency-us = <6118>;
143 arm,psci-suspend-param = <0x41000044>;
144 };
145
146 CLUSTER_SLEEP_1: cluster-sleep-1 {
147 compatible = "domain-idle-state";
148 entry-latency-us = <2893>;
149 exit-latency-us = <4023>;
150 min-residency-us = <9987>;
151 arm,psci-suspend-param = <0x41003344>;
152 };
153 };
154
155 firmware {
156 scm {
157 compatible = "qcom,scm-qdu1000", "qcom,scm";
158 };
159 };
160
161 mc_virt: interconnect-0 {
162 compatible = "qcom,qdu1000-mc-virt";
163 qcom,bcm-voters = <&apps_bcm_voter>;
164 #interconnect-cells = <2>;
165 };
166
167 clk_virt: interconnect-1 {
168 compatible = "qcom,qdu1000-clk-virt";
169 qcom,bcm-voters = <&apps_bcm_voter>;
170 #interconnect-cells = <2>;
171 };
172
173 memory@80000000 {
174 device_type = "memory";
175 /* We expect the bootloader to fill in the size */
176 reg = <0x0 0x80000000 0x0 0x0>;
177 };
178
179 pmu {
180 compatible = "arm,armv8-pmuv3";
181 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
182 };
183
184 psci {
185 compatible = "arm,psci-1.0";
186 method = "smc";
187
188 CPU_PD0: power-domain-cpu0 {
189 #power-domain-cells = <0>;
190 power-domains = <&CLUSTER_PD>;
191 domain-idle-states = <&CPU_OFF>;
192 };
193
194 CPU_PD1: power-domain-cpu1 {
195 #power-domain-cells = <0>;
196 power-domains = <&CLUSTER_PD>;
197 domain-idle-states = <&CPU_OFF>;
198 };
199
200 CPU_PD2: power-domain-cpu2 {
201 #power-domain-cells = <0>;
202 power-domains = <&CLUSTER_PD>;
203 domain-idle-states = <&CPU_OFF>;
204 };
205
206 CPU_PD3: power-domain-cpu3 {
207 #power-domain-cells = <0>;
208 power-domains = <&CLUSTER_PD>;
209 domain-idle-states = <&CPU_OFF>;
210 };
211
212 CLUSTER_PD: power-domain-cluster {
213 #power-domain-cells = <0>;
214 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>;
215 };
216 };
217
218 reserved_memory: reserved-memory {
219 #address-cells = <2>;
220 #size-cells = <2>;
221 ranges;
222
223 hyp_mem: hyp@80000000 {
224 reg = <0x0 0x80000000 0x0 0x600000>;
225 no-map;
226 };
227
228 xbl_dt_log_mem: xbl-dt-log@80600000 {
229 reg = <0x0 0x80600000 0x0 0x40000>;
230 no-map;
231 };
232
233 xbl_ramdump_mem: xbl-ramdump@80640000 {
234 reg = <0x0 0x80640000 0x0 0x1c0000>;
235 no-map;
236 };
237
238 aop_image_mem: aop-image@80800000 {
239 reg = <0x0 0x80800000 0x0 0x60000>;
240 no-map;
241 };
242
243 aop_cmd_db_mem: aop-cmd-db@80860000 {
244 compatible = "qcom,cmd-db";
245 reg = <0x0 0x80860000 0x0 0x20000>;
246 no-map;
247 };
248
249 aop_config_mem: aop-config@80880000 {
250 reg = <0x0 0x80880000 0x0 0x20000>;
251 no-map;
252 };
253
254 tme_crash_dump_mem: tme-crash-dump@808a0000 {
255 reg = <0x0 0x808a0000 0x0 0x40000>;
256 no-map;
257 };
258
259 tme_log_mem: tme-log@808e0000 {
260 reg = <0x0 0x808e0000 0x0 0x4000>;
261 no-map;
262 };
263
264 uefi_log_mem: uefi-log@808e4000 {
265 reg = <0x0 0x808e4000 0x0 0x10000>;
266 no-map;
267 };
268
269 smem_mem: smem@80900000 {
270 compatible = "qcom,smem";
271 reg = <0x0 0x80900000 0x0 0x200000>;
272 no-map;
273 hwlocks = <&tcsr_mutex 3>;
274 };
275
276 cpucp_fw_mem: cpucp-fw@80b00000 {
277 reg = <0x0 0x80b00000 0x0 0x100000>;
278 no-map;
279 };
280
281 xbl_sc_mem: memory@80c00000 {
282 reg = <0x0 0x80c00000 0x0 0x40000>;
283 no-map;
284 };
285
286 tz_stat_mem: tz-stat@81d00000 {
287 reg = <0x0 0x81d00000 0x0 0x100000>;
288 no-map;
289 };
290
291 tags_mem: tags@81e00000 {
292 reg = <0x0 0x81e00000 0x0 0x500000>;
293 no-map;
294 };
295
296 qtee_mem: qtee@82300000 {
297 reg = <0x0 0x82300000 0x0 0x500000>;
298 no-map;
299 };
300
301 ta_mem: ta@82800000 {
302 reg = <0x0 0x82800000 0x0 0xa00000>;
303 no-map;
304 };
305
306 fs1_mem: fs1@83200000 {
307 reg = <0x0 0x83200000 0x0 0x400000>;
308 no-map;
309 };
310
311 fs2_mem: fs2@83600000 {
312 reg = <0x0 0x83600000 0x0 0x400000>;
313 no-map;
314 };
315
316 fs3_mem: fs3@83a00000 {
317 reg = <0x0 0x83a00000 0x0 0x400000>;
318 no-map;
319 };
320
321 /* Linux kernel image is loaded at 0x83e00000 */
322
323 ipa_fw_mem: ipa-fw@8be00000 {
324 reg = <0x0 0x8be00000 0x0 0x10000>;
325 no-map;
326 };
327
328 ipa_gsi_mem: ipa-gsi@8be10000 {
329 reg = <0x0 0x8be10000 0x0 0x14000>;
330 no-map;
331 };
332
333 mpss_mem: mpss@8c000000 {
334 reg = <0x0 0x8c000000 0x0 0x12c00000>;
335 no-map;
336 };
337
338 q6_mpss_dtb_mem: q6-mpss-dtb@9ec00000 {
339 reg = <0x0 0x9ec00000 0x0 0x80000>;
340 no-map;
341 };
342
343 tenx_mem: tenx@a0000000 {
344 reg = <0x0 0xa0000000 0x0 0x19600000>;
345 no-map;
346 };
347
348 oem_tenx_mem: oem-tenx@b9600000 {
349 reg = <0x0 0xb9600000 0x0 0x6a00000>;
350 no-map;
351 };
352
353 tenx_q6_buffer_mem: tenx-q6-buffer@c0000000 {
354 reg = <0x0 0xc0000000 0x0 0x3200000>;
355 no-map;
356 };
357
358 ipa_buffer_mem: ipa-buffer@c3200000 {
359 reg = <0x0 0xc3200000 0x0 0x12c00000>;
360 no-map;
361 };
362 };
363
364 soc: soc@0 {
365 compatible = "simple-bus";
366 #address-cells = <2>;
367 #size-cells = <2>;
368 ranges = <0 0 0 0 0x10 0>;
369 dma-ranges = <0 0 0 0 0x10 0>;
370
371 gcc: clock-controller@80000 {
372 compatible = "qcom,qdu1000-gcc";
373 reg = <0x0 0x80000 0x0 0x1f4200>;
374 clocks = <&rpmhcc RPMH_CXO_CLK>,
375 <&sleep_clk>,
376 <0>,
377 <0>,
378 <0>;
379 #clock-cells = <1>;
380 #reset-cells = <1>;
381 #power-domain-cells = <1>;
382 };
383
384 gpi_dma0: dma-controller@900000 {
385 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
386 reg = <0x0 0x900000 0x0 0x60000>;
387 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
390 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
391 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
392 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
393 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
394 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
395 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
396 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
397 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
398 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
399 dma-channels = <12>;
400 dma-channel-mask = <0x3f>;
401 iommus = <&apps_smmu 0xf6 0x0>;
402 #dma-cells = <3>;
403 };
404
405 qupv3_id_0: geniqup@9c0000 {
406 compatible = "qcom,geni-se-qup";
407 reg = <0x0 0x9c0000 0x0 0x2000>;
408 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
409 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
410 clock-names = "m-ahb", "s-ahb";
411 iommus = <&apps_smmu 0xe3 0x0>;
412 interconnects = <&clk_virt MASTER_QUP_CORE_0 0
413 &clk_virt SLAVE_QUP_CORE_0 0>;
414 interconnect-names = "qup-core";
415
416 #address-cells = <2>;
417 #size-cells = <2>;
418 ranges;
419 status = "disabled";
420
421 uart0: serial@980000 {
422 compatible = "qcom,geni-uart";
423 reg = <0x0 0x980000 0x0 0x4000>;
424 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
425 clock-names = "se";
426 pinctrl-0 = <&qup_uart0_default>;
427 pinctrl-names = "default";
428 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
429 status = "disabled";
430 };
431
432 i2c1: i2c@984000 {
433 compatible = "qcom,geni-i2c";
434 reg = <0x0 0x984000 0x0 0x4000>;
435 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
436 clock-names = "se";
437 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
438 pinctrl-0 = <&qup_i2c1_data_clk>;
439 pinctrl-names = "default";
440 #address-cells = <1>;
441 #size-cells = <0>;
442 status = "disabled";
443 };
444
445 spi1: spi@984000 {
446 compatible = "qcom,geni-spi";
447 reg = <0x0 0x984000 0x0 0x4000>;
448 #address-cells = <1>;
449 #size-cells = <0>;
450 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
452 clock-names = "se";
453 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
454 pinctrl-names = "default";
455 status = "disabled";
456 };
457
458 i2c2: i2c@988000 {
459 compatible = "qcom,geni-i2c";
460 reg = <0x0 0x988000 0x0 0x4000>;
461 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
462 clock-names = "se";
463 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
464 pinctrl-0 = <&qup_i2c2_data_clk>;
465 pinctrl-names = "default";
466 #address-cells = <1>;
467 #size-cells = <0>;
468 status = "disabled";
469 };
470
471 spi2: spi@988000 {
472 compatible = "qcom,geni-spi";
473 reg = <0x0 0x988000 0x0 0x4000>;
474 #address-cells = <1>;
475 #size-cells = <0>;
476 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
478 clock-names = "se";
479 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
480 pinctrl-names = "default";
481 status = "disabled";
482 };
483
484 i2c3: i2c@98c000 {
485 compatible = "qcom,geni-i2c";
486 reg = <0x0 0x98c000 0x0 0x4000>;
487 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
488 clock-names = "se";
489 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
490 pinctrl-0 = <&qup_i2c3_data_clk>;
491 pinctrl-names = "default";
492 #address-cells = <1>;
493 #size-cells = <0>;
494 status = "disabled";
495 };
496
497 spi3: spi@98c000 {
498 compatible = "qcom,geni-spi";
499 reg = <0x0 0x98c000 0x0 0x4000>;
500 #address-cells = <1>;
501 #size-cells = <0>;
502 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
504 clock-names = "se";
505 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
506 pinctrl-names = "default";
507 status = "disabled";
508 };
509
510 i2c4: i2c@990000 {
511 compatible = "qcom,geni-i2c";
512 reg = <0x0 0x990000 0x0 0x4000>;
513 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
514 clock-names = "se";
515 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
516 pinctrl-0 = <&qup_i2c4_data_clk>;
517 pinctrl-names = "default";
518 #address-cells = <1>;
519 #size-cells = <0>;
520 status = "disabled";
521 };
522
523 spi4: spi@990000 {
524 compatible = "qcom,geni-spi";
525 reg = <0x0 0x990000 0x0 0x4000>;
526 #address-cells = <1>;
527 #size-cells = <0>;
528 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
530 clock-names = "se";
531 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
532 pinctrl-names = "default";
533 status = "disabled";
534 };
535
536 i2c5: i2c@994000 {
537 compatible = "qcom,geni-i2c";
538 reg = <0x0 0x994000 0x0 0x4000>;
539 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
540 clock-names = "se";
541 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
542 pinctrl-0 = <&qup_i2c5_data_clk>;
543 pinctrl-names = "default";
544 #address-cells = <1>;
545 #size-cells = <0>;
546 status = "disabled";
547 };
548
549 spi5: spi@994000 {
550 compatible = "qcom,geni-spi";
551 reg = <0x0 0x994000 0x0 0x4000>;
552 #address-cells = <1>;
553 #size-cells = <0>;
554 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
556 clock-names = "se";
557 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
558 pinctrl-names = "default";
559 status = "disabled";
560 };
561
562 i2c6: i2c@998000 {
563 compatible = "qcom,geni-i2c";
564 reg = <0x0 0x998000 0x0 0x4000>;
565 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
566 clock-names = "se";
567 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
568 pinctrl-0 = <&qup_i2c6_data_clk>;
569 pinctrl-names = "default";
570 #address-cells = <1>;
571 #size-cells = <0>;
572 status = "disabled";
573 };
574
575 spi6: spi@998000 {
576 compatible = "qcom,geni-spi";
577 reg = <0x0 0x998000 0x0 0x4000>;
578 #address-cells = <1>;
579 #size-cells = <0>;
580 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
582 clock-names = "se";
583 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
584 pinctrl-names = "default";
585 status = "disabled";
586 };
587
588 uart7: serial@99c000 {
589 compatible = "qcom,geni-debug-uart";
590 reg = <0x0 0x99c000 0x0 0x4000>;
591 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
592 clock-names = "se";
593 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
594 pinctrl-names = "default";
595 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
596 status = "disabled";
597 };
598 };
599
600 gpi_dma1: dma-controller@a00000 {
601 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
602 reg = <0x0 0xa00000 0x0 0x60000>;
603 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
615 dma-channels = <12>;
616 dma-channel-mask = <0x3f>;
617 iommus = <&apps_smmu 0x116 0x0>;
618 #dma-cells = <3>;
619 };
620
621 qupv3_id_1: geniqup@ac0000 {
622 compatible = "qcom,geni-se-qup";
623 reg = <0x0 0xac0000 0x0 0x2000>;
624 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
625 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
626 clock-names = "m-ahb", "s-ahb";
627 iommus = <&apps_smmu 0x103 0x0>;
628 #address-cells = <2>;
629 #size-cells = <2>;
630 ranges;
631 status = "disabled";
632
633 uart8: serial@a80000 {
634 compatible = "qcom,geni-uart";
635 reg = <0x0 0xa80000 0x0 0x4000>;
636 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
637 clock-names = "se";
638 pinctrl-0 = <&qup_uart8_default>;
639 pinctrl-names = "default";
640 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
641 #address-cells = <1>;
642 #size-cells = <0>;
643 status = "disabled";
644 };
645
646 i2c9: i2c@a84000 {
647 compatible = "qcom,geni-i2c";
648 reg = <0x0 0xa84000 0x0 0x4000>;
649 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
650 clock-names = "se";
651 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
652 pinctrl-0 = <&qup_i2c9_data_clk>;
653 pinctrl-names = "default";
654 #address-cells = <1>;
655 #size-cells = <0>;
656 status = "disabled";
657 };
658
659 spi9: spi@a84000 {
660 compatible = "qcom,geni-spi";
661 reg = <0x0 0xa84000 0x0 0x4000>;
662 #address-cells = <1>;
663 #size-cells = <0>;
664 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
665 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
666 clock-names = "se";
667 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
668 pinctrl-names = "default";
669 status = "disabled";
670 };
671
672 i2c10: i2c@a88000 {
673 compatible = "qcom,geni-i2c";
674 reg = <0x0 0xa88000 0x0 0x4000>;
675 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
676 clock-names = "se";
677 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
678 pinctrl-0 = <&qup_i2c10_data_clk>;
679 pinctrl-names = "default";
680 #address-cells = <1>;
681 #size-cells = <0>;
682 status = "disabled";
683 };
684
685 spi10: spi@a88000 {
686 compatible = "qcom,geni-spi";
687 reg = <0x0 0xa88000 0x0 0x4000>;
688 #address-cells = <1>;
689 #size-cells = <0>;
690 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
692 clock-names = "se";
693 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
694 pinctrl-names = "default";
695 status = "disabled";
696 };
697
698 i2c11: i2c@a8c000 {
699 compatible = "qcom,geni-i2c";
700 reg = <0x0 0xa8c000 0x0 0x4000>;
701 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
702 clock-names = "se";
703 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
704 pinctrl-0 = <&qup_i2c11_data_clk>;
705 pinctrl-names = "default";
706 #address-cells = <1>;
707 #size-cells = <0>;
708 status = "disabled";
709 };
710
711 spi11: spi@a8c000 {
712 compatible = "qcom,geni-spi";
713 reg = <0x0 0xa8c000 0x0 0x4000>;
714 #address-cells = <1>;
715 #size-cells = <0>;
716 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
718 clock-names = "se";
719 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
720 pinctrl-names = "default";
721 status = "disabled";
722 };
723
724 i2c12: i2c@a90000 {
725 compatible = "qcom,geni-i2c";
726 reg = <0x0 0xa90000 0x0 0x4000>;
727 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
728 clock-names = "se";
729 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
730 pinctrl-0 = <&qup_i2c12_data_clk>;
731 pinctrl-names = "default";
732 #address-cells = <1>;
733 #size-cells = <0>;
734 status = "disabled";
735 };
736
737 spi12: spi@a90000 {
738 compatible = "qcom,geni-spi";
739 reg = <0x0 0xa90000 0x0 0x4000>;
740 #address-cells = <1>;
741 #size-cells = <0>;
742 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
744 clock-names = "se";
745 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
746 pinctrl-names = "default";
747 status = "disabled";
748 };
749
750 i2c13: i2c@a94000 {
751 compatible = "qcom,geni-i2c";
752 reg = <0x0 0xa94000 0x0 0x4000>;
753 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
754 clock-names = "se";
755 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
756 pinctrl-0 = <&qup_i2c13_data_clk>;
757 pinctrl-names = "default";
758 #address-cells = <1>;
759 #size-cells = <0>;
760 status = "disabled";
761 };
762
763 uart13: serial@a94000 {
764 compatible = "qcom,geni-uart";
765 reg = <0x0 0xa94000 0x0 0x4000>;
766 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
767 clock-names = "se";
768 pinctrl-0 = <&qup_uart13_default>;
769 pinctrl-names = "default";
770 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
771 #address-cells = <1>;
772 #size-cells = <0>;
773 status = "disabled";
774 };
775
776 spi13: spi@a94000 {
777 compatible = "qcom,geni-spi";
778 reg = <0x0 0xa94000 0x0 0x4000>;
779 #address-cells = <1>;
780 #size-cells = <0>;
781 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
783 clock-names = "se";
784 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
785 pinctrl-names = "default";
786 status = "disabled";
787 };
788
789 i2c14: i2c@a98000 {
790 compatible = "qcom,geni-i2c";
791 reg = <0x0 0xa98000 0x0 0x4000>;
792 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
793 clock-names = "se";
794 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
795 pinctrl-0 = <&qup_i2c14_data_clk>;
796 pinctrl-names = "default";
797 #address-cells = <1>;
798 #size-cells = <0>;
799 status = "disabled";
800 };
801
802 spi14: spi@a98000 {
803 compatible = "qcom,geni-spi";
804 reg = <0x0 0xa98000 0x0 0x4000>;
805 #address-cells = <1>;
806 #size-cells = <0>;
807 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
808 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
809 clock-names = "se";
810 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
811 pinctrl-names = "default";
812 status = "disabled";
813 };
814
815 i2c15: i2c@a9c000 {
816 compatible = "qcom,geni-i2c";
817 reg = <0x0 0xa9c000 0x0 0x4000>;
818 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
819 clock-names = "se";
820 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
821 pinctrl-0 = <&qup_i2c15_data_clk>;
822 pinctrl-names = "default";
823 #address-cells = <1>;
824 #size-cells = <0>;
825 status = "disabled";
826 };
827
828 spi15: spi@a9c000 {
829 compatible = "qcom,geni-spi";
830 reg = <0x0 0xa9c000 0x0 0x4000>;
831 #address-cells = <1>;
832 #size-cells = <0>;
833 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
835 clock-names = "se";
836 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
837 pinctrl-names = "default";
838 status = "disabled";
839 };
840 };
841
842 system_noc: interconnect@1640000 {
843 compatible = "qcom,qdu1000-system-noc";
844 reg = <0x0 0x1640000 0x0 0x45080>;
845 qcom,bcm-voters = <&apps_bcm_voter>;
846 #interconnect-cells = <2>;
847 };
848
849 tcsr_mutex: hwlock@1f40000 {
850 compatible = "qcom,tcsr-mutex";
851 reg = <0x0 0x1f40000 0x0 0x20000>;
852 #hwlock-cells = <1>;
853 };
854
855 sdhc: mmc@8804000 {
856 compatible = "qcom,qdu1000-sdhci", "qcom,sdhci-msm-v5";
857 reg = <0x0 0x08804000 0x0 0x1000>,
858 <0x0 0x08805000 0x0 0x1000>;
859 reg-names = "hc", "cqhci";
860
861 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
862 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
863 interrupt-names = "hc_irq", "pwr_irq";
864
865 clocks = <&gcc GCC_SDCC5_AHB_CLK>,
866 <&gcc GCC_SDCC5_APPS_CLK>,
867 <&rpmhcc RPMH_CXO_CLK>;
868 clock-names = "iface",
869 "core",
870 "xo";
871
872 resets = <&gcc GCC_SDCC5_BCR>;
873
874 interconnects = <&system_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
875 <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_SDCC_2 0>;
876 interconnect-names = "sdhc-ddr", "cpu-sdhc";
877 power-domains = <&rpmhpd QDU1000_CX>;
878 operating-points-v2 = <&sdhc1_opp_table>;
879
880 iommus = <&apps_smmu 0x80 0x0>;
881 dma-coherent;
882
883 bus-width = <8>;
884
885 qcom,dll-config = <0x0007642c>;
886 qcom,ddr-config = <0x80040868>;
887
888 status = "disabled";
889
890 sdhc1_opp_table: opp-table {
891 compatible = "operating-points-v2";
892
893 opp-384000000 {
894 opp-hz = /bits/ 64 <384000000>;
895 required-opps = <&rpmhpd_opp_nom>;
896 opp-peak-kBps = <6528000 1652800>;
897 opp-avg-kBps = <400000 0>;
898 };
899 };
900 };
901
902 pdc: interrupt-controller@b220000 {
903 compatible = "qcom,qdu1000-pdc", "qcom,pdc";
904 reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
905 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
906 <94 609 31>, <125 63 1>;
907 #interrupt-cells = <2>;
908 interrupt-parent = <&intc>;
909 interrupt-controller;
910 };
911
912 spmi_bus: spmi@c400000 {
913 compatible = "qcom,spmi-pmic-arb";
914 reg = <0x0 0xc400000 0x0 0x3000>,
915 <0x0 0xc500000 0x0 0x400000>,
916 <0x0 0xc440000 0x0 0x80000>,
917 <0x0 0xc4c0000 0x0 0x10000>,
918 <0x0 0xc42d000 0x0 0x4000>;
919 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
920 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
921 interrupt-names = "periph_irq";
922 qcom,ee = <0>;
923 qcom,channel = <0>;
924 #address-cells = <2>;
925 #size-cells = <0>;
926 interrupt-controller;
927 #interrupt-cells = <4>;
928 };
929
930 tlmm: pinctrl@f000000 {
931 compatible = "qcom,qdu1000-tlmm";
932 reg = <0x0 0xf000000 0x0 0x1000000>;
933 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
934 gpio-controller;
935 #gpio-cells = <2>;
936 interrupt-controller;
937 #interrupt-cells = <2>;
938 gpio-ranges = <&tlmm 0 0 151>;
939 wakeup-parent = <&pdc>;
940
941 qup_uart0_default: qup-uart0-default-state {
942 pins = "gpio6", "gpio7", "gpio8", "gpio9";
943 function = "qup00";
944 };
945
946 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
947 pins = "gpio10", "gpio11";
948 function = "qup01";
949 };
950
951 qup_spi1_data_clk: qup-spi1-data-clk-state {
952 pins = "gpio10", "gpio11", "gpio12";
953 function = "qup01";
954 };
955
956 qup_spi1_cs: qup-spi1-cs-state {
957 pins = "gpio13";
958 function = "gpio";
959 };
960
961 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
962 pins = "gpio12", "gpio13";
963 function = "qup02";
964 };
965
966 qup_spi2_data_clk: qup-spi2-data-clk-state {
967 pins = "gpio12", "gpio13", "gpio10";
968 function = "qup02";
969 };
970
971 qup_spi2_cs: qup-spi2-cs-state {
972 pins = "gpio11";
973 function = "gpio";
974 };
975
976 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
977 pins = "gpio14", "gpio15";
978 function = "qup03";
979 };
980
981 qup_spi3_data_clk: qup-spi3-data-clk-state {
982 pins = "gpio14", "gpio15", "gpio16";
983 function = "qup03";
984 };
985
986 qup_spi3_cs: qup-spi3-cs-state {
987 pins = "gpio17";
988 function = "gpio";
989 };
990
991 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
992 pins = "gpio16", "gpio17";
993 function = "qup04";
994 };
995
996 qup_spi4_data_clk: qup-spi4-data-clk-state {
997 pins = "gpio16", "gpio17", "gpio14";
998 function = "qup04";
999 };
1000
1001 qup_spi4_cs: qup-spi4-cs-state {
1002 pins = "gpio15";
1003 function = "gpio";
1004 };
1005
1006 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
1007 pins = "gpio130", "gpio131";
1008 function = "qup05";
1009 };
1010
1011 qup_spi5_data_clk: qup-spi5-data-clk-state {
1012 pins = "gpio130", "gpio131", "gpio132";
1013 function = "qup05";
1014 };
1015
1016 qup_spi5_cs: qup-spi5-cs-state {
1017 pins = "gpio133";
1018 function = "gpio";
1019 };
1020
1021 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
1022 pins = "gpio132", "gpio133";
1023 function = "qup06";
1024 };
1025
1026 qup_spi6_data_clk: qup-spi6-data-clk-state {
1027 pins = "gpio132", "gpio133", "gpio130";
1028 function = "qup06";
1029 };
1030
1031 qup_spi6_cs: qup-spi6-cs-state {
1032 pins = "gpio131";
1033 function = "gpio";
1034 };
1035
1036 qup_uart7_rx: qup-uart7-rx-state {
1037 pins = "gpio135";
1038 function = "qup07";
1039 };
1040
1041 qup_uart7_tx: qup-uart7-tx-state {
1042 pins = "gpio134";
1043 function = "qup07";
1044 };
1045
1046 qup_uart8_default: qup-uart8-default-state {
1047 pins = "gpio18", "gpio19", "gpio20", "gpio21";
1048 function = "qup10";
1049 };
1050
1051 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
1052 pins = "gpio22", "gpio23";
1053 function = "qup11";
1054 };
1055
1056 qup_spi9_data_clk: qup-spi9-data-clk-state {
1057 pins = "gpio22", "gpio23", "gpio24";
1058 function = "qup11";
1059 };
1060
1061 qup_spi9_cs: qup-spi9-cs-state {
1062 pins = "gpio25";
1063 function = "gpio";
1064 };
1065
1066 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
1067 pins = "gpio24", "gpio25";
1068 function = "qup12";
1069 };
1070
1071 qup_spi10_data_clk: qup-spi10-data-clk-state {
1072 pins = "gpio24", "gpio25", "gpio22";
1073 function = "qup12";
1074 };
1075
1076 qup_spi10_cs: qup-spi10-cs-state {
1077 pins = "gpio23";
1078 function = "gpio";
1079 };
1080
1081 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
1082 pins = "gpio26", "gpio27";
1083 function = "qup13";
1084 };
1085
1086 qup_spi11_data_clk: qup-spi11-data-clk-state {
1087 pins = "gpio26", "gpio27", "gpio28";
1088 function = "qup13";
1089 };
1090
1091 qup_spi11_cs: qup-spi11-cs-state {
1092 pins = "gpio29";
1093 function = "gpio";
1094 };
1095
1096 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
1097 pins = "gpio28", "gpio29";
1098 function = "qup14";
1099 };
1100
1101 qup_spi12_data_clk: qup-spi12-data-clk-state {
1102 pins = "gpio28", "gpio29", "gpio26";
1103 function = "qup14";
1104 };
1105
1106 qup_spi12_cs: qup-spi12-cs-state {
1107 pins = "gpio27";
1108 function = "gpio";
1109 };
1110
1111 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
1112 pins = "gpio30", "gpio31";
1113 function = "qup15";
1114 };
1115
1116 qup_spi13_data_clk: qup-spi13-data-clk-state {
1117 pins = "gpio30", "gpio31", "gpio32";
1118 function = "qup15";
1119 };
1120
1121 qup_spi13_cs: qup-spi13-cs-state {
1122 pins = "gpio33";
1123 function = "gpio";
1124 };
1125
1126 qup_uart13_default: qup-uart13-default-state {
1127 pins = "gpio30", "gpio31", "gpio32", "gpio33";
1128 function = "qup15";
1129 };
1130
1131 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
1132 pins = "gpio34", "gpio35";
1133 function = "qup16";
1134 };
1135
1136 qup_spi14_data_clk: qup-spi14-data-clk-state {
1137 pins = "gpio34", "gpio35", "gpio36";
1138 function = "qup16";
1139 };
1140
1141 qup_spi14_cs: qup-spi14-cs-state {
1142 pins = "gpio37", "gpio38";
1143 function = "gpio";
1144 };
1145
1146 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
1147 pins = "gpio40", "gpio41";
1148 function = "qup17";
1149 };
1150
1151 qup_spi15_data_clk: qup-spi15-data-clk-state {
1152 pins = "gpio40", "gpio41", "gpio30";
1153 function = "qup17";
1154 };
1155
1156 qup_spi15_cs: qup-spi15-cs-state {
1157 pins = "gpio31";
1158 function = "gpio";
1159 };
1160
1161 sdc_on_state: sdc-on-state {
1162 clk-pins {
1163 pins = "sdc1_clk";
1164 drive-strength = <16>;
1165 bias-disable;
1166 };
1167
1168 cmd-pins {
1169 pins = "sdc1_cmd";
1170 drive-strength = <10>;
1171 bias-pull-up;
1172 };
1173
1174 data-pins {
1175 pins = "sdc1_data";
1176 drive-strength = <10>;
1177 bias-pull-up;
1178 };
1179
1180 rclk-pins {
1181 pins = "sdc1_rclk";
1182 bias-pull-down;
1183 };
1184 };
1185
1186 sdc_off_state: sdc-off-state {
1187 clk-pins {
1188 pins = "sdc1_clk";
1189 drive-strength = <2>;
1190 bias-disable;
1191 };
1192
1193 cmd-pins {
1194 pins = "sdc1_cmd";
1195 drive-strength = <2>;
1196 bias-pull-up;
1197 };
1198
1199 data-pins {
1200 pins = "sdc1_data";
1201 drive-strength = <2>;
1202 bias-pull-up;
1203 };
1204
1205 rclk-pins {
1206 pins = "sdc1_rclk";
1207 bias-pull-down;
1208 };
1209 };
1210 };
1211
1212 sram@14680000 {
1213 compatible = "qcom,qdu1000-imem", "syscon", "simple-mfd";
1214 reg = <0 0x14680000 0 0x1000>;
1215 ranges = <0 0 0x14680000 0x1000>;
1216 #address-cells = <1>;
1217 #size-cells = <1>;
1218
1219 pil-reloc@94c {
1220 compatible = "qcom,pil-reloc-info";
1221 reg = <0x94c 0xc8>;
1222 };
1223 };
1224
1225 apps_smmu: iommu@15000000 {
1226 compatible = "qcom,qdu1000-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1227 reg = <0x0 0x15000000 0x0 0x100000>;
1228 #iommu-cells = <2>;
1229 #global-interrupts = <2>;
1230 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1231 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
1232 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1235 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1236 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
1237 <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
1238 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1239 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1240 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1241 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1242 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1243 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1244 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1246 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1247 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1252 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1253 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1254 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1255 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1256 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1257 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1258 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1259 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1260 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1261 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1262 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1263 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1265 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1266 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1278 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
1279 };
1280
1281 intc: interrupt-controller@17200000 {
1282 compatible = "arm,gic-v3";
1283 reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
1284 <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */
1285 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1286 #interrupt-cells = <3>;
1287 interrupt-controller;
1288 #redistributor-regions = <1>;
1289 redistributor-stride = <0x0 0x20000>;
1290 };
1291
1292 timer@17420000 {
1293 compatible = "arm,armv7-timer-mem";
1294 reg = <0x0 0x17420000 0x0 0x1000>;
1295 #address-cells = <1>;
1296 #size-cells = <1>;
1297 ranges = <0x0 0x0 0x0 0x20000000>;
1298
1299 frame@17421000 {
1300 reg = <0x17421000 0x1000>,
1301 <0x17422000 0x1000>;
1302 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1303 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1304 frame-number = <0>;
1305 };
1306
1307 frame@17423000 {
1308 reg = <0x17423000 0x1000>;
1309 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1310 frame-number = <1>;
1311 status = "disabled";
1312 };
1313
1314 frame@17425000 {
1315 reg = <0x17425000 0x1000>,
1316 <0x17426000 0x1000>;
1317 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1318 frame-number = <2>;
1319 status = "disabled";
1320 };
1321
1322 frame@17427000 {
1323 reg = <0x17427000 0x1000>;
1324 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1325 frame-number = <3>;
1326 status = "disabled";
1327 };
1328
1329 frame@17429000 {
1330 reg = <0x17429000 0x1000>;
1331 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1332 frame-number = <4>;
1333 status = "disabled";
1334 };
1335
1336 frame@1742b000 {
1337 reg = <0x1742b000 0x1000>;
1338 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1339 frame-number = <5>;
1340 status = "disabled";
1341 };
1342
1343 frame@1742d000 {
1344 reg = <0x1742d000 0x1000>;
1345 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1346 frame-number = <6>;
1347 status = "disabled";
1348 };
1349 };
1350
1351 apps_rsc: rsc@17a00000 {
1352 compatible = "qcom,rpmh-rsc";
1353 reg = <0x0 0x17a00000 0x0 0x10000>,
1354 <0x0 0x17a10000 0x0 0x10000>,
1355 <0x0 0x17a20000 0x0 0x10000>;
1356 reg-names = "drv-0", "drv-1", "drv-2";
1357 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1358 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
1359 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1360 qcom,tcs-offset = <0xd00>;
1361 qcom,drv-id = <2>;
1362 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
1363 <WAKE_TCS 3>, <CONTROL_TCS 0>;
1364 label = "apps_rsc";
1365 power-domains = <&CLUSTER_PD>;
1366
1367 apps_bcm_voter: bcm-voter {
1368 compatible = "qcom,bcm-voter";
1369 };
1370
1371 rpmhcc: clock-controller {
1372 compatible = "qcom,qdu1000-rpmh-clk";
1373 clocks = <&xo_board>;
1374 clock-names = "xo";
1375 #clock-cells = <1>;
1376 };
1377
1378 rpmhpd: power-controller {
1379 compatible = "qcom,qdu1000-rpmhpd";
1380 #power-domain-cells = <1>;
1381 operating-points-v2 = <&rpmhpd_opp_table>;
1382
1383 rpmhpd_opp_table: opp-table {
1384 compatible = "operating-points-v2";
1385
1386 rpmhpd_opp_ret: opp1 {
1387 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1388 };
1389
1390 rpmhpd_opp_min_svs: opp2 {
1391 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1392 };
1393
1394 rpmhpd_opp_low_svs: opp3 {
1395 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1396 };
1397
1398 rpmhpd_opp_svs: opp4 {
1399 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1400 };
1401
1402 rpmhpd_opp_svs_l1: opp5 {
1403 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1404 };
1405
1406 rpmhpd_opp_nom: opp6 {
1407 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1408 };
1409
1410 rpmhpd_opp_nom_l1: opp7 {
1411 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1412 };
1413
1414 rpmhpd_opp_nom_l2: opp8 {
1415 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1416 };
1417
1418 rpmhpd_opp_turbo: opp9 {
1419 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1420 };
1421
1422 rpmhpd_opp_turbo_l1: opp10 {
1423 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1424 };
1425 };
1426 };
1427 };
1428
1429 cpufreq_hw: cpufreq@17d90000 {
1430 compatible = "qcom,qdu1000-cpufreq-epss", "qcom,cpufreq-epss";
1431 reg = <0x0 0x17d90000 0x0 0x1000>, <0x0 0x17d91000 0x0 0x1000>;
1432 reg-names = "freq-domain0", "freq-domain1";
1433 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
1434 clock-names = "xo", "alternate";
1435 #freq-domain-cells = <1>;
1436 #clock-cells = <1>;
1437 };
1438
1439 gem_noc: interconnect@19100000 {
1440 compatible = "qcom,qdu1000-gem-noc";
1441 reg = <0x0 0x19100000 0x0 0xB8080>;
1442 qcom,bcm-voters = <&apps_bcm_voter>;
1443 #interconnect-cells = <2>;
1444 };
1445
1446 system-cache-controller@19200000 {
1447 compatible = "qcom,qdu1000-llcc";
1448 reg = <0 0x19200000 0 0xd80000>,
1449 <0 0x1a200000 0 0x80000>,
1450 <0 0x221c8128 0 0x4>;
1451 reg-names = "llcc_base",
1452 "llcc_broadcast_base",
1453 "multi_channel_register";
1454 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1455 multi-ch-bit-off = <24 2>;
1456 };
1457 };
1458
1459 timer {
1460 compatible = "arm,armv8-timer";
1461 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1462 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1463 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1464 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1465 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1466 };
1467 };
"Das U-Boot" Source Tree