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Squashed 'dts/upstream/' changes from aaba2d45dc2a..b35b9bd1d4ee
[thirdparty/u-boot.git] / src / arm64 / qcom / qdu1000.dtsi
1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13
14 / {
15 interrupt-parent = <&intc>;
16
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 chosen: chosen { };
21
22 cpus {
23 #address-cells = <2>;
24 #size-cells = <0>;
25
26 CPU0: cpu@0 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a55";
29 reg = <0x0 0x0>;
30 clocks = <&cpufreq_hw 0>;
31 enable-method = "psci";
32 power-domains = <&CPU_PD0>;
33 power-domain-names = "psci";
34 qcom,freq-domains = <&cpufreq_hw 0>;
35 next-level-cache = <&L2_0>;
36 L2_0: l2-cache {
37 compatible = "cache";
38 cache-level = <2>;
39 cache-unified;
40 next-level-cache = <&L3_0>;
41 L3_0: l3-cache {
42 compatible = "cache";
43 cache-level = <3>;
44 cache-unified;
45 };
46 };
47 };
48
49 CPU1: cpu@100 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a55";
52 reg = <0x0 0x100>;
53 clocks = <&cpufreq_hw 0>;
54 enable-method = "psci";
55 power-domains = <&CPU_PD1>;
56 power-domain-names = "psci";
57 qcom,freq-domains = <&cpufreq_hw 0>;
58 next-level-cache = <&L2_100>;
59 L2_100: l2-cache {
60 compatible = "cache";
61 cache-level = <2>;
62 cache-unified;
63 next-level-cache = <&L3_0>;
64 };
65 };
66
67 CPU2: cpu@200 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a55";
70 reg = <0x0 0x200>;
71 clocks = <&cpufreq_hw 0>;
72 enable-method = "psci";
73 power-domains = <&CPU_PD2>;
74 power-domain-names = "psci";
75 qcom,freq-domains = <&cpufreq_hw 0>;
76 next-level-cache = <&L2_200>;
77 L2_200: l2-cache {
78 compatible = "cache";
79 cache-level = <2>;
80 cache-unified;
81 next-level-cache = <&L3_0>;
82 };
83 };
84
85 CPU3: cpu@300 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a55";
88 reg = <0x0 0x300>;
89 clocks = <&cpufreq_hw 0>;
90 enable-method = "psci";
91 power-domains = <&CPU_PD3>;
92 power-domain-names = "psci";
93 qcom,freq-domains = <&cpufreq_hw 0>;
94 next-level-cache = <&L2_300>;
95 L2_300: l2-cache {
96 compatible = "cache";
97 cache-level = <2>;
98 cache-unified;
99 next-level-cache = <&L3_0>;
100 };
101 };
102
103 cpu-map {
104 cluster0 {
105 core0 {
106 cpu = <&CPU0>;
107 };
108
109 core1 {
110 cpu = <&CPU1>;
111 };
112
113 core2 {
114 cpu = <&CPU2>;
115 };
116
117 core3 {
118 cpu = <&CPU3>;
119 };
120 };
121 };
122 };
123
124 idle-states {
125 entry-method = "psci";
126
127 CPU_OFF: cpu-sleep-0 {
128 compatible = "arm,idle-state";
129 entry-latency-us = <274>;
130 exit-latency-us = <480>;
131 min-residency-us = <3934>;
132 arm,psci-suspend-param = <0x40000004>;
133 local-timer-stop;
134 };
135 };
136
137 domain-idle-states {
138 CLUSTER_SLEEP_0: cluster-sleep-0 {
139 compatible = "domain-idle-state";
140 entry-latency-us = <584>;
141 exit-latency-us = <2332>;
142 min-residency-us = <6118>;
143 arm,psci-suspend-param = <0x41000044>;
144 };
145
146 CLUSTER_SLEEP_1: cluster-sleep-1 {
147 compatible = "domain-idle-state";
148 entry-latency-us = <2893>;
149 exit-latency-us = <4023>;
150 min-residency-us = <9987>;
151 arm,psci-suspend-param = <0x41003344>;
152 };
153 };
154
155 firmware {
156 scm {
157 compatible = "qcom,scm-qdu1000", "qcom,scm";
158 };
159 };
160
161 mc_virt: interconnect-0 {
162 compatible = "qcom,qdu1000-mc-virt";
163 qcom,bcm-voters = <&apps_bcm_voter>;
164 #interconnect-cells = <2>;
165 };
166
167 clk_virt: interconnect-1 {
168 compatible = "qcom,qdu1000-clk-virt";
169 qcom,bcm-voters = <&apps_bcm_voter>;
170 #interconnect-cells = <2>;
171 };
172
173 memory@80000000 {
174 device_type = "memory";
175 /* We expect the bootloader to fill in the size */
176 reg = <0x0 0x80000000 0x0 0x0>;
177 };
178
179 pmu {
180 compatible = "arm,armv8-pmuv3";
181 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
182 };
183
184 psci {
185 compatible = "arm,psci-1.0";
186 method = "smc";
187
188 CPU_PD0: power-domain-cpu0 {
189 #power-domain-cells = <0>;
190 power-domains = <&CLUSTER_PD>;
191 domain-idle-states = <&CPU_OFF>;
192 };
193
194 CPU_PD1: power-domain-cpu1 {
195 #power-domain-cells = <0>;
196 power-domains = <&CLUSTER_PD>;
197 domain-idle-states = <&CPU_OFF>;
198 };
199
200 CPU_PD2: power-domain-cpu2 {
201 #power-domain-cells = <0>;
202 power-domains = <&CLUSTER_PD>;
203 domain-idle-states = <&CPU_OFF>;
204 };
205
206 CPU_PD3: power-domain-cpu3 {
207 #power-domain-cells = <0>;
208 power-domains = <&CLUSTER_PD>;
209 domain-idle-states = <&CPU_OFF>;
210 };
211
212 CLUSTER_PD: power-domain-cluster {
213 #power-domain-cells = <0>;
214 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>;
215 };
216 };
217
218 reserved_memory: reserved-memory {
219 #address-cells = <2>;
220 #size-cells = <2>;
221 ranges;
222
223 hyp_mem: hyp@80000000 {
224 reg = <0x0 0x80000000 0x0 0x600000>;
225 no-map;
226 };
227
228 xbl_dt_log_mem: xbl-dt-log@80600000 {
229 reg = <0x0 0x80600000 0x0 0x40000>;
230 no-map;
231 };
232
233 xbl_ramdump_mem: xbl-ramdump@80640000 {
234 reg = <0x0 0x80640000 0x0 0x1c0000>;
235 no-map;
236 };
237
238 aop_image_mem: aop-image@80800000 {
239 reg = <0x0 0x80800000 0x0 0x60000>;
240 no-map;
241 };
242
243 aop_cmd_db_mem: aop-cmd-db@80860000 {
244 compatible = "qcom,cmd-db";
245 reg = <0x0 0x80860000 0x0 0x20000>;
246 no-map;
247 };
248
249 aop_config_mem: aop-config@80880000 {
250 reg = <0x0 0x80880000 0x0 0x20000>;
251 no-map;
252 };
253
254 tme_crash_dump_mem: tme-crash-dump@808a0000 {
255 reg = <0x0 0x808a0000 0x0 0x40000>;
256 no-map;
257 };
258
259 tme_log_mem: tme-log@808e0000 {
260 reg = <0x0 0x808e0000 0x0 0x4000>;
261 no-map;
262 };
263
264 uefi_log_mem: uefi-log@808e4000 {
265 reg = <0x0 0x808e4000 0x0 0x10000>;
266 no-map;
267 };
268
269 smem_mem: smem@80900000 {
270 compatible = "qcom,smem";
271 reg = <0x0 0x80900000 0x0 0x200000>;
272 no-map;
273 hwlocks = <&tcsr_mutex 3>;
274 };
275
276 cpucp_fw_mem: cpucp-fw@80b00000 {
277 reg = <0x0 0x80b00000 0x0 0x100000>;
278 no-map;
279 };
280
281 xbl_sc_mem: memory@80c00000 {
282 reg = <0x0 0x80c00000 0x0 0x40000>;
283 no-map;
284 };
285
286 tz_stat_mem: tz-stat@81d00000 {
287 reg = <0x0 0x81d00000 0x0 0x100000>;
288 no-map;
289 };
290
291 tags_mem: tags@81e00000 {
292 reg = <0x0 0x81e00000 0x0 0x500000>;
293 no-map;
294 };
295
296 qtee_mem: qtee@82300000 {
297 reg = <0x0 0x82300000 0x0 0x500000>;
298 no-map;
299 };
300
301 ta_mem: ta@82800000 {
302 reg = <0x0 0x82800000 0x0 0xa00000>;
303 no-map;
304 };
305
306 fs1_mem: fs1@83200000 {
307 reg = <0x0 0x83200000 0x0 0x400000>;
308 no-map;
309 };
310
311 fs2_mem: fs2@83600000 {
312 reg = <0x0 0x83600000 0x0 0x400000>;
313 no-map;
314 };
315
316 fs3_mem: fs3@83a00000 {
317 reg = <0x0 0x83a00000 0x0 0x400000>;
318 no-map;
319 };
320
321 /* Linux kernel image is loaded at 0x83e00000 */
322
323 ipa_fw_mem: ipa-fw@8be00000 {
324 reg = <0x0 0x8be00000 0x0 0x10000>;
325 no-map;
326 };
327
328 ipa_gsi_mem: ipa-gsi@8be10000 {
329 reg = <0x0 0x8be10000 0x0 0x14000>;
330 no-map;
331 };
332
333 mpss_mem: mpss@8c000000 {
334 reg = <0x0 0x8c000000 0x0 0x12c00000>;
335 no-map;
336 };
337
338 q6_mpss_dtb_mem: q6-mpss-dtb@9ec00000 {
339 reg = <0x0 0x9ec00000 0x0 0x80000>;
340 no-map;
341 };
342
343 tenx_mem: tenx@a0000000 {
344 reg = <0x0 0xa0000000 0x0 0x19600000>;
345 no-map;
346 };
347
348 oem_tenx_mem: oem-tenx@b9600000 {
349 reg = <0x0 0xb9600000 0x0 0x6a00000>;
350 no-map;
351 };
352
353 tenx_q6_buffer_mem: tenx-q6-buffer@c0000000 {
354 reg = <0x0 0xc0000000 0x0 0x3200000>;
355 no-map;
356 };
357
358 ipa_buffer_mem: ipa-buffer@c3200000 {
359 reg = <0x0 0xc3200000 0x0 0x12c00000>;
360 no-map;
361 };
362 };
363
364 soc: soc@0 {
365 compatible = "simple-bus";
366 #address-cells = <2>;
367 #size-cells = <2>;
368 ranges = <0 0 0 0 0x10 0>;
369 dma-ranges = <0 0 0 0 0x10 0>;
370
371 gcc: clock-controller@80000 {
372 compatible = "qcom,qdu1000-gcc";
373 reg = <0x0 0x80000 0x0 0x1f4200>;
374 clocks = <&rpmhcc RPMH_CXO_CLK>,
375 <&sleep_clk>,
376 <0>,
377 <0>,
378 <0>;
379 #clock-cells = <1>;
380 #reset-cells = <1>;
381 #power-domain-cells = <1>;
382 };
383
384 ecpricc: clock-controller@280000 {
385 compatible = "qcom,qdu1000-ecpricc";
386 reg = <0x0 0x00280000 0x0 0x31c00>;
387 clocks = <&rpmhcc RPMH_CXO_CLK>,
388 <&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>,
389 <&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>,
390 <&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>,
391 <&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>,
392 <&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>,
393 <&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>;
394 #clock-cells = <1>;
395 #reset-cells = <1>;
396 };
397
398 gpi_dma0: dma-controller@900000 {
399 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
400 reg = <0x0 0x900000 0x0 0x60000>;
401 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
413 dma-channels = <12>;
414 dma-channel-mask = <0x3f>;
415 iommus = <&apps_smmu 0xf6 0x0>;
416 #dma-cells = <3>;
417 };
418
419 qupv3_id_0: geniqup@9c0000 {
420 compatible = "qcom,geni-se-qup";
421 reg = <0x0 0x9c0000 0x0 0x2000>;
422 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
423 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
424 clock-names = "m-ahb", "s-ahb";
425 iommus = <&apps_smmu 0xe3 0x0>;
426 interconnects = <&clk_virt MASTER_QUP_CORE_0 0
427 &clk_virt SLAVE_QUP_CORE_0 0>;
428 interconnect-names = "qup-core";
429
430 #address-cells = <2>;
431 #size-cells = <2>;
432 ranges;
433 status = "disabled";
434
435 uart0: serial@980000 {
436 compatible = "qcom,geni-uart";
437 reg = <0x0 0x980000 0x0 0x4000>;
438 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
439 clock-names = "se";
440 pinctrl-0 = <&qup_uart0_default>;
441 pinctrl-names = "default";
442 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
443 status = "disabled";
444 };
445
446 i2c1: i2c@984000 {
447 compatible = "qcom,geni-i2c";
448 reg = <0x0 0x984000 0x0 0x4000>;
449 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
450 clock-names = "se";
451 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
452 pinctrl-0 = <&qup_i2c1_data_clk>;
453 pinctrl-names = "default";
454 #address-cells = <1>;
455 #size-cells = <0>;
456 status = "disabled";
457 };
458
459 spi1: spi@984000 {
460 compatible = "qcom,geni-spi";
461 reg = <0x0 0x984000 0x0 0x4000>;
462 #address-cells = <1>;
463 #size-cells = <0>;
464 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
466 clock-names = "se";
467 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
468 pinctrl-names = "default";
469 status = "disabled";
470 };
471
472 i2c2: i2c@988000 {
473 compatible = "qcom,geni-i2c";
474 reg = <0x0 0x988000 0x0 0x4000>;
475 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
476 clock-names = "se";
477 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
478 pinctrl-0 = <&qup_i2c2_data_clk>;
479 pinctrl-names = "default";
480 #address-cells = <1>;
481 #size-cells = <0>;
482 status = "disabled";
483 };
484
485 spi2: spi@988000 {
486 compatible = "qcom,geni-spi";
487 reg = <0x0 0x988000 0x0 0x4000>;
488 #address-cells = <1>;
489 #size-cells = <0>;
490 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
492 clock-names = "se";
493 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
494 pinctrl-names = "default";
495 status = "disabled";
496 };
497
498 i2c3: i2c@98c000 {
499 compatible = "qcom,geni-i2c";
500 reg = <0x0 0x98c000 0x0 0x4000>;
501 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
502 clock-names = "se";
503 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
504 pinctrl-0 = <&qup_i2c3_data_clk>;
505 pinctrl-names = "default";
506 #address-cells = <1>;
507 #size-cells = <0>;
508 status = "disabled";
509 };
510
511 spi3: spi@98c000 {
512 compatible = "qcom,geni-spi";
513 reg = <0x0 0x98c000 0x0 0x4000>;
514 #address-cells = <1>;
515 #size-cells = <0>;
516 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
518 clock-names = "se";
519 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
520 pinctrl-names = "default";
521 status = "disabled";
522 };
523
524 i2c4: i2c@990000 {
525 compatible = "qcom,geni-i2c";
526 reg = <0x0 0x990000 0x0 0x4000>;
527 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
528 clock-names = "se";
529 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
530 pinctrl-0 = <&qup_i2c4_data_clk>;
531 pinctrl-names = "default";
532 #address-cells = <1>;
533 #size-cells = <0>;
534 status = "disabled";
535 };
536
537 spi4: spi@990000 {
538 compatible = "qcom,geni-spi";
539 reg = <0x0 0x990000 0x0 0x4000>;
540 #address-cells = <1>;
541 #size-cells = <0>;
542 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
544 clock-names = "se";
545 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
546 pinctrl-names = "default";
547 status = "disabled";
548 };
549
550 i2c5: i2c@994000 {
551 compatible = "qcom,geni-i2c";
552 reg = <0x0 0x994000 0x0 0x4000>;
553 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
554 clock-names = "se";
555 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
556 pinctrl-0 = <&qup_i2c5_data_clk>;
557 pinctrl-names = "default";
558 #address-cells = <1>;
559 #size-cells = <0>;
560 status = "disabled";
561 };
562
563 spi5: spi@994000 {
564 compatible = "qcom,geni-spi";
565 reg = <0x0 0x994000 0x0 0x4000>;
566 #address-cells = <1>;
567 #size-cells = <0>;
568 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
570 clock-names = "se";
571 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
572 pinctrl-names = "default";
573 status = "disabled";
574 };
575
576 i2c6: i2c@998000 {
577 compatible = "qcom,geni-i2c";
578 reg = <0x0 0x998000 0x0 0x4000>;
579 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
580 clock-names = "se";
581 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
582 pinctrl-0 = <&qup_i2c6_data_clk>;
583 pinctrl-names = "default";
584 #address-cells = <1>;
585 #size-cells = <0>;
586 status = "disabled";
587 };
588
589 spi6: spi@998000 {
590 compatible = "qcom,geni-spi";
591 reg = <0x0 0x998000 0x0 0x4000>;
592 #address-cells = <1>;
593 #size-cells = <0>;
594 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
596 clock-names = "se";
597 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
598 pinctrl-names = "default";
599 status = "disabled";
600 };
601
602 uart7: serial@99c000 {
603 compatible = "qcom,geni-debug-uart";
604 reg = <0x0 0x99c000 0x0 0x4000>;
605 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
606 clock-names = "se";
607 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
608 pinctrl-names = "default";
609 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
610 status = "disabled";
611 };
612 };
613
614 gpi_dma1: dma-controller@a00000 {
615 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
616 reg = <0x0 0xa00000 0x0 0x60000>;
617 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
621 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
629 dma-channels = <12>;
630 dma-channel-mask = <0x3f>;
631 iommus = <&apps_smmu 0x116 0x0>;
632 #dma-cells = <3>;
633 };
634
635 qupv3_id_1: geniqup@ac0000 {
636 compatible = "qcom,geni-se-qup";
637 reg = <0x0 0xac0000 0x0 0x2000>;
638 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
639 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
640 clock-names = "m-ahb", "s-ahb";
641 iommus = <&apps_smmu 0x103 0x0>;
642 #address-cells = <2>;
643 #size-cells = <2>;
644 ranges;
645 status = "disabled";
646
647 uart8: serial@a80000 {
648 compatible = "qcom,geni-uart";
649 reg = <0x0 0xa80000 0x0 0x4000>;
650 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
651 clock-names = "se";
652 pinctrl-0 = <&qup_uart8_default>;
653 pinctrl-names = "default";
654 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
655 #address-cells = <1>;
656 #size-cells = <0>;
657 status = "disabled";
658 };
659
660 i2c9: i2c@a84000 {
661 compatible = "qcom,geni-i2c";
662 reg = <0x0 0xa84000 0x0 0x4000>;
663 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
664 clock-names = "se";
665 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
666 pinctrl-0 = <&qup_i2c9_data_clk>;
667 pinctrl-names = "default";
668 #address-cells = <1>;
669 #size-cells = <0>;
670 status = "disabled";
671 };
672
673 spi9: spi@a84000 {
674 compatible = "qcom,geni-spi";
675 reg = <0x0 0xa84000 0x0 0x4000>;
676 #address-cells = <1>;
677 #size-cells = <0>;
678 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
680 clock-names = "se";
681 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
682 pinctrl-names = "default";
683 status = "disabled";
684 };
685
686 i2c10: i2c@a88000 {
687 compatible = "qcom,geni-i2c";
688 reg = <0x0 0xa88000 0x0 0x4000>;
689 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
690 clock-names = "se";
691 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
692 pinctrl-0 = <&qup_i2c10_data_clk>;
693 pinctrl-names = "default";
694 #address-cells = <1>;
695 #size-cells = <0>;
696 status = "disabled";
697 };
698
699 spi10: spi@a88000 {
700 compatible = "qcom,geni-spi";
701 reg = <0x0 0xa88000 0x0 0x4000>;
702 #address-cells = <1>;
703 #size-cells = <0>;
704 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
705 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
706 clock-names = "se";
707 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
708 pinctrl-names = "default";
709 status = "disabled";
710 };
711
712 i2c11: i2c@a8c000 {
713 compatible = "qcom,geni-i2c";
714 reg = <0x0 0xa8c000 0x0 0x4000>;
715 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
716 clock-names = "se";
717 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
718 pinctrl-0 = <&qup_i2c11_data_clk>;
719 pinctrl-names = "default";
720 #address-cells = <1>;
721 #size-cells = <0>;
722 status = "disabled";
723 };
724
725 spi11: spi@a8c000 {
726 compatible = "qcom,geni-spi";
727 reg = <0x0 0xa8c000 0x0 0x4000>;
728 #address-cells = <1>;
729 #size-cells = <0>;
730 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
731 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
732 clock-names = "se";
733 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
734 pinctrl-names = "default";
735 status = "disabled";
736 };
737
738 i2c12: i2c@a90000 {
739 compatible = "qcom,geni-i2c";
740 reg = <0x0 0xa90000 0x0 0x4000>;
741 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
742 clock-names = "se";
743 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
744 pinctrl-0 = <&qup_i2c12_data_clk>;
745 pinctrl-names = "default";
746 #address-cells = <1>;
747 #size-cells = <0>;
748 status = "disabled";
749 };
750
751 spi12: spi@a90000 {
752 compatible = "qcom,geni-spi";
753 reg = <0x0 0xa90000 0x0 0x4000>;
754 #address-cells = <1>;
755 #size-cells = <0>;
756 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
758 clock-names = "se";
759 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
760 pinctrl-names = "default";
761 status = "disabled";
762 };
763
764 i2c13: i2c@a94000 {
765 compatible = "qcom,geni-i2c";
766 reg = <0x0 0xa94000 0x0 0x4000>;
767 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
768 clock-names = "se";
769 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
770 pinctrl-0 = <&qup_i2c13_data_clk>;
771 pinctrl-names = "default";
772 #address-cells = <1>;
773 #size-cells = <0>;
774 status = "disabled";
775 };
776
777 uart13: serial@a94000 {
778 compatible = "qcom,geni-uart";
779 reg = <0x0 0xa94000 0x0 0x4000>;
780 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
781 clock-names = "se";
782 pinctrl-0 = <&qup_uart13_default>;
783 pinctrl-names = "default";
784 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
785 #address-cells = <1>;
786 #size-cells = <0>;
787 status = "disabled";
788 };
789
790 spi13: spi@a94000 {
791 compatible = "qcom,geni-spi";
792 reg = <0x0 0xa94000 0x0 0x4000>;
793 #address-cells = <1>;
794 #size-cells = <0>;
795 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
797 clock-names = "se";
798 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
799 pinctrl-names = "default";
800 status = "disabled";
801 };
802
803 i2c14: i2c@a98000 {
804 compatible = "qcom,geni-i2c";
805 reg = <0x0 0xa98000 0x0 0x4000>;
806 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
807 clock-names = "se";
808 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
809 pinctrl-0 = <&qup_i2c14_data_clk>;
810 pinctrl-names = "default";
811 #address-cells = <1>;
812 #size-cells = <0>;
813 status = "disabled";
814 };
815
816 spi14: spi@a98000 {
817 compatible = "qcom,geni-spi";
818 reg = <0x0 0xa98000 0x0 0x4000>;
819 #address-cells = <1>;
820 #size-cells = <0>;
821 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
823 clock-names = "se";
824 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
825 pinctrl-names = "default";
826 status = "disabled";
827 };
828
829 i2c15: i2c@a9c000 {
830 compatible = "qcom,geni-i2c";
831 reg = <0x0 0xa9c000 0x0 0x4000>;
832 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
833 clock-names = "se";
834 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
835 pinctrl-0 = <&qup_i2c15_data_clk>;
836 pinctrl-names = "default";
837 #address-cells = <1>;
838 #size-cells = <0>;
839 status = "disabled";
840 };
841
842 spi15: spi@a9c000 {
843 compatible = "qcom,geni-spi";
844 reg = <0x0 0xa9c000 0x0 0x4000>;
845 #address-cells = <1>;
846 #size-cells = <0>;
847 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
849 clock-names = "se";
850 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
851 pinctrl-names = "default";
852 status = "disabled";
853 };
854 };
855
856 system_noc: interconnect@1640000 {
857 compatible = "qcom,qdu1000-system-noc";
858 reg = <0x0 0x1640000 0x0 0x45080>;
859 qcom,bcm-voters = <&apps_bcm_voter>;
860 #interconnect-cells = <2>;
861 };
862
863 tcsr_mutex: hwlock@1f40000 {
864 compatible = "qcom,tcsr-mutex";
865 reg = <0x0 0x1f40000 0x0 0x20000>;
866 #hwlock-cells = <1>;
867 };
868
869 sdhc: mmc@8804000 {
870 compatible = "qcom,qdu1000-sdhci", "qcom,sdhci-msm-v5";
871 reg = <0x0 0x08804000 0x0 0x1000>,
872 <0x0 0x08805000 0x0 0x1000>;
873 reg-names = "hc", "cqhci";
874
875 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
876 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
877 interrupt-names = "hc_irq", "pwr_irq";
878
879 clocks = <&gcc GCC_SDCC5_AHB_CLK>,
880 <&gcc GCC_SDCC5_APPS_CLK>,
881 <&rpmhcc RPMH_CXO_CLK>;
882 clock-names = "iface",
883 "core",
884 "xo";
885
886 resets = <&gcc GCC_SDCC5_BCR>;
887
888 interconnects = <&system_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
889 <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_SDCC_2 0>;
890 interconnect-names = "sdhc-ddr", "cpu-sdhc";
891 power-domains = <&rpmhpd QDU1000_CX>;
892 operating-points-v2 = <&sdhc1_opp_table>;
893
894 iommus = <&apps_smmu 0x80 0x0>;
895 dma-coherent;
896
897 bus-width = <8>;
898
899 qcom,dll-config = <0x0007642c>;
900 qcom,ddr-config = <0x80040868>;
901
902 status = "disabled";
903
904 sdhc1_opp_table: opp-table {
905 compatible = "operating-points-v2";
906
907 opp-384000000 {
908 opp-hz = /bits/ 64 <384000000>;
909 required-opps = <&rpmhpd_opp_nom>;
910 opp-peak-kBps = <6528000 1652800>;
911 opp-avg-kBps = <400000 0>;
912 };
913 };
914 };
915
916 pdc: interrupt-controller@b220000 {
917 compatible = "qcom,qdu1000-pdc", "qcom,pdc";
918 reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
919 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
920 <94 609 31>, <125 63 1>;
921 #interrupt-cells = <2>;
922 interrupt-parent = <&intc>;
923 interrupt-controller;
924 };
925
926 spmi_bus: spmi@c400000 {
927 compatible = "qcom,spmi-pmic-arb";
928 reg = <0x0 0xc400000 0x0 0x3000>,
929 <0x0 0xc500000 0x0 0x400000>,
930 <0x0 0xc440000 0x0 0x80000>,
931 <0x0 0xc4c0000 0x0 0x10000>,
932 <0x0 0xc42d000 0x0 0x4000>;
933 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
934 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
935 interrupt-names = "periph_irq";
936 qcom,ee = <0>;
937 qcom,channel = <0>;
938 #address-cells = <2>;
939 #size-cells = <0>;
940 interrupt-controller;
941 #interrupt-cells = <4>;
942 };
943
944 tlmm: pinctrl@f000000 {
945 compatible = "qcom,qdu1000-tlmm";
946 reg = <0x0 0xf000000 0x0 0x1000000>;
947 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
948 gpio-controller;
949 #gpio-cells = <2>;
950 interrupt-controller;
951 #interrupt-cells = <2>;
952 gpio-ranges = <&tlmm 0 0 151>;
953 wakeup-parent = <&pdc>;
954
955 qup_uart0_default: qup-uart0-default-state {
956 pins = "gpio6", "gpio7", "gpio8", "gpio9";
957 function = "qup00";
958 };
959
960 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
961 pins = "gpio10", "gpio11";
962 function = "qup01";
963 };
964
965 qup_spi1_data_clk: qup-spi1-data-clk-state {
966 pins = "gpio10", "gpio11", "gpio12";
967 function = "qup01";
968 };
969
970 qup_spi1_cs: qup-spi1-cs-state {
971 pins = "gpio13";
972 function = "gpio";
973 };
974
975 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
976 pins = "gpio12", "gpio13";
977 function = "qup02";
978 };
979
980 qup_spi2_data_clk: qup-spi2-data-clk-state {
981 pins = "gpio12", "gpio13", "gpio10";
982 function = "qup02";
983 };
984
985 qup_spi2_cs: qup-spi2-cs-state {
986 pins = "gpio11";
987 function = "gpio";
988 };
989
990 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
991 pins = "gpio14", "gpio15";
992 function = "qup03";
993 };
994
995 qup_spi3_data_clk: qup-spi3-data-clk-state {
996 pins = "gpio14", "gpio15", "gpio16";
997 function = "qup03";
998 };
999
1000 qup_spi3_cs: qup-spi3-cs-state {
1001 pins = "gpio17";
1002 function = "gpio";
1003 };
1004
1005 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
1006 pins = "gpio16", "gpio17";
1007 function = "qup04";
1008 };
1009
1010 qup_spi4_data_clk: qup-spi4-data-clk-state {
1011 pins = "gpio16", "gpio17", "gpio14";
1012 function = "qup04";
1013 };
1014
1015 qup_spi4_cs: qup-spi4-cs-state {
1016 pins = "gpio15";
1017 function = "gpio";
1018 };
1019
1020 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
1021 pins = "gpio130", "gpio131";
1022 function = "qup05";
1023 };
1024
1025 qup_spi5_data_clk: qup-spi5-data-clk-state {
1026 pins = "gpio130", "gpio131", "gpio132";
1027 function = "qup05";
1028 };
1029
1030 qup_spi5_cs: qup-spi5-cs-state {
1031 pins = "gpio133";
1032 function = "gpio";
1033 };
1034
1035 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
1036 pins = "gpio132", "gpio133";
1037 function = "qup06";
1038 };
1039
1040 qup_spi6_data_clk: qup-spi6-data-clk-state {
1041 pins = "gpio132", "gpio133", "gpio130";
1042 function = "qup06";
1043 };
1044
1045 qup_spi6_cs: qup-spi6-cs-state {
1046 pins = "gpio131";
1047 function = "gpio";
1048 };
1049
1050 qup_uart7_rx: qup-uart7-rx-state {
1051 pins = "gpio135";
1052 function = "qup07";
1053 };
1054
1055 qup_uart7_tx: qup-uart7-tx-state {
1056 pins = "gpio134";
1057 function = "qup07";
1058 };
1059
1060 qup_uart8_default: qup-uart8-default-state {
1061 pins = "gpio18", "gpio19", "gpio20", "gpio21";
1062 function = "qup10";
1063 };
1064
1065 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
1066 pins = "gpio22", "gpio23";
1067 function = "qup11";
1068 };
1069
1070 qup_spi9_data_clk: qup-spi9-data-clk-state {
1071 pins = "gpio22", "gpio23", "gpio24";
1072 function = "qup11";
1073 };
1074
1075 qup_spi9_cs: qup-spi9-cs-state {
1076 pins = "gpio25";
1077 function = "gpio";
1078 };
1079
1080 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
1081 pins = "gpio24", "gpio25";
1082 function = "qup12";
1083 };
1084
1085 qup_spi10_data_clk: qup-spi10-data-clk-state {
1086 pins = "gpio24", "gpio25", "gpio22";
1087 function = "qup12";
1088 };
1089
1090 qup_spi10_cs: qup-spi10-cs-state {
1091 pins = "gpio23";
1092 function = "gpio";
1093 };
1094
1095 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
1096 pins = "gpio26", "gpio27";
1097 function = "qup13";
1098 };
1099
1100 qup_spi11_data_clk: qup-spi11-data-clk-state {
1101 pins = "gpio26", "gpio27", "gpio28";
1102 function = "qup13";
1103 };
1104
1105 qup_spi11_cs: qup-spi11-cs-state {
1106 pins = "gpio29";
1107 function = "gpio";
1108 };
1109
1110 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
1111 pins = "gpio28", "gpio29";
1112 function = "qup14";
1113 };
1114
1115 qup_spi12_data_clk: qup-spi12-data-clk-state {
1116 pins = "gpio28", "gpio29", "gpio26";
1117 function = "qup14";
1118 };
1119
1120 qup_spi12_cs: qup-spi12-cs-state {
1121 pins = "gpio27";
1122 function = "gpio";
1123 };
1124
1125 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
1126 pins = "gpio30", "gpio31";
1127 function = "qup15";
1128 };
1129
1130 qup_spi13_data_clk: qup-spi13-data-clk-state {
1131 pins = "gpio30", "gpio31", "gpio32";
1132 function = "qup15";
1133 };
1134
1135 qup_spi13_cs: qup-spi13-cs-state {
1136 pins = "gpio33";
1137 function = "gpio";
1138 };
1139
1140 qup_uart13_default: qup-uart13-default-state {
1141 pins = "gpio30", "gpio31", "gpio32", "gpio33";
1142 function = "qup15";
1143 };
1144
1145 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
1146 pins = "gpio34", "gpio35";
1147 function = "qup16";
1148 };
1149
1150 qup_spi14_data_clk: qup-spi14-data-clk-state {
1151 pins = "gpio34", "gpio35", "gpio36";
1152 function = "qup16";
1153 };
1154
1155 qup_spi14_cs: qup-spi14-cs-state {
1156 pins = "gpio37", "gpio38";
1157 function = "gpio";
1158 };
1159
1160 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
1161 pins = "gpio40", "gpio41";
1162 function = "qup17";
1163 };
1164
1165 qup_spi15_data_clk: qup-spi15-data-clk-state {
1166 pins = "gpio40", "gpio41", "gpio30";
1167 function = "qup17";
1168 };
1169
1170 qup_spi15_cs: qup-spi15-cs-state {
1171 pins = "gpio31";
1172 function = "gpio";
1173 };
1174
1175 sdc_on_state: sdc-on-state {
1176 clk-pins {
1177 pins = "sdc1_clk";
1178 drive-strength = <16>;
1179 bias-disable;
1180 };
1181
1182 cmd-pins {
1183 pins = "sdc1_cmd";
1184 drive-strength = <10>;
1185 bias-pull-up;
1186 };
1187
1188 data-pins {
1189 pins = "sdc1_data";
1190 drive-strength = <10>;
1191 bias-pull-up;
1192 };
1193
1194 rclk-pins {
1195 pins = "sdc1_rclk";
1196 bias-pull-down;
1197 };
1198 };
1199
1200 sdc_off_state: sdc-off-state {
1201 clk-pins {
1202 pins = "sdc1_clk";
1203 drive-strength = <2>;
1204 bias-disable;
1205 };
1206
1207 cmd-pins {
1208 pins = "sdc1_cmd";
1209 drive-strength = <2>;
1210 bias-pull-up;
1211 };
1212
1213 data-pins {
1214 pins = "sdc1_data";
1215 drive-strength = <2>;
1216 bias-pull-up;
1217 };
1218
1219 rclk-pins {
1220 pins = "sdc1_rclk";
1221 bias-pull-down;
1222 };
1223 };
1224 };
1225
1226 sram@14680000 {
1227 compatible = "qcom,qdu1000-imem", "syscon", "simple-mfd";
1228 reg = <0 0x14680000 0 0x1000>;
1229 ranges = <0 0 0x14680000 0x1000>;
1230 #address-cells = <1>;
1231 #size-cells = <1>;
1232
1233 pil-reloc@94c {
1234 compatible = "qcom,pil-reloc-info";
1235 reg = <0x94c 0xc8>;
1236 };
1237 };
1238
1239 apps_smmu: iommu@15000000 {
1240 compatible = "qcom,qdu1000-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1241 reg = <0x0 0x15000000 0x0 0x100000>;
1242 #iommu-cells = <2>;
1243 #global-interrupts = <2>;
1244 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
1246 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1247 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
1252 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1253 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1254 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1255 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1256 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1257 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1258 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1259 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1260 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1261 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1262 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1263 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1265 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1266 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1278 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1279 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1280 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1281 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1282 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1283 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1284 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1285 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1286 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1287 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1288 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1289 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1290 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1291 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1292 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
1293 };
1294
1295 intc: interrupt-controller@17200000 {
1296 compatible = "arm,gic-v3";
1297 reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
1298 <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */
1299 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1300 #interrupt-cells = <3>;
1301 interrupt-controller;
1302 #redistributor-regions = <1>;
1303 redistributor-stride = <0x0 0x20000>;
1304 };
1305
1306 timer@17420000 {
1307 compatible = "arm,armv7-timer-mem";
1308 reg = <0x0 0x17420000 0x0 0x1000>;
1309 #address-cells = <1>;
1310 #size-cells = <1>;
1311 ranges = <0x0 0x0 0x0 0x20000000>;
1312
1313 frame@17421000 {
1314 reg = <0x17421000 0x1000>,
1315 <0x17422000 0x1000>;
1316 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1317 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1318 frame-number = <0>;
1319 };
1320
1321 frame@17423000 {
1322 reg = <0x17423000 0x1000>;
1323 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1324 frame-number = <1>;
1325 status = "disabled";
1326 };
1327
1328 frame@17425000 {
1329 reg = <0x17425000 0x1000>,
1330 <0x17426000 0x1000>;
1331 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1332 frame-number = <2>;
1333 status = "disabled";
1334 };
1335
1336 frame@17427000 {
1337 reg = <0x17427000 0x1000>;
1338 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1339 frame-number = <3>;
1340 status = "disabled";
1341 };
1342
1343 frame@17429000 {
1344 reg = <0x17429000 0x1000>;
1345 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1346 frame-number = <4>;
1347 status = "disabled";
1348 };
1349
1350 frame@1742b000 {
1351 reg = <0x1742b000 0x1000>;
1352 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1353 frame-number = <5>;
1354 status = "disabled";
1355 };
1356
1357 frame@1742d000 {
1358 reg = <0x1742d000 0x1000>;
1359 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1360 frame-number = <6>;
1361 status = "disabled";
1362 };
1363 };
1364
1365 apps_rsc: rsc@17a00000 {
1366 compatible = "qcom,rpmh-rsc";
1367 reg = <0x0 0x17a00000 0x0 0x10000>,
1368 <0x0 0x17a10000 0x0 0x10000>,
1369 <0x0 0x17a20000 0x0 0x10000>;
1370 reg-names = "drv-0", "drv-1", "drv-2";
1371 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1374 qcom,tcs-offset = <0xd00>;
1375 qcom,drv-id = <2>;
1376 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
1377 <WAKE_TCS 3>, <CONTROL_TCS 0>;
1378 label = "apps_rsc";
1379 power-domains = <&CLUSTER_PD>;
1380
1381 apps_bcm_voter: bcm-voter {
1382 compatible = "qcom,bcm-voter";
1383 };
1384
1385 rpmhcc: clock-controller {
1386 compatible = "qcom,qdu1000-rpmh-clk";
1387 clocks = <&xo_board>;
1388 clock-names = "xo";
1389 #clock-cells = <1>;
1390 };
1391
1392 rpmhpd: power-controller {
1393 compatible = "qcom,qdu1000-rpmhpd";
1394 #power-domain-cells = <1>;
1395 operating-points-v2 = <&rpmhpd_opp_table>;
1396
1397 rpmhpd_opp_table: opp-table {
1398 compatible = "operating-points-v2";
1399
1400 rpmhpd_opp_ret: opp1 {
1401 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1402 };
1403
1404 rpmhpd_opp_min_svs: opp2 {
1405 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1406 };
1407
1408 rpmhpd_opp_low_svs: opp3 {
1409 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1410 };
1411
1412 rpmhpd_opp_svs: opp4 {
1413 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1414 };
1415
1416 rpmhpd_opp_svs_l1: opp5 {
1417 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1418 };
1419
1420 rpmhpd_opp_nom: opp6 {
1421 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1422 };
1423
1424 rpmhpd_opp_nom_l1: opp7 {
1425 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1426 };
1427
1428 rpmhpd_opp_nom_l2: opp8 {
1429 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1430 };
1431
1432 rpmhpd_opp_turbo: opp9 {
1433 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1434 };
1435
1436 rpmhpd_opp_turbo_l1: opp10 {
1437 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1438 };
1439 };
1440 };
1441 };
1442
1443 cpufreq_hw: cpufreq@17d90000 {
1444 compatible = "qcom,qdu1000-cpufreq-epss", "qcom,cpufreq-epss";
1445 reg = <0x0 0x17d90000 0x0 0x1000>, <0x0 0x17d91000 0x0 0x1000>;
1446 reg-names = "freq-domain0", "freq-domain1";
1447 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
1448 clock-names = "xo", "alternate";
1449 #freq-domain-cells = <1>;
1450 #clock-cells = <1>;
1451 };
1452
1453 gem_noc: interconnect@19100000 {
1454 compatible = "qcom,qdu1000-gem-noc";
1455 reg = <0x0 0x19100000 0x0 0xB8080>;
1456 qcom,bcm-voters = <&apps_bcm_voter>;
1457 #interconnect-cells = <2>;
1458 };
1459
1460 system-cache-controller@19200000 {
1461 compatible = "qcom,qdu1000-llcc";
1462 reg = <0 0x19200000 0 0xd80000>,
1463 <0 0x1a200000 0 0x80000>;
1464 reg-names = "llcc0_base",
1465 "llcc_broadcast_base";
1466 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1467 };
1468 };
1469
1470 timer {
1471 compatible = "arm,armv8-timer";
1472 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1473 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1474 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1475 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1476 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1477 };
1478 };
"Das U-Boot" Source Tree