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Squashed 'dts/upstream/' changes from aaba2d45dc2a..b35b9bd1d4ee
[thirdparty/u-boot.git] / src / arm64 / qcom / sc7280.dtsi
1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * sc7280 SoC device tree source
4 *
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
6 */
7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
11 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/firmware/qcom,scm.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/interconnect/qcom,icc.h>
19 #include <dt-bindings/interconnect/qcom,osm-l3.h>
20 #include <dt-bindings/interconnect/qcom,sc7280.h>
21 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/mailbox/qcom-ipcc.h>
23 #include <dt-bindings/phy/phy-qcom-qmp.h>
24 #include <dt-bindings/power/qcom-rpmpd.h>
25 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
26 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
27 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
28 #include <dt-bindings/sound/qcom,lpass.h>
29 #include <dt-bindings/thermal/thermal.h>
30
31 / {
32 interrupt-parent = <&intc>;
33
34 #address-cells = <2>;
35 #size-cells = <2>;
36
37 chosen { };
38
39 aliases {
40 i2c0 = &i2c0;
41 i2c1 = &i2c1;
42 i2c2 = &i2c2;
43 i2c3 = &i2c3;
44 i2c4 = &i2c4;
45 i2c5 = &i2c5;
46 i2c6 = &i2c6;
47 i2c7 = &i2c7;
48 i2c8 = &i2c8;
49 i2c9 = &i2c9;
50 i2c10 = &i2c10;
51 i2c11 = &i2c11;
52 i2c12 = &i2c12;
53 i2c13 = &i2c13;
54 i2c14 = &i2c14;
55 i2c15 = &i2c15;
56 mmc1 = &sdhc_1;
57 mmc2 = &sdhc_2;
58 spi0 = &spi0;
59 spi1 = &spi1;
60 spi2 = &spi2;
61 spi3 = &spi3;
62 spi4 = &spi4;
63 spi5 = &spi5;
64 spi6 = &spi6;
65 spi7 = &spi7;
66 spi8 = &spi8;
67 spi9 = &spi9;
68 spi10 = &spi10;
69 spi11 = &spi11;
70 spi12 = &spi12;
71 spi13 = &spi13;
72 spi14 = &spi14;
73 spi15 = &spi15;
74 };
75
76 clocks {
77 xo_board: xo-board {
78 compatible = "fixed-clock";
79 clock-frequency = <76800000>;
80 #clock-cells = <0>;
81 };
82
83 sleep_clk: sleep-clk {
84 compatible = "fixed-clock";
85 clock-frequency = <32000>;
86 #clock-cells = <0>;
87 };
88 };
89
90 reserved-memory {
91 #address-cells = <2>;
92 #size-cells = <2>;
93 ranges;
94
95 wlan_ce_mem: wlan-ce@4cd000 {
96 no-map;
97 reg = <0x0 0x004cd000 0x0 0x1000>;
98 };
99
100 hyp_mem: hyp@80000000 {
101 reg = <0x0 0x80000000 0x0 0x600000>;
102 no-map;
103 };
104
105 xbl_mem: xbl@80600000 {
106 reg = <0x0 0x80600000 0x0 0x200000>;
107 no-map;
108 };
109
110 aop_mem: aop@80800000 {
111 reg = <0x0 0x80800000 0x0 0x60000>;
112 no-map;
113 };
114
115 aop_cmd_db_mem: aop-cmd-db@80860000 {
116 reg = <0x0 0x80860000 0x0 0x20000>;
117 compatible = "qcom,cmd-db";
118 no-map;
119 };
120
121 reserved_xbl_uefi_log: xbl-uefi-res@80880000 {
122 reg = <0x0 0x80884000 0x0 0x10000>;
123 no-map;
124 };
125
126 sec_apps_mem: sec-apps@808ff000 {
127 reg = <0x0 0x808ff000 0x0 0x1000>;
128 no-map;
129 };
130
131 smem_mem: smem@80900000 {
132 reg = <0x0 0x80900000 0x0 0x200000>;
133 no-map;
134 };
135
136 cpucp_mem: cpucp@80b00000 {
137 no-map;
138 reg = <0x0 0x80b00000 0x0 0x100000>;
139 };
140
141 wlan_fw_mem: wlan-fw@80c00000 {
142 reg = <0x0 0x80c00000 0x0 0xc00000>;
143 no-map;
144 };
145
146 adsp_mem: adsp@86700000 {
147 reg = <0x0 0x86700000 0x0 0x2800000>;
148 no-map;
149 };
150
151 video_mem: video@8b200000 {
152 reg = <0x0 0x8b200000 0x0 0x500000>;
153 no-map;
154 };
155
156 cdsp_mem: cdsp@88f00000 {
157 reg = <0x0 0x88f00000 0x0 0x1e00000>;
158 no-map;
159 };
160
161 ipa_fw_mem: ipa-fw@8b700000 {
162 reg = <0 0x8b700000 0 0x10000>;
163 no-map;
164 };
165
166 gpu_zap_mem: zap@8b71a000 {
167 reg = <0 0x8b71a000 0 0x2000>;
168 no-map;
169 };
170
171 mpss_mem: mpss@8b800000 {
172 reg = <0x0 0x8b800000 0x0 0xf600000>;
173 no-map;
174 };
175
176 wpss_mem: wpss@9ae00000 {
177 reg = <0x0 0x9ae00000 0x0 0x1900000>;
178 no-map;
179 };
180
181 rmtfs_mem: rmtfs@9c900000 {
182 compatible = "qcom,rmtfs-mem";
183 reg = <0x0 0x9c900000 0x0 0x280000>;
184 no-map;
185
186 qcom,client-id = <1>;
187 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
188 };
189 };
190
191 cpus {
192 #address-cells = <2>;
193 #size-cells = <0>;
194
195 CPU0: cpu@0 {
196 device_type = "cpu";
197 compatible = "qcom,kryo";
198 reg = <0x0 0x0>;
199 clocks = <&cpufreq_hw 0>;
200 enable-method = "psci";
201 power-domains = <&CPU_PD0>;
202 power-domain-names = "psci";
203 next-level-cache = <&L2_0>;
204 operating-points-v2 = <&cpu0_opp_table>;
205 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
206 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
207 qcom,freq-domain = <&cpufreq_hw 0>;
208 #cooling-cells = <2>;
209 L2_0: l2-cache {
210 compatible = "cache";
211 cache-level = <2>;
212 cache-unified;
213 next-level-cache = <&L3_0>;
214 L3_0: l3-cache {
215 compatible = "cache";
216 cache-level = <3>;
217 cache-unified;
218 };
219 };
220 };
221
222 CPU1: cpu@100 {
223 device_type = "cpu";
224 compatible = "qcom,kryo";
225 reg = <0x0 0x100>;
226 clocks = <&cpufreq_hw 0>;
227 enable-method = "psci";
228 power-domains = <&CPU_PD1>;
229 power-domain-names = "psci";
230 next-level-cache = <&L2_100>;
231 operating-points-v2 = <&cpu0_opp_table>;
232 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
233 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
234 qcom,freq-domain = <&cpufreq_hw 0>;
235 #cooling-cells = <2>;
236 L2_100: l2-cache {
237 compatible = "cache";
238 cache-level = <2>;
239 cache-unified;
240 next-level-cache = <&L3_0>;
241 };
242 };
243
244 CPU2: cpu@200 {
245 device_type = "cpu";
246 compatible = "qcom,kryo";
247 reg = <0x0 0x200>;
248 clocks = <&cpufreq_hw 0>;
249 enable-method = "psci";
250 power-domains = <&CPU_PD2>;
251 power-domain-names = "psci";
252 next-level-cache = <&L2_200>;
253 operating-points-v2 = <&cpu0_opp_table>;
254 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
255 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
256 qcom,freq-domain = <&cpufreq_hw 0>;
257 #cooling-cells = <2>;
258 L2_200: l2-cache {
259 compatible = "cache";
260 cache-level = <2>;
261 cache-unified;
262 next-level-cache = <&L3_0>;
263 };
264 };
265
266 CPU3: cpu@300 {
267 device_type = "cpu";
268 compatible = "qcom,kryo";
269 reg = <0x0 0x300>;
270 clocks = <&cpufreq_hw 0>;
271 enable-method = "psci";
272 power-domains = <&CPU_PD3>;
273 power-domain-names = "psci";
274 next-level-cache = <&L2_300>;
275 operating-points-v2 = <&cpu0_opp_table>;
276 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
277 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
278 qcom,freq-domain = <&cpufreq_hw 0>;
279 #cooling-cells = <2>;
280 L2_300: l2-cache {
281 compatible = "cache";
282 cache-level = <2>;
283 cache-unified;
284 next-level-cache = <&L3_0>;
285 };
286 };
287
288 CPU4: cpu@400 {
289 device_type = "cpu";
290 compatible = "qcom,kryo";
291 reg = <0x0 0x400>;
292 clocks = <&cpufreq_hw 1>;
293 enable-method = "psci";
294 power-domains = <&CPU_PD4>;
295 power-domain-names = "psci";
296 next-level-cache = <&L2_400>;
297 operating-points-v2 = <&cpu4_opp_table>;
298 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
299 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
300 qcom,freq-domain = <&cpufreq_hw 1>;
301 #cooling-cells = <2>;
302 L2_400: l2-cache {
303 compatible = "cache";
304 cache-level = <2>;
305 cache-unified;
306 next-level-cache = <&L3_0>;
307 };
308 };
309
310 CPU5: cpu@500 {
311 device_type = "cpu";
312 compatible = "qcom,kryo";
313 reg = <0x0 0x500>;
314 clocks = <&cpufreq_hw 1>;
315 enable-method = "psci";
316 power-domains = <&CPU_PD5>;
317 power-domain-names = "psci";
318 next-level-cache = <&L2_500>;
319 operating-points-v2 = <&cpu4_opp_table>;
320 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
321 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
322 qcom,freq-domain = <&cpufreq_hw 1>;
323 #cooling-cells = <2>;
324 L2_500: l2-cache {
325 compatible = "cache";
326 cache-level = <2>;
327 cache-unified;
328 next-level-cache = <&L3_0>;
329 };
330 };
331
332 CPU6: cpu@600 {
333 device_type = "cpu";
334 compatible = "qcom,kryo";
335 reg = <0x0 0x600>;
336 clocks = <&cpufreq_hw 1>;
337 enable-method = "psci";
338 power-domains = <&CPU_PD6>;
339 power-domain-names = "psci";
340 next-level-cache = <&L2_600>;
341 operating-points-v2 = <&cpu4_opp_table>;
342 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
343 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
344 qcom,freq-domain = <&cpufreq_hw 1>;
345 #cooling-cells = <2>;
346 L2_600: l2-cache {
347 compatible = "cache";
348 cache-level = <2>;
349 cache-unified;
350 next-level-cache = <&L3_0>;
351 };
352 };
353
354 CPU7: cpu@700 {
355 device_type = "cpu";
356 compatible = "qcom,kryo";
357 reg = <0x0 0x700>;
358 clocks = <&cpufreq_hw 2>;
359 enable-method = "psci";
360 power-domains = <&CPU_PD7>;
361 power-domain-names = "psci";
362 next-level-cache = <&L2_700>;
363 operating-points-v2 = <&cpu7_opp_table>;
364 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
365 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
366 qcom,freq-domain = <&cpufreq_hw 2>;
367 #cooling-cells = <2>;
368 L2_700: l2-cache {
369 compatible = "cache";
370 cache-level = <2>;
371 cache-unified;
372 next-level-cache = <&L3_0>;
373 };
374 };
375
376 cpu-map {
377 cluster0 {
378 core0 {
379 cpu = <&CPU0>;
380 };
381
382 core1 {
383 cpu = <&CPU1>;
384 };
385
386 core2 {
387 cpu = <&CPU2>;
388 };
389
390 core3 {
391 cpu = <&CPU3>;
392 };
393
394 core4 {
395 cpu = <&CPU4>;
396 };
397
398 core5 {
399 cpu = <&CPU5>;
400 };
401
402 core6 {
403 cpu = <&CPU6>;
404 };
405
406 core7 {
407 cpu = <&CPU7>;
408 };
409 };
410 };
411
412 idle-states {
413 entry-method = "psci";
414
415 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
416 compatible = "arm,idle-state";
417 idle-state-name = "little-power-down";
418 arm,psci-suspend-param = <0x40000003>;
419 entry-latency-us = <549>;
420 exit-latency-us = <901>;
421 min-residency-us = <1774>;
422 local-timer-stop;
423 };
424
425 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
426 compatible = "arm,idle-state";
427 idle-state-name = "little-rail-power-down";
428 arm,psci-suspend-param = <0x40000004>;
429 entry-latency-us = <702>;
430 exit-latency-us = <915>;
431 min-residency-us = <4001>;
432 local-timer-stop;
433 };
434
435 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
436 compatible = "arm,idle-state";
437 idle-state-name = "big-power-down";
438 arm,psci-suspend-param = <0x40000003>;
439 entry-latency-us = <523>;
440 exit-latency-us = <1244>;
441 min-residency-us = <2207>;
442 local-timer-stop;
443 };
444
445 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
446 compatible = "arm,idle-state";
447 idle-state-name = "big-rail-power-down";
448 arm,psci-suspend-param = <0x40000004>;
449 entry-latency-us = <526>;
450 exit-latency-us = <1854>;
451 min-residency-us = <5555>;
452 local-timer-stop;
453 };
454 };
455
456 domain-idle-states {
457 CLUSTER_SLEEP_0: cluster-sleep-0 {
458 compatible = "domain-idle-state";
459 idle-state-name = "cluster-power-down";
460 arm,psci-suspend-param = <0x40003444>;
461 entry-latency-us = <3263>;
462 exit-latency-us = <6562>;
463 min-residency-us = <9926>;
464 local-timer-stop;
465 };
466 };
467 };
468
469 cpu0_opp_table: opp-table-cpu0 {
470 compatible = "operating-points-v2";
471 opp-shared;
472
473 cpu0_opp_300mhz: opp-300000000 {
474 opp-hz = /bits/ 64 <300000000>;
475 opp-peak-kBps = <800000 9600000>;
476 };
477
478 cpu0_opp_691mhz: opp-691200000 {
479 opp-hz = /bits/ 64 <691200000>;
480 opp-peak-kBps = <800000 17817600>;
481 };
482
483 cpu0_opp_806mhz: opp-806400000 {
484 opp-hz = /bits/ 64 <806400000>;
485 opp-peak-kBps = <800000 20889600>;
486 };
487
488 cpu0_opp_941mhz: opp-940800000 {
489 opp-hz = /bits/ 64 <940800000>;
490 opp-peak-kBps = <1804000 24576000>;
491 };
492
493 cpu0_opp_1152mhz: opp-1152000000 {
494 opp-hz = /bits/ 64 <1152000000>;
495 opp-peak-kBps = <2188000 27033600>;
496 };
497
498 cpu0_opp_1325mhz: opp-1324800000 {
499 opp-hz = /bits/ 64 <1324800000>;
500 opp-peak-kBps = <2188000 33792000>;
501 };
502
503 cpu0_opp_1517mhz: opp-1516800000 {
504 opp-hz = /bits/ 64 <1516800000>;
505 opp-peak-kBps = <3072000 38092800>;
506 };
507
508 cpu0_opp_1651mhz: opp-1651200000 {
509 opp-hz = /bits/ 64 <1651200000>;
510 opp-peak-kBps = <3072000 41779200>;
511 };
512
513 cpu0_opp_1805mhz: opp-1804800000 {
514 opp-hz = /bits/ 64 <1804800000>;
515 opp-peak-kBps = <4068000 48537600>;
516 };
517
518 cpu0_opp_1958mhz: opp-1958400000 {
519 opp-hz = /bits/ 64 <1958400000>;
520 opp-peak-kBps = <4068000 48537600>;
521 };
522
523 cpu0_opp_2016mhz: opp-2016000000 {
524 opp-hz = /bits/ 64 <2016000000>;
525 opp-peak-kBps = <6220000 48537600>;
526 };
527 };
528
529 cpu4_opp_table: opp-table-cpu4 {
530 compatible = "operating-points-v2";
531 opp-shared;
532
533 cpu4_opp_691mhz: opp-691200000 {
534 opp-hz = /bits/ 64 <691200000>;
535 opp-peak-kBps = <1804000 9600000>;
536 };
537
538 cpu4_opp_941mhz: opp-940800000 {
539 opp-hz = /bits/ 64 <940800000>;
540 opp-peak-kBps = <2188000 17817600>;
541 };
542
543 cpu4_opp_1229mhz: opp-1228800000 {
544 opp-hz = /bits/ 64 <1228800000>;
545 opp-peak-kBps = <4068000 24576000>;
546 };
547
548 cpu4_opp_1344mhz: opp-1344000000 {
549 opp-hz = /bits/ 64 <1344000000>;
550 opp-peak-kBps = <4068000 24576000>;
551 };
552
553 cpu4_opp_1517mhz: opp-1516800000 {
554 opp-hz = /bits/ 64 <1516800000>;
555 opp-peak-kBps = <4068000 24576000>;
556 };
557
558 cpu4_opp_1651mhz: opp-1651200000 {
559 opp-hz = /bits/ 64 <1651200000>;
560 opp-peak-kBps = <6220000 38092800>;
561 };
562
563 cpu4_opp_1901mhz: opp-1900800000 {
564 opp-hz = /bits/ 64 <1900800000>;
565 opp-peak-kBps = <6220000 44851200>;
566 };
567
568 cpu4_opp_2054mhz: opp-2054400000 {
569 opp-hz = /bits/ 64 <2054400000>;
570 opp-peak-kBps = <6220000 44851200>;
571 };
572
573 cpu4_opp_2112mhz: opp-2112000000 {
574 opp-hz = /bits/ 64 <2112000000>;
575 opp-peak-kBps = <6220000 44851200>;
576 };
577
578 cpu4_opp_2131mhz: opp-2131200000 {
579 opp-hz = /bits/ 64 <2131200000>;
580 opp-peak-kBps = <6220000 44851200>;
581 };
582
583 cpu4_opp_2208mhz: opp-2208000000 {
584 opp-hz = /bits/ 64 <2208000000>;
585 opp-peak-kBps = <6220000 44851200>;
586 };
587
588 cpu4_opp_2400mhz: opp-2400000000 {
589 opp-hz = /bits/ 64 <2400000000>;
590 opp-peak-kBps = <8532000 48537600>;
591 };
592
593 cpu4_opp_2611mhz: opp-2611200000 {
594 opp-hz = /bits/ 64 <2611200000>;
595 opp-peak-kBps = <8532000 48537600>;
596 };
597 };
598
599 cpu7_opp_table: opp-table-cpu7 {
600 compatible = "operating-points-v2";
601 opp-shared;
602
603 cpu7_opp_806mhz: opp-806400000 {
604 opp-hz = /bits/ 64 <806400000>;
605 opp-peak-kBps = <1804000 9600000>;
606 };
607
608 cpu7_opp_1056mhz: opp-1056000000 {
609 opp-hz = /bits/ 64 <1056000000>;
610 opp-peak-kBps = <2188000 17817600>;
611 };
612
613 cpu7_opp_1325mhz: opp-1324800000 {
614 opp-hz = /bits/ 64 <1324800000>;
615 opp-peak-kBps = <4068000 24576000>;
616 };
617
618 cpu7_opp_1517mhz: opp-1516800000 {
619 opp-hz = /bits/ 64 <1516800000>;
620 opp-peak-kBps = <4068000 24576000>;
621 };
622
623 cpu7_opp_1766mhz: opp-1766400000 {
624 opp-hz = /bits/ 64 <1766400000>;
625 opp-peak-kBps = <6220000 38092800>;
626 };
627
628 cpu7_opp_1862mhz: opp-1862400000 {
629 opp-hz = /bits/ 64 <1862400000>;
630 opp-peak-kBps = <6220000 38092800>;
631 };
632
633 cpu7_opp_2035mhz: opp-2035200000 {
634 opp-hz = /bits/ 64 <2035200000>;
635 opp-peak-kBps = <6220000 38092800>;
636 };
637
638 cpu7_opp_2112mhz: opp-2112000000 {
639 opp-hz = /bits/ 64 <2112000000>;
640 opp-peak-kBps = <6220000 44851200>;
641 };
642
643 cpu7_opp_2208mhz: opp-2208000000 {
644 opp-hz = /bits/ 64 <2208000000>;
645 opp-peak-kBps = <6220000 44851200>;
646 };
647
648 cpu7_opp_2381mhz: opp-2380800000 {
649 opp-hz = /bits/ 64 <2380800000>;
650 opp-peak-kBps = <6832000 44851200>;
651 };
652
653 cpu7_opp_2400mhz: opp-2400000000 {
654 opp-hz = /bits/ 64 <2400000000>;
655 opp-peak-kBps = <8532000 48537600>;
656 };
657
658 cpu7_opp_2515mhz: opp-2515200000 {
659 opp-hz = /bits/ 64 <2515200000>;
660 opp-peak-kBps = <8532000 48537600>;
661 };
662
663 cpu7_opp_2707mhz: opp-2707200000 {
664 opp-hz = /bits/ 64 <2707200000>;
665 opp-peak-kBps = <8532000 48537600>;
666 };
667
668 cpu7_opp_3014mhz: opp-3014400000 {
669 opp-hz = /bits/ 64 <3014400000>;
670 opp-peak-kBps = <8532000 48537600>;
671 };
672 };
673
674 memory@80000000 {
675 device_type = "memory";
676 /* We expect the bootloader to fill in the size */
677 reg = <0 0x80000000 0 0>;
678 };
679
680 firmware {
681 scm: scm {
682 compatible = "qcom,scm-sc7280", "qcom,scm";
683 };
684 };
685
686 clk_virt: interconnect {
687 compatible = "qcom,sc7280-clk-virt";
688 #interconnect-cells = <2>;
689 qcom,bcm-voters = <&apps_bcm_voter>;
690 };
691
692 smem {
693 compatible = "qcom,smem";
694 memory-region = <&smem_mem>;
695 hwlocks = <&tcsr_mutex 3>;
696 };
697
698 smp2p-adsp {
699 compatible = "qcom,smp2p";
700 qcom,smem = <443>, <429>;
701 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
702 IPCC_MPROC_SIGNAL_SMP2P
703 IRQ_TYPE_EDGE_RISING>;
704 mboxes = <&ipcc IPCC_CLIENT_LPASS
705 IPCC_MPROC_SIGNAL_SMP2P>;
706
707 qcom,local-pid = <0>;
708 qcom,remote-pid = <2>;
709
710 adsp_smp2p_out: master-kernel {
711 qcom,entry-name = "master-kernel";
712 #qcom,smem-state-cells = <1>;
713 };
714
715 adsp_smp2p_in: slave-kernel {
716 qcom,entry-name = "slave-kernel";
717 interrupt-controller;
718 #interrupt-cells = <2>;
719 };
720 };
721
722 smp2p-cdsp {
723 compatible = "qcom,smp2p";
724 qcom,smem = <94>, <432>;
725 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
726 IPCC_MPROC_SIGNAL_SMP2P
727 IRQ_TYPE_EDGE_RISING>;
728 mboxes = <&ipcc IPCC_CLIENT_CDSP
729 IPCC_MPROC_SIGNAL_SMP2P>;
730
731 qcom,local-pid = <0>;
732 qcom,remote-pid = <5>;
733
734 cdsp_smp2p_out: master-kernel {
735 qcom,entry-name = "master-kernel";
736 #qcom,smem-state-cells = <1>;
737 };
738
739 cdsp_smp2p_in: slave-kernel {
740 qcom,entry-name = "slave-kernel";
741 interrupt-controller;
742 #interrupt-cells = <2>;
743 };
744 };
745
746 smp2p-mpss {
747 compatible = "qcom,smp2p";
748 qcom,smem = <435>, <428>;
749 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
750 IPCC_MPROC_SIGNAL_SMP2P
751 IRQ_TYPE_EDGE_RISING>;
752 mboxes = <&ipcc IPCC_CLIENT_MPSS
753 IPCC_MPROC_SIGNAL_SMP2P>;
754
755 qcom,local-pid = <0>;
756 qcom,remote-pid = <1>;
757
758 modem_smp2p_out: master-kernel {
759 qcom,entry-name = "master-kernel";
760 #qcom,smem-state-cells = <1>;
761 };
762
763 modem_smp2p_in: slave-kernel {
764 qcom,entry-name = "slave-kernel";
765 interrupt-controller;
766 #interrupt-cells = <2>;
767 };
768
769 ipa_smp2p_out: ipa-ap-to-modem {
770 qcom,entry-name = "ipa";
771 #qcom,smem-state-cells = <1>;
772 };
773
774 ipa_smp2p_in: ipa-modem-to-ap {
775 qcom,entry-name = "ipa";
776 interrupt-controller;
777 #interrupt-cells = <2>;
778 };
779 };
780
781 smp2p-wpss {
782 compatible = "qcom,smp2p";
783 qcom,smem = <617>, <616>;
784 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
785 IPCC_MPROC_SIGNAL_SMP2P
786 IRQ_TYPE_EDGE_RISING>;
787 mboxes = <&ipcc IPCC_CLIENT_WPSS
788 IPCC_MPROC_SIGNAL_SMP2P>;
789
790 qcom,local-pid = <0>;
791 qcom,remote-pid = <13>;
792
793 wpss_smp2p_out: master-kernel {
794 qcom,entry-name = "master-kernel";
795 #qcom,smem-state-cells = <1>;
796 };
797
798 wpss_smp2p_in: slave-kernel {
799 qcom,entry-name = "slave-kernel";
800 interrupt-controller;
801 #interrupt-cells = <2>;
802 };
803
804 wlan_smp2p_out: wlan-ap-to-wpss {
805 qcom,entry-name = "wlan";
806 #qcom,smem-state-cells = <1>;
807 };
808
809 wlan_smp2p_in: wlan-wpss-to-ap {
810 qcom,entry-name = "wlan";
811 interrupt-controller;
812 #interrupt-cells = <2>;
813 };
814 };
815
816 pmu {
817 compatible = "arm,armv8-pmuv3";
818 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
819 };
820
821 psci {
822 compatible = "arm,psci-1.0";
823 method = "smc";
824
825 CPU_PD0: power-domain-cpu0 {
826 #power-domain-cells = <0>;
827 power-domains = <&CLUSTER_PD>;
828 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
829 };
830
831 CPU_PD1: power-domain-cpu1 {
832 #power-domain-cells = <0>;
833 power-domains = <&CLUSTER_PD>;
834 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
835 };
836
837 CPU_PD2: power-domain-cpu2 {
838 #power-domain-cells = <0>;
839 power-domains = <&CLUSTER_PD>;
840 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
841 };
842
843 CPU_PD3: power-domain-cpu3 {
844 #power-domain-cells = <0>;
845 power-domains = <&CLUSTER_PD>;
846 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
847 };
848
849 CPU_PD4: power-domain-cpu4 {
850 #power-domain-cells = <0>;
851 power-domains = <&CLUSTER_PD>;
852 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
853 };
854
855 CPU_PD5: power-domain-cpu5 {
856 #power-domain-cells = <0>;
857 power-domains = <&CLUSTER_PD>;
858 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
859 };
860
861 CPU_PD6: power-domain-cpu6 {
862 #power-domain-cells = <0>;
863 power-domains = <&CLUSTER_PD>;
864 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
865 };
866
867 CPU_PD7: power-domain-cpu7 {
868 #power-domain-cells = <0>;
869 power-domains = <&CLUSTER_PD>;
870 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
871 };
872
873 CLUSTER_PD: power-domain-cluster {
874 #power-domain-cells = <0>;
875 domain-idle-states = <&CLUSTER_SLEEP_0>;
876 };
877 };
878
879 qspi_opp_table: opp-table-qspi {
880 compatible = "operating-points-v2";
881
882 opp-75000000 {
883 opp-hz = /bits/ 64 <75000000>;
884 required-opps = <&rpmhpd_opp_low_svs>;
885 };
886
887 opp-150000000 {
888 opp-hz = /bits/ 64 <150000000>;
889 required-opps = <&rpmhpd_opp_svs>;
890 };
891
892 opp-200000000 {
893 opp-hz = /bits/ 64 <200000000>;
894 required-opps = <&rpmhpd_opp_svs_l1>;
895 };
896
897 opp-300000000 {
898 opp-hz = /bits/ 64 <300000000>;
899 required-opps = <&rpmhpd_opp_nom>;
900 };
901 };
902
903 qup_opp_table: opp-table-qup {
904 compatible = "operating-points-v2";
905
906 opp-75000000 {
907 opp-hz = /bits/ 64 <75000000>;
908 required-opps = <&rpmhpd_opp_low_svs>;
909 };
910
911 opp-100000000 {
912 opp-hz = /bits/ 64 <100000000>;
913 required-opps = <&rpmhpd_opp_svs>;
914 };
915
916 opp-128000000 {
917 opp-hz = /bits/ 64 <128000000>;
918 required-opps = <&rpmhpd_opp_nom>;
919 };
920 };
921
922 soc: soc@0 {
923 #address-cells = <2>;
924 #size-cells = <2>;
925 ranges = <0 0 0 0 0x10 0>;
926 dma-ranges = <0 0 0 0 0x10 0>;
927 compatible = "simple-bus";
928
929 gcc: clock-controller@100000 {
930 compatible = "qcom,gcc-sc7280";
931 reg = <0 0x00100000 0 0x1f0000>;
932 clocks = <&rpmhcc RPMH_CXO_CLK>,
933 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
934 <0>, <&pcie1_phy>,
935 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>,
936 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
937 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
938 "pcie_0_pipe_clk", "pcie_1_pipe_clk",
939 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
940 "ufs_phy_tx_symbol_0_clk",
941 "usb3_phy_wrapper_gcc_usb30_pipe_clk";
942 #clock-cells = <1>;
943 #reset-cells = <1>;
944 #power-domain-cells = <1>;
945 power-domains = <&rpmhpd SC7280_CX>;
946 };
947
948 ipcc: mailbox@408000 {
949 compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
950 reg = <0 0x00408000 0 0x1000>;
951 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
952 interrupt-controller;
953 #interrupt-cells = <3>;
954 #mbox-cells = <2>;
955 };
956
957 qfprom: efuse@784000 {
958 compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
959 reg = <0 0x00784000 0 0xa20>,
960 <0 0x00780000 0 0xa20>,
961 <0 0x00782000 0 0x120>,
962 <0 0x00786000 0 0x1fff>;
963 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
964 clock-names = "core";
965 power-domains = <&rpmhpd SC7280_MX>;
966 #address-cells = <1>;
967 #size-cells = <1>;
968
969 gpu_speed_bin: gpu_speed_bin@1e9 {
970 reg = <0x1e9 0x2>;
971 bits = <5 8>;
972 };
973 };
974
975 sdhc_1: mmc@7c4000 {
976 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
977 pinctrl-names = "default", "sleep";
978 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
979 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
980 status = "disabled";
981
982 reg = <0 0x007c4000 0 0x1000>,
983 <0 0x007c5000 0 0x1000>;
984 reg-names = "hc", "cqhci";
985
986 iommus = <&apps_smmu 0xc0 0x0>;
987 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;
989 interrupt-names = "hc_irq", "pwr_irq";
990
991 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
992 <&gcc GCC_SDCC1_APPS_CLK>,
993 <&rpmhcc RPMH_CXO_CLK>;
994 clock-names = "iface", "core", "xo";
995 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
996 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>;
997 interconnect-names = "sdhc-ddr","cpu-sdhc";
998 power-domains = <&rpmhpd SC7280_CX>;
999 operating-points-v2 = <&sdhc1_opp_table>;
1000
1001 bus-width = <8>;
1002 supports-cqe;
1003 dma-coherent;
1004
1005 qcom,dll-config = <0x0007642c>;
1006 qcom,ddr-config = <0x80040868>;
1007
1008 mmc-ddr-1_8v;
1009 mmc-hs200-1_8v;
1010 mmc-hs400-1_8v;
1011 mmc-hs400-enhanced-strobe;
1012
1013 resets = <&gcc GCC_SDCC1_BCR>;
1014
1015 sdhc1_opp_table: opp-table {
1016 compatible = "operating-points-v2";
1017
1018 opp-100000000 {
1019 opp-hz = /bits/ 64 <100000000>;
1020 required-opps = <&rpmhpd_opp_low_svs>;
1021 opp-peak-kBps = <1800000 400000>;
1022 opp-avg-kBps = <100000 0>;
1023 };
1024
1025 opp-384000000 {
1026 opp-hz = /bits/ 64 <384000000>;
1027 required-opps = <&rpmhpd_opp_nom>;
1028 opp-peak-kBps = <5400000 1600000>;
1029 opp-avg-kBps = <390000 0>;
1030 };
1031 };
1032 };
1033
1034 gpi_dma0: dma-controller@900000 {
1035 #dma-cells = <3>;
1036 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
1037 reg = <0 0x00900000 0 0x60000>;
1038 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1039 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1040 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1041 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1042 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1043 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1044 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1045 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1046 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1047 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1048 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1049 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1050 dma-channels = <12>;
1051 dma-channel-mask = <0x7f>;
1052 iommus = <&apps_smmu 0x0136 0x0>;
1053 status = "disabled";
1054 };
1055
1056 qupv3_id_0: geniqup@9c0000 {
1057 compatible = "qcom,geni-se-qup";
1058 reg = <0 0x009c0000 0 0x2000>;
1059 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1060 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1061 clock-names = "m-ahb", "s-ahb";
1062 #address-cells = <2>;
1063 #size-cells = <2>;
1064 ranges;
1065 iommus = <&apps_smmu 0x123 0x0>;
1066 status = "disabled";
1067
1068 i2c0: i2c@980000 {
1069 compatible = "qcom,geni-i2c";
1070 reg = <0 0x00980000 0 0x4000>;
1071 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1072 clock-names = "se";
1073 pinctrl-names = "default";
1074 pinctrl-0 = <&qup_i2c0_data_clk>;
1075 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1076 #address-cells = <1>;
1077 #size-cells = <0>;
1078 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1079 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1080 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1081 interconnect-names = "qup-core", "qup-config",
1082 "qup-memory";
1083 power-domains = <&rpmhpd SC7280_CX>;
1084 required-opps = <&rpmhpd_opp_low_svs>;
1085 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1086 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1087 dma-names = "tx", "rx";
1088 status = "disabled";
1089 };
1090
1091 spi0: spi@980000 {
1092 compatible = "qcom,geni-spi";
1093 reg = <0 0x00980000 0 0x4000>;
1094 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1095 clock-names = "se";
1096 pinctrl-names = "default";
1097 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1098 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1099 #address-cells = <1>;
1100 #size-cells = <0>;
1101 power-domains = <&rpmhpd SC7280_CX>;
1102 operating-points-v2 = <&qup_opp_table>;
1103 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1104 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1105 interconnect-names = "qup-core", "qup-config";
1106 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1107 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1108 dma-names = "tx", "rx";
1109 status = "disabled";
1110 };
1111
1112 uart0: serial@980000 {
1113 compatible = "qcom,geni-uart";
1114 reg = <0 0x00980000 0 0x4000>;
1115 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1116 clock-names = "se";
1117 pinctrl-names = "default";
1118 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1119 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1120 power-domains = <&rpmhpd SC7280_CX>;
1121 operating-points-v2 = <&qup_opp_table>;
1122 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1123 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1124 interconnect-names = "qup-core", "qup-config";
1125 status = "disabled";
1126 };
1127
1128 i2c1: i2c@984000 {
1129 compatible = "qcom,geni-i2c";
1130 reg = <0 0x00984000 0 0x4000>;
1131 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1132 clock-names = "se";
1133 pinctrl-names = "default";
1134 pinctrl-0 = <&qup_i2c1_data_clk>;
1135 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1136 #address-cells = <1>;
1137 #size-cells = <0>;
1138 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1139 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1140 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1141 interconnect-names = "qup-core", "qup-config",
1142 "qup-memory";
1143 power-domains = <&rpmhpd SC7280_CX>;
1144 required-opps = <&rpmhpd_opp_low_svs>;
1145 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1146 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1147 dma-names = "tx", "rx";
1148 status = "disabled";
1149 };
1150
1151 spi1: spi@984000 {
1152 compatible = "qcom,geni-spi";
1153 reg = <0 0x00984000 0 0x4000>;
1154 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1155 clock-names = "se";
1156 pinctrl-names = "default";
1157 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1158 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1159 #address-cells = <1>;
1160 #size-cells = <0>;
1161 power-domains = <&rpmhpd SC7280_CX>;
1162 operating-points-v2 = <&qup_opp_table>;
1163 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1164 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1165 interconnect-names = "qup-core", "qup-config";
1166 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1167 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1168 dma-names = "tx", "rx";
1169 status = "disabled";
1170 };
1171
1172 uart1: serial@984000 {
1173 compatible = "qcom,geni-uart";
1174 reg = <0 0x00984000 0 0x4000>;
1175 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1176 clock-names = "se";
1177 pinctrl-names = "default";
1178 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1179 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1180 power-domains = <&rpmhpd SC7280_CX>;
1181 operating-points-v2 = <&qup_opp_table>;
1182 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1183 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1184 interconnect-names = "qup-core", "qup-config";
1185 status = "disabled";
1186 };
1187
1188 i2c2: i2c@988000 {
1189 compatible = "qcom,geni-i2c";
1190 reg = <0 0x00988000 0 0x4000>;
1191 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1192 clock-names = "se";
1193 pinctrl-names = "default";
1194 pinctrl-0 = <&qup_i2c2_data_clk>;
1195 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1196 #address-cells = <1>;
1197 #size-cells = <0>;
1198 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1199 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1200 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1201 interconnect-names = "qup-core", "qup-config",
1202 "qup-memory";
1203 power-domains = <&rpmhpd SC7280_CX>;
1204 required-opps = <&rpmhpd_opp_low_svs>;
1205 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1206 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1207 dma-names = "tx", "rx";
1208 status = "disabled";
1209 };
1210
1211 spi2: spi@988000 {
1212 compatible = "qcom,geni-spi";
1213 reg = <0 0x00988000 0 0x4000>;
1214 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1215 clock-names = "se";
1216 pinctrl-names = "default";
1217 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1218 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1221 power-domains = <&rpmhpd SC7280_CX>;
1222 operating-points-v2 = <&qup_opp_table>;
1223 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1224 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1225 interconnect-names = "qup-core", "qup-config";
1226 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1227 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1228 dma-names = "tx", "rx";
1229 status = "disabled";
1230 };
1231
1232 uart2: serial@988000 {
1233 compatible = "qcom,geni-uart";
1234 reg = <0 0x00988000 0 0x4000>;
1235 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1236 clock-names = "se";
1237 pinctrl-names = "default";
1238 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1239 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1240 power-domains = <&rpmhpd SC7280_CX>;
1241 operating-points-v2 = <&qup_opp_table>;
1242 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1243 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1244 interconnect-names = "qup-core", "qup-config";
1245 status = "disabled";
1246 };
1247
1248 i2c3: i2c@98c000 {
1249 compatible = "qcom,geni-i2c";
1250 reg = <0 0x0098c000 0 0x4000>;
1251 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1252 clock-names = "se";
1253 pinctrl-names = "default";
1254 pinctrl-0 = <&qup_i2c3_data_clk>;
1255 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1256 #address-cells = <1>;
1257 #size-cells = <0>;
1258 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1259 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1260 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1261 interconnect-names = "qup-core", "qup-config",
1262 "qup-memory";
1263 power-domains = <&rpmhpd SC7280_CX>;
1264 required-opps = <&rpmhpd_opp_low_svs>;
1265 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1266 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1267 dma-names = "tx", "rx";
1268 status = "disabled";
1269 };
1270
1271 spi3: spi@98c000 {
1272 compatible = "qcom,geni-spi";
1273 reg = <0 0x0098c000 0 0x4000>;
1274 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1275 clock-names = "se";
1276 pinctrl-names = "default";
1277 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1278 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1279 #address-cells = <1>;
1280 #size-cells = <0>;
1281 power-domains = <&rpmhpd SC7280_CX>;
1282 operating-points-v2 = <&qup_opp_table>;
1283 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1284 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1285 interconnect-names = "qup-core", "qup-config";
1286 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1287 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1288 dma-names = "tx", "rx";
1289 status = "disabled";
1290 };
1291
1292 uart3: serial@98c000 {
1293 compatible = "qcom,geni-uart";
1294 reg = <0 0x0098c000 0 0x4000>;
1295 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1296 clock-names = "se";
1297 pinctrl-names = "default";
1298 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1299 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1300 power-domains = <&rpmhpd SC7280_CX>;
1301 operating-points-v2 = <&qup_opp_table>;
1302 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1303 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1304 interconnect-names = "qup-core", "qup-config";
1305 status = "disabled";
1306 };
1307
1308 i2c4: i2c@990000 {
1309 compatible = "qcom,geni-i2c";
1310 reg = <0 0x00990000 0 0x4000>;
1311 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1312 clock-names = "se";
1313 pinctrl-names = "default";
1314 pinctrl-0 = <&qup_i2c4_data_clk>;
1315 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1316 #address-cells = <1>;
1317 #size-cells = <0>;
1318 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1319 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1320 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1321 interconnect-names = "qup-core", "qup-config",
1322 "qup-memory";
1323 power-domains = <&rpmhpd SC7280_CX>;
1324 required-opps = <&rpmhpd_opp_low_svs>;
1325 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1326 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1327 dma-names = "tx", "rx";
1328 status = "disabled";
1329 };
1330
1331 spi4: spi@990000 {
1332 compatible = "qcom,geni-spi";
1333 reg = <0 0x00990000 0 0x4000>;
1334 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1335 clock-names = "se";
1336 pinctrl-names = "default";
1337 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1338 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1339 #address-cells = <1>;
1340 #size-cells = <0>;
1341 power-domains = <&rpmhpd SC7280_CX>;
1342 operating-points-v2 = <&qup_opp_table>;
1343 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1344 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1345 interconnect-names = "qup-core", "qup-config";
1346 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1347 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1348 dma-names = "tx", "rx";
1349 status = "disabled";
1350 };
1351
1352 uart4: serial@990000 {
1353 compatible = "qcom,geni-uart";
1354 reg = <0 0x00990000 0 0x4000>;
1355 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1356 clock-names = "se";
1357 pinctrl-names = "default";
1358 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1359 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1360 power-domains = <&rpmhpd SC7280_CX>;
1361 operating-points-v2 = <&qup_opp_table>;
1362 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1363 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1364 interconnect-names = "qup-core", "qup-config";
1365 status = "disabled";
1366 };
1367
1368 i2c5: i2c@994000 {
1369 compatible = "qcom,geni-i2c";
1370 reg = <0 0x00994000 0 0x4000>;
1371 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1372 clock-names = "se";
1373 pinctrl-names = "default";
1374 pinctrl-0 = <&qup_i2c5_data_clk>;
1375 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1376 #address-cells = <1>;
1377 #size-cells = <0>;
1378 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1379 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1380 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1381 interconnect-names = "qup-core", "qup-config",
1382 "qup-memory";
1383 power-domains = <&rpmhpd SC7280_CX>;
1384 required-opps = <&rpmhpd_opp_low_svs>;
1385 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1386 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1387 dma-names = "tx", "rx";
1388 status = "disabled";
1389 };
1390
1391 spi5: spi@994000 {
1392 compatible = "qcom,geni-spi";
1393 reg = <0 0x00994000 0 0x4000>;
1394 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1395 clock-names = "se";
1396 pinctrl-names = "default";
1397 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1398 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1399 #address-cells = <1>;
1400 #size-cells = <0>;
1401 power-domains = <&rpmhpd SC7280_CX>;
1402 operating-points-v2 = <&qup_opp_table>;
1403 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1404 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1405 interconnect-names = "qup-core", "qup-config";
1406 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1407 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1408 dma-names = "tx", "rx";
1409 status = "disabled";
1410 };
1411
1412 uart5: serial@994000 {
1413 compatible = "qcom,geni-uart";
1414 reg = <0 0x00994000 0 0x4000>;
1415 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1416 clock-names = "se";
1417 pinctrl-names = "default";
1418 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
1419 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1420 power-domains = <&rpmhpd SC7280_CX>;
1421 operating-points-v2 = <&qup_opp_table>;
1422 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1423 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1424 interconnect-names = "qup-core", "qup-config";
1425 status = "disabled";
1426 };
1427
1428 i2c6: i2c@998000 {
1429 compatible = "qcom,geni-i2c";
1430 reg = <0 0x00998000 0 0x4000>;
1431 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1432 clock-names = "se";
1433 pinctrl-names = "default";
1434 pinctrl-0 = <&qup_i2c6_data_clk>;
1435 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1436 #address-cells = <1>;
1437 #size-cells = <0>;
1438 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1439 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1440 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1441 interconnect-names = "qup-core", "qup-config",
1442 "qup-memory";
1443 power-domains = <&rpmhpd SC7280_CX>;
1444 required-opps = <&rpmhpd_opp_low_svs>;
1445 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1446 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1447 dma-names = "tx", "rx";
1448 status = "disabled";
1449 };
1450
1451 spi6: spi@998000 {
1452 compatible = "qcom,geni-spi";
1453 reg = <0 0x00998000 0 0x4000>;
1454 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1455 clock-names = "se";
1456 pinctrl-names = "default";
1457 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1458 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1459 #address-cells = <1>;
1460 #size-cells = <0>;
1461 power-domains = <&rpmhpd SC7280_CX>;
1462 operating-points-v2 = <&qup_opp_table>;
1463 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1464 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1465 interconnect-names = "qup-core", "qup-config";
1466 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1467 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1468 dma-names = "tx", "rx";
1469 status = "disabled";
1470 };
1471
1472 uart6: serial@998000 {
1473 compatible = "qcom,geni-uart";
1474 reg = <0 0x00998000 0 0x4000>;
1475 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1476 clock-names = "se";
1477 pinctrl-names = "default";
1478 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1479 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1480 power-domains = <&rpmhpd SC7280_CX>;
1481 operating-points-v2 = <&qup_opp_table>;
1482 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1483 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1484 interconnect-names = "qup-core", "qup-config";
1485 status = "disabled";
1486 };
1487
1488 i2c7: i2c@99c000 {
1489 compatible = "qcom,geni-i2c";
1490 reg = <0 0x0099c000 0 0x4000>;
1491 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1492 clock-names = "se";
1493 pinctrl-names = "default";
1494 pinctrl-0 = <&qup_i2c7_data_clk>;
1495 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1496 #address-cells = <1>;
1497 #size-cells = <0>;
1498 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1499 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1500 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1501 interconnect-names = "qup-core", "qup-config",
1502 "qup-memory";
1503 power-domains = <&rpmhpd SC7280_CX>;
1504 required-opps = <&rpmhpd_opp_low_svs>;
1505 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1506 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1507 dma-names = "tx", "rx";
1508 status = "disabled";
1509 };
1510
1511 spi7: spi@99c000 {
1512 compatible = "qcom,geni-spi";
1513 reg = <0 0x0099c000 0 0x4000>;
1514 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1515 clock-names = "se";
1516 pinctrl-names = "default";
1517 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1518 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1519 #address-cells = <1>;
1520 #size-cells = <0>;
1521 power-domains = <&rpmhpd SC7280_CX>;
1522 operating-points-v2 = <&qup_opp_table>;
1523 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1524 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1525 interconnect-names = "qup-core", "qup-config";
1526 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1527 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1528 dma-names = "tx", "rx";
1529 status = "disabled";
1530 };
1531
1532 uart7: serial@99c000 {
1533 compatible = "qcom,geni-uart";
1534 reg = <0 0x0099c000 0 0x4000>;
1535 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1536 clock-names = "se";
1537 pinctrl-names = "default";
1538 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1539 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1540 power-domains = <&rpmhpd SC7280_CX>;
1541 operating-points-v2 = <&qup_opp_table>;
1542 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1543 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1544 interconnect-names = "qup-core", "qup-config";
1545 status = "disabled";
1546 };
1547 };
1548
1549 gpi_dma1: dma-controller@a00000 {
1550 #dma-cells = <3>;
1551 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
1552 reg = <0 0x00a00000 0 0x60000>;
1553 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1554 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1555 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1556 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1557 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1558 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1559 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1560 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1561 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1562 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1563 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1564 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1565 dma-channels = <12>;
1566 dma-channel-mask = <0x1e>;
1567 iommus = <&apps_smmu 0x56 0x0>;
1568 status = "disabled";
1569 };
1570
1571 qupv3_id_1: geniqup@ac0000 {
1572 compatible = "qcom,geni-se-qup";
1573 reg = <0 0x00ac0000 0 0x2000>;
1574 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1575 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1576 clock-names = "m-ahb", "s-ahb";
1577 #address-cells = <2>;
1578 #size-cells = <2>;
1579 ranges;
1580 iommus = <&apps_smmu 0x43 0x0>;
1581 status = "disabled";
1582
1583 i2c8: i2c@a80000 {
1584 compatible = "qcom,geni-i2c";
1585 reg = <0 0x00a80000 0 0x4000>;
1586 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1587 clock-names = "se";
1588 pinctrl-names = "default";
1589 pinctrl-0 = <&qup_i2c8_data_clk>;
1590 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1591 #address-cells = <1>;
1592 #size-cells = <0>;
1593 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1594 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1595 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1596 interconnect-names = "qup-core", "qup-config",
1597 "qup-memory";
1598 power-domains = <&rpmhpd SC7280_CX>;
1599 required-opps = <&rpmhpd_opp_low_svs>;
1600 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1601 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1602 dma-names = "tx", "rx";
1603 status = "disabled";
1604 };
1605
1606 spi8: spi@a80000 {
1607 compatible = "qcom,geni-spi";
1608 reg = <0 0x00a80000 0 0x4000>;
1609 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1610 clock-names = "se";
1611 pinctrl-names = "default";
1612 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1613 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1614 #address-cells = <1>;
1615 #size-cells = <0>;
1616 power-domains = <&rpmhpd SC7280_CX>;
1617 operating-points-v2 = <&qup_opp_table>;
1618 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1619 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1620 interconnect-names = "qup-core", "qup-config";
1621 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1622 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1623 dma-names = "tx", "rx";
1624 status = "disabled";
1625 };
1626
1627 uart8: serial@a80000 {
1628 compatible = "qcom,geni-uart";
1629 reg = <0 0x00a80000 0 0x4000>;
1630 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1631 clock-names = "se";
1632 pinctrl-names = "default";
1633 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1634 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1635 power-domains = <&rpmhpd SC7280_CX>;
1636 operating-points-v2 = <&qup_opp_table>;
1637 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1638 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1639 interconnect-names = "qup-core", "qup-config";
1640 status = "disabled";
1641 };
1642
1643 i2c9: i2c@a84000 {
1644 compatible = "qcom,geni-i2c";
1645 reg = <0 0x00a84000 0 0x4000>;
1646 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1647 clock-names = "se";
1648 pinctrl-names = "default";
1649 pinctrl-0 = <&qup_i2c9_data_clk>;
1650 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1651 #address-cells = <1>;
1652 #size-cells = <0>;
1653 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1654 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1655 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1656 interconnect-names = "qup-core", "qup-config",
1657 "qup-memory";
1658 power-domains = <&rpmhpd SC7280_CX>;
1659 required-opps = <&rpmhpd_opp_low_svs>;
1660 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1661 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1662 dma-names = "tx", "rx";
1663 status = "disabled";
1664 };
1665
1666 spi9: spi@a84000 {
1667 compatible = "qcom,geni-spi";
1668 reg = <0 0x00a84000 0 0x4000>;
1669 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1670 clock-names = "se";
1671 pinctrl-names = "default";
1672 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1673 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1674 #address-cells = <1>;
1675 #size-cells = <0>;
1676 power-domains = <&rpmhpd SC7280_CX>;
1677 operating-points-v2 = <&qup_opp_table>;
1678 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1679 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1680 interconnect-names = "qup-core", "qup-config";
1681 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1682 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1683 dma-names = "tx", "rx";
1684 status = "disabled";
1685 };
1686
1687 uart9: serial@a84000 {
1688 compatible = "qcom,geni-uart";
1689 reg = <0 0x00a84000 0 0x4000>;
1690 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1691 clock-names = "se";
1692 pinctrl-names = "default";
1693 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1694 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1695 power-domains = <&rpmhpd SC7280_CX>;
1696 operating-points-v2 = <&qup_opp_table>;
1697 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1698 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1699 interconnect-names = "qup-core", "qup-config";
1700 status = "disabled";
1701 };
1702
1703 i2c10: i2c@a88000 {
1704 compatible = "qcom,geni-i2c";
1705 reg = <0 0x00a88000 0 0x4000>;
1706 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1707 clock-names = "se";
1708 pinctrl-names = "default";
1709 pinctrl-0 = <&qup_i2c10_data_clk>;
1710 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1711 #address-cells = <1>;
1712 #size-cells = <0>;
1713 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1714 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1715 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1716 interconnect-names = "qup-core", "qup-config",
1717 "qup-memory";
1718 power-domains = <&rpmhpd SC7280_CX>;
1719 required-opps = <&rpmhpd_opp_low_svs>;
1720 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1721 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1722 dma-names = "tx", "rx";
1723 status = "disabled";
1724 };
1725
1726 spi10: spi@a88000 {
1727 compatible = "qcom,geni-spi";
1728 reg = <0 0x00a88000 0 0x4000>;
1729 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1730 clock-names = "se";
1731 pinctrl-names = "default";
1732 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1733 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1734 #address-cells = <1>;
1735 #size-cells = <0>;
1736 power-domains = <&rpmhpd SC7280_CX>;
1737 operating-points-v2 = <&qup_opp_table>;
1738 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1739 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1740 interconnect-names = "qup-core", "qup-config";
1741 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1742 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1743 dma-names = "tx", "rx";
1744 status = "disabled";
1745 };
1746
1747 uart10: serial@a88000 {
1748 compatible = "qcom,geni-uart";
1749 reg = <0 0x00a88000 0 0x4000>;
1750 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1751 clock-names = "se";
1752 pinctrl-names = "default";
1753 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1754 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1755 power-domains = <&rpmhpd SC7280_CX>;
1756 operating-points-v2 = <&qup_opp_table>;
1757 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1758 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1759 interconnect-names = "qup-core", "qup-config";
1760 status = "disabled";
1761 };
1762
1763 i2c11: i2c@a8c000 {
1764 compatible = "qcom,geni-i2c";
1765 reg = <0 0x00a8c000 0 0x4000>;
1766 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1767 clock-names = "se";
1768 pinctrl-names = "default";
1769 pinctrl-0 = <&qup_i2c11_data_clk>;
1770 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1771 #address-cells = <1>;
1772 #size-cells = <0>;
1773 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1774 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1775 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1776 interconnect-names = "qup-core", "qup-config",
1777 "qup-memory";
1778 power-domains = <&rpmhpd SC7280_CX>;
1779 required-opps = <&rpmhpd_opp_low_svs>;
1780 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1781 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1782 dma-names = "tx", "rx";
1783 status = "disabled";
1784 };
1785
1786 spi11: spi@a8c000 {
1787 compatible = "qcom,geni-spi";
1788 reg = <0 0x00a8c000 0 0x4000>;
1789 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1790 clock-names = "se";
1791 pinctrl-names = "default";
1792 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1793 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1794 #address-cells = <1>;
1795 #size-cells = <0>;
1796 power-domains = <&rpmhpd SC7280_CX>;
1797 operating-points-v2 = <&qup_opp_table>;
1798 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1799 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1800 interconnect-names = "qup-core", "qup-config";
1801 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1802 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1803 dma-names = "tx", "rx";
1804 status = "disabled";
1805 };
1806
1807 uart11: serial@a8c000 {
1808 compatible = "qcom,geni-uart";
1809 reg = <0 0x00a8c000 0 0x4000>;
1810 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1811 clock-names = "se";
1812 pinctrl-names = "default";
1813 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1814 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1815 power-domains = <&rpmhpd SC7280_CX>;
1816 operating-points-v2 = <&qup_opp_table>;
1817 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1818 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1819 interconnect-names = "qup-core", "qup-config";
1820 status = "disabled";
1821 };
1822
1823 i2c12: i2c@a90000 {
1824 compatible = "qcom,geni-i2c";
1825 reg = <0 0x00a90000 0 0x4000>;
1826 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1827 clock-names = "se";
1828 pinctrl-names = "default";
1829 pinctrl-0 = <&qup_i2c12_data_clk>;
1830 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1831 #address-cells = <1>;
1832 #size-cells = <0>;
1833 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1834 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1835 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1836 interconnect-names = "qup-core", "qup-config",
1837 "qup-memory";
1838 power-domains = <&rpmhpd SC7280_CX>;
1839 required-opps = <&rpmhpd_opp_low_svs>;
1840 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1841 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1842 dma-names = "tx", "rx";
1843 status = "disabled";
1844 };
1845
1846 spi12: spi@a90000 {
1847 compatible = "qcom,geni-spi";
1848 reg = <0 0x00a90000 0 0x4000>;
1849 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1850 clock-names = "se";
1851 pinctrl-names = "default";
1852 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1853 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1854 #address-cells = <1>;
1855 #size-cells = <0>;
1856 power-domains = <&rpmhpd SC7280_CX>;
1857 operating-points-v2 = <&qup_opp_table>;
1858 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1859 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1860 interconnect-names = "qup-core", "qup-config";
1861 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1862 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1863 dma-names = "tx", "rx";
1864 status = "disabled";
1865 };
1866
1867 uart12: serial@a90000 {
1868 compatible = "qcom,geni-uart";
1869 reg = <0 0x00a90000 0 0x4000>;
1870 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1871 clock-names = "se";
1872 pinctrl-names = "default";
1873 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1874 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1875 power-domains = <&rpmhpd SC7280_CX>;
1876 operating-points-v2 = <&qup_opp_table>;
1877 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1878 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1879 interconnect-names = "qup-core", "qup-config";
1880 status = "disabled";
1881 };
1882
1883 i2c13: i2c@a94000 {
1884 compatible = "qcom,geni-i2c";
1885 reg = <0 0x00a94000 0 0x4000>;
1886 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1887 clock-names = "se";
1888 pinctrl-names = "default";
1889 pinctrl-0 = <&qup_i2c13_data_clk>;
1890 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1891 #address-cells = <1>;
1892 #size-cells = <0>;
1893 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1894 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1895 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1896 interconnect-names = "qup-core", "qup-config",
1897 "qup-memory";
1898 power-domains = <&rpmhpd SC7280_CX>;
1899 required-opps = <&rpmhpd_opp_low_svs>;
1900 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1901 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1902 dma-names = "tx", "rx";
1903 status = "disabled";
1904 };
1905
1906 spi13: spi@a94000 {
1907 compatible = "qcom,geni-spi";
1908 reg = <0 0x00a94000 0 0x4000>;
1909 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1910 clock-names = "se";
1911 pinctrl-names = "default";
1912 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1913 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1914 #address-cells = <1>;
1915 #size-cells = <0>;
1916 power-domains = <&rpmhpd SC7280_CX>;
1917 operating-points-v2 = <&qup_opp_table>;
1918 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1919 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1920 interconnect-names = "qup-core", "qup-config";
1921 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1922 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1923 dma-names = "tx", "rx";
1924 status = "disabled";
1925 };
1926
1927 uart13: serial@a94000 {
1928 compatible = "qcom,geni-uart";
1929 reg = <0 0x00a94000 0 0x4000>;
1930 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1931 clock-names = "se";
1932 pinctrl-names = "default";
1933 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1934 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1935 power-domains = <&rpmhpd SC7280_CX>;
1936 operating-points-v2 = <&qup_opp_table>;
1937 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1938 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1939 interconnect-names = "qup-core", "qup-config";
1940 status = "disabled";
1941 };
1942
1943 i2c14: i2c@a98000 {
1944 compatible = "qcom,geni-i2c";
1945 reg = <0 0x00a98000 0 0x4000>;
1946 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1947 clock-names = "se";
1948 pinctrl-names = "default";
1949 pinctrl-0 = <&qup_i2c14_data_clk>;
1950 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1951 #address-cells = <1>;
1952 #size-cells = <0>;
1953 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1954 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1955 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1956 interconnect-names = "qup-core", "qup-config",
1957 "qup-memory";
1958 power-domains = <&rpmhpd SC7280_CX>;
1959 required-opps = <&rpmhpd_opp_low_svs>;
1960 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1961 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1962 dma-names = "tx", "rx";
1963 status = "disabled";
1964 };
1965
1966 spi14: spi@a98000 {
1967 compatible = "qcom,geni-spi";
1968 reg = <0 0x00a98000 0 0x4000>;
1969 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1970 clock-names = "se";
1971 pinctrl-names = "default";
1972 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1973 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1974 #address-cells = <1>;
1975 #size-cells = <0>;
1976 power-domains = <&rpmhpd SC7280_CX>;
1977 operating-points-v2 = <&qup_opp_table>;
1978 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1979 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1980 interconnect-names = "qup-core", "qup-config";
1981 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1982 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1983 dma-names = "tx", "rx";
1984 status = "disabled";
1985 };
1986
1987 uart14: serial@a98000 {
1988 compatible = "qcom,geni-uart";
1989 reg = <0 0x00a98000 0 0x4000>;
1990 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1991 clock-names = "se";
1992 pinctrl-names = "default";
1993 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
1994 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1995 power-domains = <&rpmhpd SC7280_CX>;
1996 operating-points-v2 = <&qup_opp_table>;
1997 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1998 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1999 interconnect-names = "qup-core", "qup-config";
2000 status = "disabled";
2001 };
2002
2003 i2c15: i2c@a9c000 {
2004 compatible = "qcom,geni-i2c";
2005 reg = <0 0x00a9c000 0 0x4000>;
2006 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2007 clock-names = "se";
2008 pinctrl-names = "default";
2009 pinctrl-0 = <&qup_i2c15_data_clk>;
2010 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
2011 #address-cells = <1>;
2012 #size-cells = <0>;
2013 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2014 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
2015 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
2016 interconnect-names = "qup-core", "qup-config",
2017 "qup-memory";
2018 power-domains = <&rpmhpd SC7280_CX>;
2019 required-opps = <&rpmhpd_opp_low_svs>;
2020 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2021 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
2022 dma-names = "tx", "rx";
2023 status = "disabled";
2024 };
2025
2026 spi15: spi@a9c000 {
2027 compatible = "qcom,geni-spi";
2028 reg = <0 0x00a9c000 0 0x4000>;
2029 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2030 clock-names = "se";
2031 pinctrl-names = "default";
2032 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
2033 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
2034 #address-cells = <1>;
2035 #size-cells = <0>;
2036 power-domains = <&rpmhpd SC7280_CX>;
2037 operating-points-v2 = <&qup_opp_table>;
2038 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2039 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
2040 interconnect-names = "qup-core", "qup-config";
2041 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2042 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
2043 dma-names = "tx", "rx";
2044 status = "disabled";
2045 };
2046
2047 uart15: serial@a9c000 {
2048 compatible = "qcom,geni-uart";
2049 reg = <0 0x00a9c000 0 0x4000>;
2050 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2051 clock-names = "se";
2052 pinctrl-names = "default";
2053 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
2054 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
2055 power-domains = <&rpmhpd SC7280_CX>;
2056 operating-points-v2 = <&qup_opp_table>;
2057 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2058 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
2059 interconnect-names = "qup-core", "qup-config";
2060 status = "disabled";
2061 };
2062 };
2063
2064 rng: rng@10d3000 {
2065 compatible = "qcom,sc7280-trng", "qcom,trng";
2066 reg = <0 0x010d3000 0 0x1000>;
2067 };
2068
2069 cnoc2: interconnect@1500000 {
2070 reg = <0 0x01500000 0 0x1000>;
2071 compatible = "qcom,sc7280-cnoc2";
2072 #interconnect-cells = <2>;
2073 qcom,bcm-voters = <&apps_bcm_voter>;
2074 };
2075
2076 cnoc3: interconnect@1502000 {
2077 reg = <0 0x01502000 0 0x1000>;
2078 compatible = "qcom,sc7280-cnoc3";
2079 #interconnect-cells = <2>;
2080 qcom,bcm-voters = <&apps_bcm_voter>;
2081 };
2082
2083 mc_virt: interconnect@1580000 {
2084 reg = <0 0x01580000 0 0x4>;
2085 compatible = "qcom,sc7280-mc-virt";
2086 #interconnect-cells = <2>;
2087 qcom,bcm-voters = <&apps_bcm_voter>;
2088 };
2089
2090 system_noc: interconnect@1680000 {
2091 reg = <0 0x01680000 0 0x15480>;
2092 compatible = "qcom,sc7280-system-noc";
2093 #interconnect-cells = <2>;
2094 qcom,bcm-voters = <&apps_bcm_voter>;
2095 };
2096
2097 aggre1_noc: interconnect@16e0000 {
2098 compatible = "qcom,sc7280-aggre1-noc";
2099 reg = <0 0x016e0000 0 0x1c080>;
2100 #interconnect-cells = <2>;
2101 qcom,bcm-voters = <&apps_bcm_voter>;
2102 };
2103
2104 aggre2_noc: interconnect@1700000 {
2105 reg = <0 0x01700000 0 0x2b080>;
2106 compatible = "qcom,sc7280-aggre2-noc";
2107 #interconnect-cells = <2>;
2108 qcom,bcm-voters = <&apps_bcm_voter>;
2109 };
2110
2111 mmss_noc: interconnect@1740000 {
2112 reg = <0 0x01740000 0 0x1e080>;
2113 compatible = "qcom,sc7280-mmss-noc";
2114 #interconnect-cells = <2>;
2115 qcom,bcm-voters = <&apps_bcm_voter>;
2116 };
2117
2118 wifi: wifi@17a10040 {
2119 compatible = "qcom,wcn6750-wifi";
2120 reg = <0 0x17a10040 0 0x0>;
2121 iommus = <&apps_smmu 0x1c00 0x1>;
2122 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
2123 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
2124 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
2125 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
2126 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
2127 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
2128 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
2129 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
2130 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
2131 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
2132 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
2133 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
2134 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
2135 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
2136 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
2137 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
2138 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
2139 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
2140 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
2141 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
2142 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
2143 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
2144 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
2145 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
2146 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
2147 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
2148 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
2149 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
2150 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
2151 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
2152 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
2153 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
2154 qcom,rproc = <&remoteproc_wpss>;
2155 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
2156 status = "disabled";
2157 qcom,smem-states = <&wlan_smp2p_out 0>;
2158 qcom,smem-state-names = "wlan-smp2p-out";
2159 };
2160
2161 pcie1: pcie@1c08000 {
2162 compatible = "qcom,pcie-sc7280";
2163 reg = <0 0x01c08000 0 0x3000>,
2164 <0 0x40000000 0 0xf1d>,
2165 <0 0x40000f20 0 0xa8>,
2166 <0 0x40001000 0 0x1000>,
2167 <0 0x40100000 0 0x100000>;
2168
2169 reg-names = "parf", "dbi", "elbi", "atu", "config";
2170 device_type = "pci";
2171 linux,pci-domain = <1>;
2172 bus-range = <0x00 0xff>;
2173 num-lanes = <2>;
2174
2175 #address-cells = <3>;
2176 #size-cells = <2>;
2177
2178 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2179 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2180
2181 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
2182 interrupt-names = "msi";
2183 #interrupt-cells = <1>;
2184 interrupt-map-mask = <0 0 0 0x7>;
2185 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2186 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
2187 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
2188 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
2189
2190 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2191 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
2192 <&pcie1_phy>,
2193 <&rpmhcc RPMH_CXO_CLK>,
2194 <&gcc GCC_PCIE_1_AUX_CLK>,
2195 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2196 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2197 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2198 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2199 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2200 <&gcc GCC_DDRSS_PCIE_SF_CLK>,
2201 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
2202 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
2203
2204 clock-names = "pipe",
2205 "pipe_mux",
2206 "phy_pipe",
2207 "ref",
2208 "aux",
2209 "cfg",
2210 "bus_master",
2211 "bus_slave",
2212 "slave_q2a",
2213 "tbu",
2214 "ddrss_sf_tbu",
2215 "aggre0",
2216 "aggre1";
2217
2218 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2219 assigned-clock-rates = <19200000>;
2220
2221 resets = <&gcc GCC_PCIE_1_BCR>;
2222 reset-names = "pci";
2223
2224 power-domains = <&gcc GCC_PCIE_1_GDSC>;
2225
2226 phys = <&pcie1_phy>;
2227 phy-names = "pciephy";
2228
2229 pinctrl-names = "default";
2230 pinctrl-0 = <&pcie1_clkreq_n>;
2231
2232 dma-coherent;
2233
2234 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2235 <0x100 &apps_smmu 0x1c81 0x1>;
2236
2237 status = "disabled";
2238 };
2239
2240 pcie1_phy: phy@1c0e000 {
2241 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2242 reg = <0 0x01c0e000 0 0x1000>;
2243 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
2244 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2245 <&gcc GCC_PCIE_CLKREF_EN>,
2246 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>,
2247 <&gcc GCC_PCIE_1_PIPE_CLK>;
2248 clock-names = "aux",
2249 "cfg_ahb",
2250 "ref",
2251 "refgen",
2252 "pipe";
2253
2254 clock-output-names = "pcie_1_pipe_clk";
2255 #clock-cells = <0>;
2256
2257 #phy-cells = <0>;
2258
2259 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2260 reset-names = "phy";
2261
2262 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
2263 assigned-clock-rates = <100000000>;
2264
2265 status = "disabled";
2266 };
2267
2268 ufs_mem_hc: ufs@1d84000 {
2269 compatible = "qcom,sc7280-ufshc", "qcom,ufshc",
2270 "jedec,ufs-2.0";
2271 reg = <0x0 0x01d84000 0x0 0x3000>;
2272 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2273 phys = <&ufs_mem_phy>;
2274 phy-names = "ufsphy";
2275 lanes-per-direction = <2>;
2276 #reset-cells = <1>;
2277 resets = <&gcc GCC_UFS_PHY_BCR>;
2278 reset-names = "rst";
2279
2280 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
2281 required-opps = <&rpmhpd_opp_nom>;
2282
2283 iommus = <&apps_smmu 0x80 0x0>;
2284 dma-coherent;
2285
2286 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
2287 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
2288 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
2289 &cnoc2 SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
2290 interconnect-names = "ufs-ddr", "cpu-ufs";
2291
2292 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2293 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2294 <&gcc GCC_UFS_PHY_AHB_CLK>,
2295 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2296 <&rpmhcc RPMH_CXO_CLK>,
2297 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2298 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2299 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2300 clock-names = "core_clk",
2301 "bus_aggr_clk",
2302 "iface_clk",
2303 "core_clk_unipro",
2304 "ref_clk",
2305 "tx_lane0_sync_clk",
2306 "rx_lane0_sync_clk",
2307 "rx_lane1_sync_clk";
2308 freq-table-hz =
2309 <75000000 300000000>,
2310 <0 0>,
2311 <0 0>,
2312 <75000000 300000000>,
2313 <0 0>,
2314 <0 0>,
2315 <0 0>,
2316 <0 0>;
2317 status = "disabled";
2318 };
2319
2320 ufs_mem_phy: phy@1d87000 {
2321 compatible = "qcom,sc7280-qmp-ufs-phy";
2322 reg = <0x0 0x01d87000 0x0 0xe00>;
2323 clocks = <&rpmhcc RPMH_CXO_CLK>,
2324 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2325 <&gcc GCC_UFS_1_CLKREF_EN>;
2326 clock-names = "ref", "ref_aux", "qref";
2327
2328 power-domains = <&rpmhpd SC7280_MX>;
2329
2330 resets = <&ufs_mem_hc 0>;
2331 reset-names = "ufsphy";
2332
2333 #clock-cells = <1>;
2334 #phy-cells = <0>;
2335
2336 status = "disabled";
2337 };
2338
2339 cryptobam: dma-controller@1dc4000 {
2340 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2341 reg = <0x0 0x01dc4000 0x0 0x28000>;
2342 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2343 #dma-cells = <1>;
2344 iommus = <&apps_smmu 0x4e4 0x0011>,
2345 <&apps_smmu 0x4e6 0x0011>;
2346 qcom,ee = <0>;
2347 qcom,controlled-remotely;
2348 };
2349
2350 crypto: crypto@1dfa000 {
2351 compatible = "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce";
2352 reg = <0x0 0x01dfa000 0x0 0x6000>;
2353 dmas = <&cryptobam 4>, <&cryptobam 5>;
2354 dma-names = "rx", "tx";
2355 iommus = <&apps_smmu 0x4e4 0x0011>,
2356 <&apps_smmu 0x4e4 0x0011>;
2357 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
2358 interconnect-names = "memory";
2359 };
2360
2361 ipa: ipa@1e40000 {
2362 compatible = "qcom,sc7280-ipa";
2363
2364 iommus = <&apps_smmu 0x480 0x0>,
2365 <&apps_smmu 0x482 0x0>;
2366 reg = <0 0x01e40000 0 0x8000>,
2367 <0 0x01e50000 0 0x4ad0>,
2368 <0 0x01e04000 0 0x23000>;
2369 reg-names = "ipa-reg",
2370 "ipa-shared",
2371 "gsi";
2372
2373 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2374 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2375 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2376 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2377 interrupt-names = "ipa",
2378 "gsi",
2379 "ipa-clock-query",
2380 "ipa-setup-ready";
2381
2382 clocks = <&rpmhcc RPMH_IPA_CLK>;
2383 clock-names = "core";
2384
2385 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2386 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
2387 interconnect-names = "memory",
2388 "config";
2389
2390 qcom,qmp = <&aoss_qmp>;
2391
2392 qcom,smem-states = <&ipa_smp2p_out 0>,
2393 <&ipa_smp2p_out 1>;
2394 qcom,smem-state-names = "ipa-clock-enabled-valid",
2395 "ipa-clock-enabled";
2396
2397 status = "disabled";
2398 };
2399
2400 tcsr_mutex: hwlock@1f40000 {
2401 compatible = "qcom,tcsr-mutex";
2402 reg = <0 0x01f40000 0 0x20000>;
2403 #hwlock-cells = <1>;
2404 };
2405
2406 tcsr_1: syscon@1f60000 {
2407 compatible = "qcom,sc7280-tcsr", "syscon";
2408 reg = <0 0x01f60000 0 0x20000>;
2409 };
2410
2411 tcsr_2: syscon@1fc0000 {
2412 compatible = "qcom,sc7280-tcsr", "syscon";
2413 reg = <0 0x01fc0000 0 0x30000>;
2414 };
2415
2416 lpasscc: lpasscc@3000000 {
2417 compatible = "qcom,sc7280-lpasscc";
2418 reg = <0 0x03000000 0 0x40>,
2419 <0 0x03c04000 0 0x4>;
2420 reg-names = "qdsp6ss", "top_cc";
2421 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
2422 clock-names = "iface";
2423 #clock-cells = <1>;
2424 status = "reserved"; /* Owned by ADSP firmware */
2425 };
2426
2427 lpass_rx_macro: codec@3200000 {
2428 compatible = "qcom,sc7280-lpass-rx-macro";
2429 reg = <0 0x03200000 0 0x1000>;
2430
2431 pinctrl-names = "default";
2432 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
2433
2434 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>,
2435 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>,
2436 <&lpass_va_macro>;
2437 clock-names = "mclk", "npl", "fsgen";
2438
2439 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2440 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2441 power-domain-names = "macro", "dcodec";
2442
2443 #clock-cells = <0>;
2444 #sound-dai-cells = <1>;
2445
2446 status = "disabled";
2447 };
2448
2449 swr0: soundwire@3210000 {
2450 compatible = "qcom,soundwire-v1.6.0";
2451 reg = <0 0x03210000 0 0x2000>;
2452
2453 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2454 clocks = <&lpass_rx_macro>;
2455 clock-names = "iface";
2456
2457 qcom,din-ports = <0>;
2458 qcom,dout-ports = <5>;
2459
2460 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
2461 reset-names = "swr_audio_cgcr";
2462
2463 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2464 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
2465 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
2466 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2467 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2468 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2469 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2470 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2471 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2472
2473 #sound-dai-cells = <1>;
2474 #address-cells = <2>;
2475 #size-cells = <0>;
2476
2477 status = "disabled";
2478 };
2479
2480 lpass_tx_macro: codec@3220000 {
2481 compatible = "qcom,sc7280-lpass-tx-macro";
2482 reg = <0 0x03220000 0 0x1000>;
2483
2484 pinctrl-names = "default";
2485 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
2486
2487 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>,
2488 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>,
2489 <&lpass_va_macro>;
2490 clock-names = "mclk", "npl", "fsgen";
2491
2492 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2493 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2494 power-domain-names = "macro", "dcodec";
2495
2496 #clock-cells = <0>;
2497 #sound-dai-cells = <1>;
2498
2499 status = "disabled";
2500 };
2501
2502 swr1: soundwire@3230000 {
2503 compatible = "qcom,soundwire-v1.6.0";
2504 reg = <0 0x03230000 0 0x2000>;
2505
2506 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2507 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>;
2508 clocks = <&lpass_tx_macro>;
2509 clock-names = "iface";
2510
2511 qcom,din-ports = <3>;
2512 qcom,dout-ports = <0>;
2513
2514 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>;
2515 reset-names = "swr_audio_cgcr";
2516
2517 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>;
2518 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>;
2519 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>;
2520 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>;
2521 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>;
2522 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>;
2523 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
2524 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
2525 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
2526
2527 #sound-dai-cells = <1>;
2528 #address-cells = <2>;
2529 #size-cells = <0>;
2530
2531 status = "disabled";
2532 };
2533
2534 lpass_audiocc: clock-controller@3300000 {
2535 compatible = "qcom,sc7280-lpassaudiocc";
2536 reg = <0 0x03300000 0 0x30000>,
2537 <0 0x032a9000 0 0x1000>;
2538 clocks = <&rpmhcc RPMH_CXO_CLK>,
2539 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
2540 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
2541 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2542 #clock-cells = <1>;
2543 #power-domain-cells = <1>;
2544 #reset-cells = <1>;
2545 };
2546
2547 lpass_va_macro: codec@3370000 {
2548 compatible = "qcom,sc7280-lpass-va-macro";
2549 reg = <0 0x03370000 0 0x1000>;
2550
2551 pinctrl-names = "default";
2552 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>;
2553
2554 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>;
2555 clock-names = "mclk";
2556
2557 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2558 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2559 power-domain-names = "macro", "dcodec";
2560
2561 #clock-cells = <0>;
2562 #sound-dai-cells = <1>;
2563
2564 status = "disabled";
2565 };
2566
2567 lpass_aon: clock-controller@3380000 {
2568 compatible = "qcom,sc7280-lpassaoncc";
2569 reg = <0 0x03380000 0 0x30000>;
2570 clocks = <&rpmhcc RPMH_CXO_CLK>,
2571 <&rpmhcc RPMH_CXO_CLK_A>,
2572 <&lpass_core LPASS_CORE_CC_CORE_CLK>;
2573 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
2574 #clock-cells = <1>;
2575 #power-domain-cells = <1>;
2576 status = "reserved"; /* Owned by ADSP firmware */
2577 };
2578
2579 lpass_core: clock-controller@3900000 {
2580 compatible = "qcom,sc7280-lpasscorecc";
2581 reg = <0 0x03900000 0 0x50000>;
2582 clocks = <&rpmhcc RPMH_CXO_CLK>;
2583 clock-names = "bi_tcxo";
2584 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
2585 #clock-cells = <1>;
2586 #power-domain-cells = <1>;
2587 status = "reserved"; /* Owned by ADSP firmware */
2588 };
2589
2590 lpass_cpu: audio@3987000 {
2591 compatible = "qcom,sc7280-lpass-cpu";
2592
2593 reg = <0 0x03987000 0 0x68000>,
2594 <0 0x03b00000 0 0x29000>,
2595 <0 0x03260000 0 0xc000>,
2596 <0 0x03280000 0 0x29000>,
2597 <0 0x03340000 0 0x29000>,
2598 <0 0x0336c000 0 0x3000>;
2599 reg-names = "lpass-hdmiif",
2600 "lpass-lpaif",
2601 "lpass-rxtx-cdc-dma-lpm",
2602 "lpass-rxtx-lpaif",
2603 "lpass-va-lpaif",
2604 "lpass-va-cdc-dma-lpm";
2605
2606 iommus = <&apps_smmu 0x1820 0>,
2607 <&apps_smmu 0x1821 0>,
2608 <&apps_smmu 0x1832 0>;
2609
2610 power-domains = <&rpmhpd SC7280_LCX>;
2611 power-domain-names = "lcx";
2612 required-opps = <&rpmhpd_opp_nom>;
2613
2614 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>,
2615 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>,
2616 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>,
2617 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>,
2618 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>,
2619 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>,
2620 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>,
2621 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>,
2622 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>,
2623 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>;
2624 clock-names = "aon_cc_audio_hm_h",
2625 "audio_cc_ext_mclk0",
2626 "core_cc_sysnoc_mport_core",
2627 "core_cc_ext_if0_ibit",
2628 "core_cc_ext_if1_ibit",
2629 "audio_cc_codec_mem",
2630 "audio_cc_codec_mem0",
2631 "audio_cc_codec_mem1",
2632 "audio_cc_codec_mem2",
2633 "aon_cc_va_mem0";
2634
2635 #sound-dai-cells = <1>;
2636 #address-cells = <1>;
2637 #size-cells = <0>;
2638
2639 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
2640 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2641 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
2642 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
2643 interrupt-names = "lpass-irq-lpaif",
2644 "lpass-irq-hdmi",
2645 "lpass-irq-vaif",
2646 "lpass-irq-rxtxif";
2647
2648 status = "disabled";
2649 };
2650
2651 lpass_hm: clock-controller@3c00000 {
2652 compatible = "qcom,sc7280-lpasshm";
2653 reg = <0 0x03c00000 0 0x28>;
2654 clocks = <&rpmhcc RPMH_CXO_CLK>;
2655 clock-names = "bi_tcxo";
2656 #clock-cells = <1>;
2657 #power-domain-cells = <1>;
2658 status = "reserved"; /* Owned by ADSP firmware */
2659 };
2660
2661 lpass_ag_noc: interconnect@3c40000 {
2662 reg = <0 0x03c40000 0 0xf080>;
2663 compatible = "qcom,sc7280-lpass-ag-noc";
2664 #interconnect-cells = <2>;
2665 qcom,bcm-voters = <&apps_bcm_voter>;
2666 };
2667
2668 lpass_tlmm: pinctrl@33c0000 {
2669 compatible = "qcom,sc7280-lpass-lpi-pinctrl";
2670 reg = <0 0x033c0000 0x0 0x20000>,
2671 <0 0x03550000 0x0 0x10000>;
2672 gpio-controller;
2673 #gpio-cells = <2>;
2674 gpio-ranges = <&lpass_tlmm 0 0 15>;
2675
2676 lpass_dmic01_clk: dmic01-clk-state {
2677 pins = "gpio6";
2678 function = "dmic1_clk";
2679 };
2680
2681 lpass_dmic01_data: dmic01-data-state {
2682 pins = "gpio7";
2683 function = "dmic1_data";
2684 };
2685
2686 lpass_dmic23_clk: dmic23-clk-state {
2687 pins = "gpio8";
2688 function = "dmic2_clk";
2689 };
2690
2691 lpass_dmic23_data: dmic23-data-state {
2692 pins = "gpio9";
2693 function = "dmic2_data";
2694 };
2695
2696 lpass_rx_swr_clk: rx-swr-clk-state {
2697 pins = "gpio3";
2698 function = "swr_rx_clk";
2699 };
2700
2701 lpass_rx_swr_data: rx-swr-data-state {
2702 pins = "gpio4", "gpio5";
2703 function = "swr_rx_data";
2704 };
2705
2706 lpass_tx_swr_clk: tx-swr-clk-state {
2707 pins = "gpio0";
2708 function = "swr_tx_clk";
2709 };
2710
2711 lpass_tx_swr_data: tx-swr-data-state {
2712 pins = "gpio1", "gpio2", "gpio14";
2713 function = "swr_tx_data";
2714 };
2715 };
2716
2717 gpu: gpu@3d00000 {
2718 compatible = "qcom,adreno-635.0", "qcom,adreno";
2719 reg = <0 0x03d00000 0 0x40000>,
2720 <0 0x03d9e000 0 0x1000>,
2721 <0 0x03d61000 0 0x800>;
2722 reg-names = "kgsl_3d0_reg_memory",
2723 "cx_mem",
2724 "cx_dbgc";
2725 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2726 iommus = <&adreno_smmu 0 0x400>,
2727 <&adreno_smmu 1 0x400>;
2728 operating-points-v2 = <&gpu_opp_table>;
2729 qcom,gmu = <&gmu>;
2730 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2731 interconnect-names = "gfx-mem";
2732 #cooling-cells = <2>;
2733
2734 nvmem-cells = <&gpu_speed_bin>;
2735 nvmem-cell-names = "speed_bin";
2736
2737 gpu_zap_shader: zap-shader {
2738 memory-region = <&gpu_zap_mem>;
2739 };
2740
2741 gpu_opp_table: opp-table {
2742 compatible = "operating-points-v2";
2743
2744 opp-315000000 {
2745 opp-hz = /bits/ 64 <315000000>;
2746 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2747 opp-peak-kBps = <1804000>;
2748 opp-supported-hw = <0x07>;
2749 };
2750
2751 opp-450000000 {
2752 opp-hz = /bits/ 64 <450000000>;
2753 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2754 opp-peak-kBps = <4068000>;
2755 opp-supported-hw = <0x07>;
2756 };
2757
2758 /* Only applicable for SKUs which has 550Mhz as Fmax */
2759 opp-550000000-0 {
2760 opp-hz = /bits/ 64 <550000000>;
2761 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2762 opp-peak-kBps = <8368000>;
2763 opp-supported-hw = <0x01>;
2764 };
2765
2766 opp-550000000-1 {
2767 opp-hz = /bits/ 64 <550000000>;
2768 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2769 opp-peak-kBps = <6832000>;
2770 opp-supported-hw = <0x06>;
2771 };
2772
2773 opp-608000000 {
2774 opp-hz = /bits/ 64 <608000000>;
2775 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2776 opp-peak-kBps = <8368000>;
2777 opp-supported-hw = <0x06>;
2778 };
2779
2780 opp-700000000 {
2781 opp-hz = /bits/ 64 <700000000>;
2782 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2783 opp-peak-kBps = <8532000>;
2784 opp-supported-hw = <0x06>;
2785 };
2786
2787 opp-812000000 {
2788 opp-hz = /bits/ 64 <812000000>;
2789 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2790 opp-peak-kBps = <8532000>;
2791 opp-supported-hw = <0x06>;
2792 };
2793
2794 opp-840000000 {
2795 opp-hz = /bits/ 64 <840000000>;
2796 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2797 opp-peak-kBps = <8532000>;
2798 opp-supported-hw = <0x02>;
2799 };
2800
2801 opp-900000000 {
2802 opp-hz = /bits/ 64 <900000000>;
2803 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2804 opp-peak-kBps = <8532000>;
2805 opp-supported-hw = <0x02>;
2806 };
2807 };
2808 };
2809
2810 gmu: gmu@3d6a000 {
2811 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
2812 reg = <0 0x03d6a000 0 0x34000>,
2813 <0 0x3de0000 0 0x10000>,
2814 <0 0x0b290000 0 0x10000>;
2815 reg-names = "gmu", "rscc", "gmu_pdc";
2816 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2817 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2818 interrupt-names = "hfi", "gmu";
2819 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2820 <&gpucc GPU_CC_CXO_CLK>,
2821 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2822 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2823 <&gpucc GPU_CC_AHB_CLK>,
2824 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2825 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
2826 clock-names = "gmu",
2827 "cxo",
2828 "axi",
2829 "memnoc",
2830 "ahb",
2831 "hub",
2832 "smmu_vote";
2833 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2834 <&gpucc GPU_CC_GX_GDSC>;
2835 power-domain-names = "cx",
2836 "gx";
2837 iommus = <&adreno_smmu 5 0x400>;
2838 operating-points-v2 = <&gmu_opp_table>;
2839
2840 gmu_opp_table: opp-table {
2841 compatible = "operating-points-v2";
2842
2843 opp-200000000 {
2844 opp-hz = /bits/ 64 <200000000>;
2845 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2846 };
2847 };
2848 };
2849
2850 gpucc: clock-controller@3d90000 {
2851 compatible = "qcom,sc7280-gpucc";
2852 reg = <0 0x03d90000 0 0x9000>;
2853 clocks = <&rpmhcc RPMH_CXO_CLK>,
2854 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2855 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2856 clock-names = "bi_tcxo",
2857 "gcc_gpu_gpll0_clk_src",
2858 "gcc_gpu_gpll0_div_clk_src";
2859 #clock-cells = <1>;
2860 #reset-cells = <1>;
2861 #power-domain-cells = <1>;
2862 };
2863
2864 dma@117f000 {
2865 compatible = "qcom,sc7280-dcc", "qcom,dcc";
2866 reg = <0x0 0x0117f000 0x0 0x1000>,
2867 <0x0 0x01112000 0x0 0x6000>;
2868 };
2869
2870 adreno_smmu: iommu@3da0000 {
2871 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu",
2872 "qcom,smmu-500", "arm,mmu-500";
2873 reg = <0 0x03da0000 0 0x20000>;
2874 #iommu-cells = <2>;
2875 #global-interrupts = <2>;
2876 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2877 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
2878 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2879 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2880 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2881 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2882 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2883 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2884 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2885 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2886 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2887 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
2888
2889 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2890 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2891 <&gpucc GPU_CC_AHB_CLK>,
2892 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2893 <&gpucc GPU_CC_CX_GMU_CLK>,
2894 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2895 <&gpucc GPU_CC_HUB_AON_CLK>;
2896 clock-names = "gcc_gpu_memnoc_gfx_clk",
2897 "gcc_gpu_snoc_dvm_gfx_clk",
2898 "gpu_cc_ahb_clk",
2899 "gpu_cc_hlos1_vote_gpu_smmu_clk",
2900 "gpu_cc_cx_gmu_clk",
2901 "gpu_cc_hub_cx_int_clk",
2902 "gpu_cc_hub_aon_clk";
2903
2904 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2905 dma-coherent;
2906 };
2907
2908 remoteproc_mpss: remoteproc@4080000 {
2909 compatible = "qcom,sc7280-mpss-pas";
2910 reg = <0 0x04080000 0 0x10000>;
2911
2912 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2913 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2914 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2915 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2916 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2917 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2918 interrupt-names = "wdog", "fatal", "ready", "handover",
2919 "stop-ack", "shutdown-ack";
2920
2921 clocks = <&rpmhcc RPMH_CXO_CLK>;
2922 clock-names = "xo";
2923
2924 power-domains = <&rpmhpd SC7280_CX>,
2925 <&rpmhpd SC7280_MSS>;
2926 power-domain-names = "cx", "mss";
2927
2928 memory-region = <&mpss_mem>;
2929
2930 qcom,qmp = <&aoss_qmp>;
2931
2932 qcom,smem-states = <&modem_smp2p_out 0>;
2933 qcom,smem-state-names = "stop";
2934
2935 status = "disabled";
2936
2937 glink-edge {
2938 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2939 IPCC_MPROC_SIGNAL_GLINK_QMP
2940 IRQ_TYPE_EDGE_RISING>;
2941 mboxes = <&ipcc IPCC_CLIENT_MPSS
2942 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2943 label = "modem";
2944 qcom,remote-pid = <1>;
2945 };
2946 };
2947
2948 stm@6002000 {
2949 compatible = "arm,coresight-stm", "arm,primecell";
2950 reg = <0 0x06002000 0 0x1000>,
2951 <0 0x16280000 0 0x180000>;
2952 reg-names = "stm-base", "stm-stimulus-base";
2953
2954 clocks = <&aoss_qmp>;
2955 clock-names = "apb_pclk";
2956
2957 out-ports {
2958 port {
2959 stm_out: endpoint {
2960 remote-endpoint = <&funnel0_in7>;
2961 };
2962 };
2963 };
2964 };
2965
2966 funnel@6041000 {
2967 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2968 reg = <0 0x06041000 0 0x1000>;
2969
2970 clocks = <&aoss_qmp>;
2971 clock-names = "apb_pclk";
2972
2973 out-ports {
2974 port {
2975 funnel0_out: endpoint {
2976 remote-endpoint = <&merge_funnel_in0>;
2977 };
2978 };
2979 };
2980
2981 in-ports {
2982 #address-cells = <1>;
2983 #size-cells = <0>;
2984
2985 port@7 {
2986 reg = <7>;
2987 funnel0_in7: endpoint {
2988 remote-endpoint = <&stm_out>;
2989 };
2990 };
2991 };
2992 };
2993
2994 funnel@6042000 {
2995 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2996 reg = <0 0x06042000 0 0x1000>;
2997
2998 clocks = <&aoss_qmp>;
2999 clock-names = "apb_pclk";
3000
3001 out-ports {
3002 port {
3003 funnel1_out: endpoint {
3004 remote-endpoint = <&merge_funnel_in1>;
3005 };
3006 };
3007 };
3008
3009 in-ports {
3010 #address-cells = <1>;
3011 #size-cells = <0>;
3012
3013 port@4 {
3014 reg = <4>;
3015 funnel1_in4: endpoint {
3016 remote-endpoint = <&apss_merge_funnel_out>;
3017 };
3018 };
3019 };
3020 };
3021
3022 funnel@6045000 {
3023 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3024 reg = <0 0x06045000 0 0x1000>;
3025
3026 clocks = <&aoss_qmp>;
3027 clock-names = "apb_pclk";
3028
3029 out-ports {
3030 port {
3031 merge_funnel_out: endpoint {
3032 remote-endpoint = <&swao_funnel_in>;
3033 };
3034 };
3035 };
3036
3037 in-ports {
3038 #address-cells = <1>;
3039 #size-cells = <0>;
3040
3041 port@0 {
3042 reg = <0>;
3043 merge_funnel_in0: endpoint {
3044 remote-endpoint = <&funnel0_out>;
3045 };
3046 };
3047
3048 port@1 {
3049 reg = <1>;
3050 merge_funnel_in1: endpoint {
3051 remote-endpoint = <&funnel1_out>;
3052 };
3053 };
3054 };
3055 };
3056
3057 replicator@6046000 {
3058 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3059 reg = <0 0x06046000 0 0x1000>;
3060
3061 clocks = <&aoss_qmp>;
3062 clock-names = "apb_pclk";
3063
3064 out-ports {
3065 port {
3066 replicator_out: endpoint {
3067 remote-endpoint = <&etr_in>;
3068 };
3069 };
3070 };
3071
3072 in-ports {
3073 port {
3074 replicator_in: endpoint {
3075 remote-endpoint = <&swao_replicator_out>;
3076 };
3077 };
3078 };
3079 };
3080
3081 etr@6048000 {
3082 compatible = "arm,coresight-tmc", "arm,primecell";
3083 reg = <0 0x06048000 0 0x1000>;
3084 iommus = <&apps_smmu 0x04c0 0>;
3085
3086 clocks = <&aoss_qmp>;
3087 clock-names = "apb_pclk";
3088 arm,scatter-gather;
3089
3090 in-ports {
3091 port {
3092 etr_in: endpoint {
3093 remote-endpoint = <&replicator_out>;
3094 };
3095 };
3096 };
3097 };
3098
3099 funnel@6b04000 {
3100 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3101 reg = <0 0x06b04000 0 0x1000>;
3102
3103 clocks = <&aoss_qmp>;
3104 clock-names = "apb_pclk";
3105
3106 out-ports {
3107 port {
3108 swao_funnel_out: endpoint {
3109 remote-endpoint = <&etf_in>;
3110 };
3111 };
3112 };
3113
3114 in-ports {
3115 #address-cells = <1>;
3116 #size-cells = <0>;
3117
3118 port@7 {
3119 reg = <7>;
3120 swao_funnel_in: endpoint {
3121 remote-endpoint = <&merge_funnel_out>;
3122 };
3123 };
3124 };
3125 };
3126
3127 etf@6b05000 {
3128 compatible = "arm,coresight-tmc", "arm,primecell";
3129 reg = <0 0x06b05000 0 0x1000>;
3130
3131 clocks = <&aoss_qmp>;
3132 clock-names = "apb_pclk";
3133
3134 out-ports {
3135 port {
3136 etf_out: endpoint {
3137 remote-endpoint = <&swao_replicator_in>;
3138 };
3139 };
3140 };
3141
3142 in-ports {
3143 port {
3144 etf_in: endpoint {
3145 remote-endpoint = <&swao_funnel_out>;
3146 };
3147 };
3148 };
3149 };
3150
3151 replicator@6b06000 {
3152 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3153 reg = <0 0x06b06000 0 0x1000>;
3154
3155 clocks = <&aoss_qmp>;
3156 clock-names = "apb_pclk";
3157 qcom,replicator-loses-context;
3158
3159 out-ports {
3160 port {
3161 swao_replicator_out: endpoint {
3162 remote-endpoint = <&replicator_in>;
3163 };
3164 };
3165 };
3166
3167 in-ports {
3168 port {
3169 swao_replicator_in: endpoint {
3170 remote-endpoint = <&etf_out>;
3171 };
3172 };
3173 };
3174 };
3175
3176 etm@7040000 {
3177 compatible = "arm,coresight-etm4x", "arm,primecell";
3178 reg = <0 0x07040000 0 0x1000>;
3179
3180 cpu = <&CPU0>;
3181
3182 clocks = <&aoss_qmp>;
3183 clock-names = "apb_pclk";
3184 arm,coresight-loses-context-with-cpu;
3185 qcom,skip-power-up;
3186
3187 out-ports {
3188 port {
3189 etm0_out: endpoint {
3190 remote-endpoint = <&apss_funnel_in0>;
3191 };
3192 };
3193 };
3194 };
3195
3196 etm@7140000 {
3197 compatible = "arm,coresight-etm4x", "arm,primecell";
3198 reg = <0 0x07140000 0 0x1000>;
3199
3200 cpu = <&CPU1>;
3201
3202 clocks = <&aoss_qmp>;
3203 clock-names = "apb_pclk";
3204 arm,coresight-loses-context-with-cpu;
3205 qcom,skip-power-up;
3206
3207 out-ports {
3208 port {
3209 etm1_out: endpoint {
3210 remote-endpoint = <&apss_funnel_in1>;
3211 };
3212 };
3213 };
3214 };
3215
3216 etm@7240000 {
3217 compatible = "arm,coresight-etm4x", "arm,primecell";
3218 reg = <0 0x07240000 0 0x1000>;
3219
3220 cpu = <&CPU2>;
3221
3222 clocks = <&aoss_qmp>;
3223 clock-names = "apb_pclk";
3224 arm,coresight-loses-context-with-cpu;
3225 qcom,skip-power-up;
3226
3227 out-ports {
3228 port {
3229 etm2_out: endpoint {
3230 remote-endpoint = <&apss_funnel_in2>;
3231 };
3232 };
3233 };
3234 };
3235
3236 etm@7340000 {
3237 compatible = "arm,coresight-etm4x", "arm,primecell";
3238 reg = <0 0x07340000 0 0x1000>;
3239
3240 cpu = <&CPU3>;
3241
3242 clocks = <&aoss_qmp>;
3243 clock-names = "apb_pclk";
3244 arm,coresight-loses-context-with-cpu;
3245 qcom,skip-power-up;
3246
3247 out-ports {
3248 port {
3249 etm3_out: endpoint {
3250 remote-endpoint = <&apss_funnel_in3>;
3251 };
3252 };
3253 };
3254 };
3255
3256 etm@7440000 {
3257 compatible = "arm,coresight-etm4x", "arm,primecell";
3258 reg = <0 0x07440000 0 0x1000>;
3259
3260 cpu = <&CPU4>;
3261
3262 clocks = <&aoss_qmp>;
3263 clock-names = "apb_pclk";
3264 arm,coresight-loses-context-with-cpu;
3265 qcom,skip-power-up;
3266
3267 out-ports {
3268 port {
3269 etm4_out: endpoint {
3270 remote-endpoint = <&apss_funnel_in4>;
3271 };
3272 };
3273 };
3274 };
3275
3276 etm@7540000 {
3277 compatible = "arm,coresight-etm4x", "arm,primecell";
3278 reg = <0 0x07540000 0 0x1000>;
3279
3280 cpu = <&CPU5>;
3281
3282 clocks = <&aoss_qmp>;
3283 clock-names = "apb_pclk";
3284 arm,coresight-loses-context-with-cpu;
3285 qcom,skip-power-up;
3286
3287 out-ports {
3288 port {
3289 etm5_out: endpoint {
3290 remote-endpoint = <&apss_funnel_in5>;
3291 };
3292 };
3293 };
3294 };
3295
3296 etm@7640000 {
3297 compatible = "arm,coresight-etm4x", "arm,primecell";
3298 reg = <0 0x07640000 0 0x1000>;
3299
3300 cpu = <&CPU6>;
3301
3302 clocks = <&aoss_qmp>;
3303 clock-names = "apb_pclk";
3304 arm,coresight-loses-context-with-cpu;
3305 qcom,skip-power-up;
3306
3307 out-ports {
3308 port {
3309 etm6_out: endpoint {
3310 remote-endpoint = <&apss_funnel_in6>;
3311 };
3312 };
3313 };
3314 };
3315
3316 etm@7740000 {
3317 compatible = "arm,coresight-etm4x", "arm,primecell";
3318 reg = <0 0x07740000 0 0x1000>;
3319
3320 cpu = <&CPU7>;
3321
3322 clocks = <&aoss_qmp>;
3323 clock-names = "apb_pclk";
3324 arm,coresight-loses-context-with-cpu;
3325 qcom,skip-power-up;
3326
3327 out-ports {
3328 port {
3329 etm7_out: endpoint {
3330 remote-endpoint = <&apss_funnel_in7>;
3331 };
3332 };
3333 };
3334 };
3335
3336 funnel@7800000 { /* APSS Funnel */
3337 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3338 reg = <0 0x07800000 0 0x1000>;
3339
3340 clocks = <&aoss_qmp>;
3341 clock-names = "apb_pclk";
3342
3343 out-ports {
3344 port {
3345 apss_funnel_out: endpoint {
3346 remote-endpoint = <&apss_merge_funnel_in>;
3347 };
3348 };
3349 };
3350
3351 in-ports {
3352 #address-cells = <1>;
3353 #size-cells = <0>;
3354
3355 port@0 {
3356 reg = <0>;
3357 apss_funnel_in0: endpoint {
3358 remote-endpoint = <&etm0_out>;
3359 };
3360 };
3361
3362 port@1 {
3363 reg = <1>;
3364 apss_funnel_in1: endpoint {
3365 remote-endpoint = <&etm1_out>;
3366 };
3367 };
3368
3369 port@2 {
3370 reg = <2>;
3371 apss_funnel_in2: endpoint {
3372 remote-endpoint = <&etm2_out>;
3373 };
3374 };
3375
3376 port@3 {
3377 reg = <3>;
3378 apss_funnel_in3: endpoint {
3379 remote-endpoint = <&etm3_out>;
3380 };
3381 };
3382
3383 port@4 {
3384 reg = <4>;
3385 apss_funnel_in4: endpoint {
3386 remote-endpoint = <&etm4_out>;
3387 };
3388 };
3389
3390 port@5 {
3391 reg = <5>;
3392 apss_funnel_in5: endpoint {
3393 remote-endpoint = <&etm5_out>;
3394 };
3395 };
3396
3397 port@6 {
3398 reg = <6>;
3399 apss_funnel_in6: endpoint {
3400 remote-endpoint = <&etm6_out>;
3401 };
3402 };
3403
3404 port@7 {
3405 reg = <7>;
3406 apss_funnel_in7: endpoint {
3407 remote-endpoint = <&etm7_out>;
3408 };
3409 };
3410 };
3411 };
3412
3413 funnel@7810000 {
3414 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3415 reg = <0 0x07810000 0 0x1000>;
3416
3417 clocks = <&aoss_qmp>;
3418 clock-names = "apb_pclk";
3419
3420 out-ports {
3421 port {
3422 apss_merge_funnel_out: endpoint {
3423 remote-endpoint = <&funnel1_in4>;
3424 };
3425 };
3426 };
3427
3428 in-ports {
3429 port {
3430 apss_merge_funnel_in: endpoint {
3431 remote-endpoint = <&apss_funnel_out>;
3432 };
3433 };
3434 };
3435 };
3436
3437 sdhc_2: mmc@8804000 {
3438 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
3439 pinctrl-names = "default", "sleep";
3440 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
3441 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
3442 status = "disabled";
3443
3444 reg = <0 0x08804000 0 0x1000>;
3445
3446 iommus = <&apps_smmu 0x100 0x0>;
3447 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
3448 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
3449 interrupt-names = "hc_irq", "pwr_irq";
3450
3451 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3452 <&gcc GCC_SDCC2_APPS_CLK>,
3453 <&rpmhcc RPMH_CXO_CLK>;
3454 clock-names = "iface", "core", "xo";
3455 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3456 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
3457 interconnect-names = "sdhc-ddr","cpu-sdhc";
3458 power-domains = <&rpmhpd SC7280_CX>;
3459 operating-points-v2 = <&sdhc2_opp_table>;
3460
3461 bus-width = <4>;
3462 dma-coherent;
3463
3464 qcom,dll-config = <0x0007642c>;
3465
3466 resets = <&gcc GCC_SDCC2_BCR>;
3467
3468 sdhc2_opp_table: opp-table {
3469 compatible = "operating-points-v2";
3470
3471 opp-100000000 {
3472 opp-hz = /bits/ 64 <100000000>;
3473 required-opps = <&rpmhpd_opp_low_svs>;
3474 opp-peak-kBps = <1800000 400000>;
3475 opp-avg-kBps = <100000 0>;
3476 };
3477
3478 opp-202000000 {
3479 opp-hz = /bits/ 64 <202000000>;
3480 required-opps = <&rpmhpd_opp_nom>;
3481 opp-peak-kBps = <5400000 1600000>;
3482 opp-avg-kBps = <200000 0>;
3483 };
3484 };
3485 };
3486
3487 usb_1_hsphy: phy@88e3000 {
3488 compatible = "qcom,sc7280-usb-hs-phy",
3489 "qcom,usb-snps-hs-7nm-phy";
3490 reg = <0 0x088e3000 0 0x400>;
3491 status = "disabled";
3492 #phy-cells = <0>;
3493
3494 clocks = <&rpmhcc RPMH_CXO_CLK>;
3495 clock-names = "ref";
3496
3497 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3498 };
3499
3500 usb_2_hsphy: phy@88e4000 {
3501 compatible = "qcom,sc7280-usb-hs-phy",
3502 "qcom,usb-snps-hs-7nm-phy";
3503 reg = <0 0x088e4000 0 0x400>;
3504 status = "disabled";
3505 #phy-cells = <0>;
3506
3507 clocks = <&rpmhcc RPMH_CXO_CLK>;
3508 clock-names = "ref";
3509
3510 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3511 };
3512
3513 usb_1_qmpphy: phy@88e8000 {
3514 compatible = "qcom,sc7280-qmp-usb3-dp-phy";
3515 reg = <0 0x088e8000 0 0x3000>;
3516 status = "disabled";
3517
3518 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3519 <&rpmhcc RPMH_CXO_CLK>,
3520 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3521 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3522 clock-names = "aux",
3523 "ref",
3524 "com_aux",
3525 "usb3_pipe";
3526
3527 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3528 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3529 reset-names = "phy", "common";
3530
3531 #clock-cells = <1>;
3532 #phy-cells = <1>;
3533
3534 ports {
3535 #address-cells = <1>;
3536 #size-cells = <0>;
3537
3538 port@0 {
3539 reg = <0>;
3540
3541 usb_dp_qmpphy_out: endpoint {
3542 };
3543 };
3544
3545 port@1 {
3546 reg = <1>;
3547
3548 usb_dp_qmpphy_usb_ss_in: endpoint {
3549 };
3550 };
3551
3552 port@2 {
3553 reg = <2>;
3554
3555 usb_dp_qmpphy_dp_in: endpoint {
3556 };
3557 };
3558 };
3559 };
3560
3561 usb_2: usb@8cf8800 {
3562 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3563 reg = <0 0x08cf8800 0 0x400>;
3564 status = "disabled";
3565 #address-cells = <2>;
3566 #size-cells = <2>;
3567 ranges;
3568 dma-ranges;
3569
3570 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3571 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3572 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3573 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3574 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
3575 clock-names = "cfg_noc",
3576 "core",
3577 "iface",
3578 "sleep",
3579 "mock_utmi";
3580
3581 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3582 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3583 assigned-clock-rates = <19200000>, <200000000>;
3584
3585 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
3586 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
3587 <&pdc 13 IRQ_TYPE_EDGE_BOTH>;
3588 interrupt-names = "hs_phy_irq",
3589 "dp_hs_phy_irq",
3590 "dm_hs_phy_irq";
3591
3592 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
3593 required-opps = <&rpmhpd_opp_nom>;
3594
3595 resets = <&gcc GCC_USB30_SEC_BCR>;
3596
3597 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
3598 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
3599 interconnect-names = "usb-ddr", "apps-usb";
3600
3601 usb_2_dwc3: usb@8c00000 {
3602 compatible = "snps,dwc3";
3603 reg = <0 0x08c00000 0 0xe000>;
3604 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
3605 iommus = <&apps_smmu 0xa0 0x0>;
3606 snps,dis_u2_susphy_quirk;
3607 snps,dis_enblslpm_quirk;
3608 phys = <&usb_2_hsphy>;
3609 phy-names = "usb2-phy";
3610 maximum-speed = "high-speed";
3611 usb-role-switch;
3612
3613 port {
3614 usb2_role_switch: endpoint {
3615 remote-endpoint = <&eud_ep>;
3616 };
3617 };
3618 };
3619 };
3620
3621 qspi: spi@88dc000 {
3622 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
3623 reg = <0 0x088dc000 0 0x1000>;
3624 iommus = <&apps_smmu 0x20 0x0>;
3625 #address-cells = <1>;
3626 #size-cells = <0>;
3627 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3628 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3629 <&gcc GCC_QSPI_CORE_CLK>;
3630 clock-names = "iface", "core";
3631 interconnects = <&gem_noc MASTER_APPSS_PROC 0
3632 &cnoc2 SLAVE_QSPI_0 0>;
3633 interconnect-names = "qspi-config";
3634 power-domains = <&rpmhpd SC7280_CX>;
3635 operating-points-v2 = <&qspi_opp_table>;
3636 status = "disabled";
3637 };
3638
3639 remoteproc_adsp: remoteproc@3700000 {
3640 compatible = "qcom,sc7280-adsp-pas";
3641 reg = <0 0x03700000 0 0x100>;
3642
3643 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3644 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3645 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3646 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3647 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3648 <&adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3649 interrupt-names = "wdog", "fatal", "ready", "handover",
3650 "stop-ack", "shutdown-ack";
3651
3652 clocks = <&rpmhcc RPMH_CXO_CLK>;
3653 clock-names = "xo";
3654
3655 power-domains = <&rpmhpd SC7280_LCX>,
3656 <&rpmhpd SC7280_LMX>;
3657 power-domain-names = "lcx", "lmx";
3658
3659 memory-region = <&adsp_mem>;
3660
3661 qcom,qmp = <&aoss_qmp>;
3662
3663 qcom,smem-states = <&adsp_smp2p_out 0>;
3664 qcom,smem-state-names = "stop";
3665
3666 status = "disabled";
3667
3668 glink-edge {
3669 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3670 IPCC_MPROC_SIGNAL_GLINK_QMP
3671 IRQ_TYPE_EDGE_RISING>;
3672
3673 mboxes = <&ipcc IPCC_CLIENT_LPASS
3674 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3675
3676 label = "lpass";
3677 qcom,remote-pid = <2>;
3678
3679 fastrpc {
3680 compatible = "qcom,fastrpc";
3681 qcom,glink-channels = "fastrpcglink-apps-dsp";
3682 label = "adsp";
3683 qcom,non-secure-domain;
3684 #address-cells = <1>;
3685 #size-cells = <0>;
3686
3687 compute-cb@3 {
3688 compatible = "qcom,fastrpc-compute-cb";
3689 reg = <3>;
3690 iommus = <&apps_smmu 0x1803 0x0>;
3691 };
3692
3693 compute-cb@4 {
3694 compatible = "qcom,fastrpc-compute-cb";
3695 reg = <4>;
3696 iommus = <&apps_smmu 0x1804 0x0>;
3697 };
3698
3699 compute-cb@5 {
3700 compatible = "qcom,fastrpc-compute-cb";
3701 reg = <5>;
3702 iommus = <&apps_smmu 0x1805 0x0>;
3703 };
3704 };
3705 };
3706 };
3707
3708 remoteproc_wpss: remoteproc@8a00000 {
3709 compatible = "qcom,sc7280-wpss-pas";
3710 reg = <0 0x08a00000 0 0x10000>;
3711
3712 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
3713 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3714 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3715 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3716 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3717 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3718 interrupt-names = "wdog", "fatal", "ready", "handover",
3719 "stop-ack", "shutdown-ack";
3720
3721 clocks = <&rpmhcc RPMH_CXO_CLK>;
3722 clock-names = "xo";
3723
3724 power-domains = <&rpmhpd SC7280_CX>,
3725 <&rpmhpd SC7280_MX>;
3726 power-domain-names = "cx", "mx";
3727
3728 memory-region = <&wpss_mem>;
3729
3730 qcom,qmp = <&aoss_qmp>;
3731
3732 qcom,smem-states = <&wpss_smp2p_out 0>;
3733 qcom,smem-state-names = "stop";
3734
3735
3736 status = "disabled";
3737
3738 glink-edge {
3739 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
3740 IPCC_MPROC_SIGNAL_GLINK_QMP
3741 IRQ_TYPE_EDGE_RISING>;
3742 mboxes = <&ipcc IPCC_CLIENT_WPSS
3743 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3744
3745 label = "wpss";
3746 qcom,remote-pid = <13>;
3747 };
3748 };
3749
3750 pmu@9091000 {
3751 compatible = "qcom,sc7280-llcc-bwmon";
3752 reg = <0 0x09091000 0 0x1000>;
3753
3754 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3755
3756 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
3757
3758 operating-points-v2 = <&llcc_bwmon_opp_table>;
3759
3760 llcc_bwmon_opp_table: opp-table {
3761 compatible = "operating-points-v2";
3762
3763 opp-0 {
3764 opp-peak-kBps = <800000>;
3765 };
3766 opp-1 {
3767 opp-peak-kBps = <1804000>;
3768 };
3769 opp-2 {
3770 opp-peak-kBps = <2188000>;
3771 };
3772 opp-3 {
3773 opp-peak-kBps = <3072000>;
3774 };
3775 opp-4 {
3776 opp-peak-kBps = <4068000>;
3777 };
3778 opp-5 {
3779 opp-peak-kBps = <6220000>;
3780 };
3781 opp-6 {
3782 opp-peak-kBps = <6832000>;
3783 };
3784 opp-7 {
3785 opp-peak-kBps = <8532000>;
3786 };
3787 };
3788 };
3789
3790 pmu@90b6400 {
3791 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon";
3792 reg = <0 0x090b6400 0 0x600>;
3793
3794 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
3795
3796 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
3797 operating-points-v2 = <&cpu_bwmon_opp_table>;
3798
3799 cpu_bwmon_opp_table: opp-table {
3800 compatible = "operating-points-v2";
3801
3802 opp-0 {
3803 opp-peak-kBps = <2400000>;
3804 };
3805 opp-1 {
3806 opp-peak-kBps = <4800000>;
3807 };
3808 opp-2 {
3809 opp-peak-kBps = <7456000>;
3810 };
3811 opp-3 {
3812 opp-peak-kBps = <9600000>;
3813 };
3814 opp-4 {
3815 opp-peak-kBps = <12896000>;
3816 };
3817 opp-5 {
3818 opp-peak-kBps = <14928000>;
3819 };
3820 opp-6 {
3821 opp-peak-kBps = <17056000>;
3822 };
3823 };
3824 };
3825
3826 dc_noc: interconnect@90e0000 {
3827 reg = <0 0x090e0000 0 0x5080>;
3828 compatible = "qcom,sc7280-dc-noc";
3829 #interconnect-cells = <2>;
3830 qcom,bcm-voters = <&apps_bcm_voter>;
3831 };
3832
3833 gem_noc: interconnect@9100000 {
3834 reg = <0 0x09100000 0 0xe2200>;
3835 compatible = "qcom,sc7280-gem-noc";
3836 #interconnect-cells = <2>;
3837 qcom,bcm-voters = <&apps_bcm_voter>;
3838 };
3839
3840 system-cache-controller@9200000 {
3841 compatible = "qcom,sc7280-llcc";
3842 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
3843 <0 0x09600000 0 0x58000>;
3844 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base";
3845 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3846 };
3847
3848 eud: eud@88e0000 {
3849 compatible = "qcom,sc7280-eud", "qcom,eud";
3850 reg = <0 0x88e0000 0 0x2000>,
3851 <0 0x88e2000 0 0x1000>;
3852 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>;
3853
3854 status = "disabled";
3855
3856 ports {
3857 #address-cells = <1>;
3858 #size-cells = <0>;
3859
3860 port@0 {
3861 reg = <0>;
3862 eud_ep: endpoint {
3863 remote-endpoint = <&usb2_role_switch>;
3864 };
3865 };
3866 };
3867 };
3868
3869 nsp_noc: interconnect@a0c0000 {
3870 reg = <0 0x0a0c0000 0 0x10000>;
3871 compatible = "qcom,sc7280-nsp-noc";
3872 #interconnect-cells = <2>;
3873 qcom,bcm-voters = <&apps_bcm_voter>;
3874 };
3875
3876 remoteproc_cdsp: remoteproc@a300000 {
3877 compatible = "qcom,sc7280-cdsp-pas";
3878 reg = <0 0x0a300000 0 0x10000>;
3879
3880 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3881 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3882 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3883 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3884 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3885 <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3886 interrupt-names = "wdog", "fatal", "ready", "handover",
3887 "stop-ack", "shutdown-ack";
3888
3889 clocks = <&rpmhcc RPMH_CXO_CLK>;
3890 clock-names = "xo";
3891
3892 power-domains = <&rpmhpd SC7280_CX>,
3893 <&rpmhpd SC7280_MX>;
3894 power-domain-names = "cx", "mx";
3895
3896 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
3897
3898 memory-region = <&cdsp_mem>;
3899
3900 qcom,qmp = <&aoss_qmp>;
3901
3902 qcom,smem-states = <&cdsp_smp2p_out 0>;
3903 qcom,smem-state-names = "stop";
3904
3905 status = "disabled";
3906
3907 glink-edge {
3908 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3909 IPCC_MPROC_SIGNAL_GLINK_QMP
3910 IRQ_TYPE_EDGE_RISING>;
3911 mboxes = <&ipcc IPCC_CLIENT_CDSP
3912 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3913
3914 label = "cdsp";
3915 qcom,remote-pid = <5>;
3916
3917 fastrpc {
3918 compatible = "qcom,fastrpc";
3919 qcom,glink-channels = "fastrpcglink-apps-dsp";
3920 label = "cdsp";
3921 qcom,non-secure-domain;
3922 #address-cells = <1>;
3923 #size-cells = <0>;
3924
3925 compute-cb@1 {
3926 compatible = "qcom,fastrpc-compute-cb";
3927 reg = <1>;
3928 iommus = <&apps_smmu 0x11a1 0x0420>,
3929 <&apps_smmu 0x1181 0x0420>;
3930 };
3931
3932 compute-cb@2 {
3933 compatible = "qcom,fastrpc-compute-cb";
3934 reg = <2>;
3935 iommus = <&apps_smmu 0x11a2 0x0420>,
3936 <&apps_smmu 0x1182 0x0420>;
3937 };
3938
3939 compute-cb@3 {
3940 compatible = "qcom,fastrpc-compute-cb";
3941 reg = <3>;
3942 iommus = <&apps_smmu 0x11a3 0x0420>,
3943 <&apps_smmu 0x1183 0x0420>;
3944 };
3945
3946 compute-cb@4 {
3947 compatible = "qcom,fastrpc-compute-cb";
3948 reg = <4>;
3949 iommus = <&apps_smmu 0x11a4 0x0420>,
3950 <&apps_smmu 0x1184 0x0420>;
3951 };
3952
3953 compute-cb@5 {
3954 compatible = "qcom,fastrpc-compute-cb";
3955 reg = <5>;
3956 iommus = <&apps_smmu 0x11a5 0x0420>,
3957 <&apps_smmu 0x1185 0x0420>;
3958 };
3959
3960 compute-cb@6 {
3961 compatible = "qcom,fastrpc-compute-cb";
3962 reg = <6>;
3963 iommus = <&apps_smmu 0x11a6 0x0420>,
3964 <&apps_smmu 0x1186 0x0420>;
3965 };
3966
3967 compute-cb@7 {
3968 compatible = "qcom,fastrpc-compute-cb";
3969 reg = <7>;
3970 iommus = <&apps_smmu 0x11a7 0x0420>,
3971 <&apps_smmu 0x1187 0x0420>;
3972 };
3973
3974 compute-cb@8 {
3975 compatible = "qcom,fastrpc-compute-cb";
3976 reg = <8>;
3977 iommus = <&apps_smmu 0x11a8 0x0420>,
3978 <&apps_smmu 0x1188 0x0420>;
3979 };
3980
3981 /* note: secure cb9 in downstream */
3982
3983 compute-cb@11 {
3984 compatible = "qcom,fastrpc-compute-cb";
3985 reg = <11>;
3986 iommus = <&apps_smmu 0x11ab 0x0420>,
3987 <&apps_smmu 0x118b 0x0420>;
3988 };
3989
3990 compute-cb@12 {
3991 compatible = "qcom,fastrpc-compute-cb";
3992 reg = <12>;
3993 iommus = <&apps_smmu 0x11ac 0x0420>,
3994 <&apps_smmu 0x118c 0x0420>;
3995 };
3996
3997 compute-cb@13 {
3998 compatible = "qcom,fastrpc-compute-cb";
3999 reg = <13>;
4000 iommus = <&apps_smmu 0x11ad 0x0420>,
4001 <&apps_smmu 0x118d 0x0420>;
4002 };
4003
4004 compute-cb@14 {
4005 compatible = "qcom,fastrpc-compute-cb";
4006 reg = <14>;
4007 iommus = <&apps_smmu 0x11ae 0x0420>,
4008 <&apps_smmu 0x118e 0x0420>;
4009 };
4010 };
4011 };
4012 };
4013
4014 usb_1: usb@a6f8800 {
4015 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
4016 reg = <0 0x0a6f8800 0 0x400>;
4017 status = "disabled";
4018 #address-cells = <2>;
4019 #size-cells = <2>;
4020 ranges;
4021 dma-ranges;
4022
4023 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4024 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4025 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4026 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4027 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
4028 clock-names = "cfg_noc",
4029 "core",
4030 "iface",
4031 "sleep",
4032 "mock_utmi";
4033
4034 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4035 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4036 assigned-clock-rates = <19200000>, <200000000>;
4037
4038 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4039 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
4040 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4041 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4042 interrupt-names = "hs_phy_irq",
4043 "dp_hs_phy_irq",
4044 "dm_hs_phy_irq",
4045 "ss_phy_irq";
4046
4047 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
4048 required-opps = <&rpmhpd_opp_nom>;
4049
4050 resets = <&gcc GCC_USB30_PRIM_BCR>;
4051
4052 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
4053 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>;
4054 interconnect-names = "usb-ddr", "apps-usb";
4055
4056 wakeup-source;
4057
4058 usb_1_dwc3: usb@a600000 {
4059 compatible = "snps,dwc3";
4060 reg = <0 0x0a600000 0 0xe000>;
4061 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4062 iommus = <&apps_smmu 0xe0 0x0>;
4063 snps,dis_u2_susphy_quirk;
4064 snps,dis_enblslpm_quirk;
4065 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4066 phy-names = "usb2-phy", "usb3-phy";
4067 maximum-speed = "super-speed";
4068 };
4069 };
4070
4071 venus: video-codec@aa00000 {
4072 compatible = "qcom,sc7280-venus";
4073 reg = <0 0x0aa00000 0 0xd0600>;
4074 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4075
4076 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>,
4077 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>,
4078 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
4079 <&videocc VIDEO_CC_MVS0_CORE_CLK>,
4080 <&videocc VIDEO_CC_MVS0_AXI_CLK>;
4081 clock-names = "core", "bus", "iface",
4082 "vcodec_core", "vcodec_bus";
4083
4084 power-domains = <&videocc MVSC_GDSC>,
4085 <&videocc MVS0_GDSC>,
4086 <&rpmhpd SC7280_CX>;
4087 power-domain-names = "venus", "vcodec0", "cx";
4088 operating-points-v2 = <&venus_opp_table>;
4089
4090 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>,
4091 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
4092 interconnect-names = "cpu-cfg", "video-mem";
4093
4094 iommus = <&apps_smmu 0x2180 0x20>,
4095 <&apps_smmu 0x2184 0x20>;
4096 memory-region = <&video_mem>;
4097
4098 video-decoder {
4099 compatible = "venus-decoder";
4100 };
4101
4102 video-encoder {
4103 compatible = "venus-encoder";
4104 };
4105
4106 video-firmware {
4107 iommus = <&apps_smmu 0x21a2 0x0>;
4108 };
4109
4110 venus_opp_table: opp-table {
4111 compatible = "operating-points-v2";
4112
4113 opp-133330000 {
4114 opp-hz = /bits/ 64 <133330000>;
4115 required-opps = <&rpmhpd_opp_low_svs>;
4116 };
4117
4118 opp-240000000 {
4119 opp-hz = /bits/ 64 <240000000>;
4120 required-opps = <&rpmhpd_opp_svs>;
4121 };
4122
4123 opp-335000000 {
4124 opp-hz = /bits/ 64 <335000000>;
4125 required-opps = <&rpmhpd_opp_svs_l1>;
4126 };
4127
4128 opp-424000000 {
4129 opp-hz = /bits/ 64 <424000000>;
4130 required-opps = <&rpmhpd_opp_nom>;
4131 };
4132
4133 opp-460000048 {
4134 opp-hz = /bits/ 64 <460000048>;
4135 required-opps = <&rpmhpd_opp_turbo>;
4136 };
4137 };
4138 };
4139
4140 videocc: clock-controller@aaf0000 {
4141 compatible = "qcom,sc7280-videocc";
4142 reg = <0 0x0aaf0000 0 0x10000>;
4143 clocks = <&rpmhcc RPMH_CXO_CLK>,
4144 <&rpmhcc RPMH_CXO_CLK_A>;
4145 clock-names = "bi_tcxo", "bi_tcxo_ao";
4146 #clock-cells = <1>;
4147 #reset-cells = <1>;
4148 #power-domain-cells = <1>;
4149 };
4150
4151 cci0: cci@ac4a000 {
4152 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";
4153 reg = <0 0x0ac4a000 0 0x1000>;
4154 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4155 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
4156
4157 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4158 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4159 <&camcc CAM_CC_CPAS_AHB_CLK>,
4160 <&camcc CAM_CC_CCI_0_CLK>,
4161 <&camcc CAM_CC_CCI_0_CLK_SRC>;
4162 clock-names = "camnoc_axi",
4163 "slow_ahb_src",
4164 "cpas_ahb",
4165 "cci",
4166 "cci_src";
4167 pinctrl-0 = <&cci0_default &cci1_default>;
4168 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4169 pinctrl-names = "default", "sleep";
4170
4171 #address-cells = <1>;
4172 #size-cells = <0>;
4173
4174 status = "disabled";
4175
4176 cci0_i2c0: i2c-bus@0 {
4177 reg = <0>;
4178 clock-frequency = <1000000>;
4179 #address-cells = <1>;
4180 #size-cells = <0>;
4181 };
4182
4183 cci0_i2c1: i2c-bus@1 {
4184 reg = <1>;
4185 clock-frequency = <1000000>;
4186 #address-cells = <1>;
4187 #size-cells = <0>;
4188 };
4189 };
4190
4191 cci1: cci@ac4b000 {
4192 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";
4193 reg = <0 0x0ac4b000 0 0x1000>;
4194 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
4195 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
4196
4197 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4198 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4199 <&camcc CAM_CC_CPAS_AHB_CLK>,
4200 <&camcc CAM_CC_CCI_1_CLK>,
4201 <&camcc CAM_CC_CCI_1_CLK_SRC>;
4202 clock-names = "camnoc_axi",
4203 "slow_ahb_src",
4204 "cpas_ahb",
4205 "cci",
4206 "cci_src";
4207 pinctrl-0 = <&cci2_default &cci3_default>;
4208 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
4209 pinctrl-names = "default", "sleep";
4210
4211 #address-cells = <1>;
4212 #size-cells = <0>;
4213
4214 status = "disabled";
4215
4216 cci1_i2c0: i2c-bus@0 {
4217 reg = <0>;
4218 clock-frequency = <1000000>;
4219 #address-cells = <1>;
4220 #size-cells = <0>;
4221 };
4222
4223 cci1_i2c1: i2c-bus@1 {
4224 reg = <1>;
4225 clock-frequency = <1000000>;
4226 #address-cells = <1>;
4227 #size-cells = <0>;
4228 };
4229 };
4230
4231 camcc: clock-controller@ad00000 {
4232 compatible = "qcom,sc7280-camcc";
4233 reg = <0 0x0ad00000 0 0x10000>;
4234 clocks = <&rpmhcc RPMH_CXO_CLK>,
4235 <&rpmhcc RPMH_CXO_CLK_A>,
4236 <&sleep_clk>;
4237 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4238 #clock-cells = <1>;
4239 #reset-cells = <1>;
4240 #power-domain-cells = <1>;
4241 };
4242
4243 dispcc: clock-controller@af00000 {
4244 compatible = "qcom,sc7280-dispcc";
4245 reg = <0 0x0af00000 0 0x20000>;
4246 clocks = <&rpmhcc RPMH_CXO_CLK>,
4247 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4248 <&mdss_dsi_phy 0>,
4249 <&mdss_dsi_phy 1>,
4250 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4251 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4252 <&mdss_edp_phy 0>,
4253 <&mdss_edp_phy 1>;
4254 clock-names = "bi_tcxo",
4255 "gcc_disp_gpll0_clk",
4256 "dsi0_phy_pll_out_byteclk",
4257 "dsi0_phy_pll_out_dsiclk",
4258 "dp_phy_pll_link_clk",
4259 "dp_phy_pll_vco_div_clk",
4260 "edp_phy_pll_link_clk",
4261 "edp_phy_pll_vco_div_clk";
4262 #clock-cells = <1>;
4263 #reset-cells = <1>;
4264 #power-domain-cells = <1>;
4265 };
4266
4267 mdss: display-subsystem@ae00000 {
4268 compatible = "qcom,sc7280-mdss";
4269 reg = <0 0x0ae00000 0 0x1000>;
4270 reg-names = "mdss";
4271
4272 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
4273
4274 clocks = <&gcc GCC_DISP_AHB_CLK>,
4275 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4276 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4277 clock-names = "iface",
4278 "ahb",
4279 "core";
4280
4281 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4282 interrupt-controller;
4283 #interrupt-cells = <1>;
4284
4285 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
4286 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4287 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
4288 &cnoc2 SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>;
4289 interconnect-names = "mdp0-mem",
4290 "cpu-cfg";
4291
4292 iommus = <&apps_smmu 0x900 0x402>;
4293
4294 #address-cells = <2>;
4295 #size-cells = <2>;
4296 ranges;
4297
4298 status = "disabled";
4299
4300 mdss_mdp: display-controller@ae01000 {
4301 compatible = "qcom,sc7280-dpu";
4302 reg = <0 0x0ae01000 0 0x8f030>,
4303 <0 0x0aeb0000 0 0x2008>;
4304 reg-names = "mdp", "vbif";
4305
4306 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
4307 <&gcc GCC_DISP_SF_AXI_CLK>,
4308 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4309 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
4310 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4311 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4312 clock-names = "bus",
4313 "nrt_bus",
4314 "iface",
4315 "lut",
4316 "core",
4317 "vsync";
4318 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
4319 <&dispcc DISP_CC_MDSS_AHB_CLK>;
4320 assigned-clock-rates = <19200000>,
4321 <19200000>;
4322 operating-points-v2 = <&mdp_opp_table>;
4323 power-domains = <&rpmhpd SC7280_CX>;
4324
4325 interrupt-parent = <&mdss>;
4326 interrupts = <0>;
4327
4328 ports {
4329 #address-cells = <1>;
4330 #size-cells = <0>;
4331
4332 port@0 {
4333 reg = <0>;
4334 dpu_intf1_out: endpoint {
4335 remote-endpoint = <&mdss_dsi0_in>;
4336 };
4337 };
4338
4339 port@1 {
4340 reg = <1>;
4341 dpu_intf5_out: endpoint {
4342 remote-endpoint = <&edp_in>;
4343 };
4344 };
4345
4346 port@2 {
4347 reg = <2>;
4348 dpu_intf0_out: endpoint {
4349 remote-endpoint = <&dp_in>;
4350 };
4351 };
4352 };
4353
4354 mdp_opp_table: opp-table {
4355 compatible = "operating-points-v2";
4356
4357 opp-200000000 {
4358 opp-hz = /bits/ 64 <200000000>;
4359 required-opps = <&rpmhpd_opp_low_svs>;
4360 };
4361
4362 opp-300000000 {
4363 opp-hz = /bits/ 64 <300000000>;
4364 required-opps = <&rpmhpd_opp_svs>;
4365 };
4366
4367 opp-380000000 {
4368 opp-hz = /bits/ 64 <380000000>;
4369 required-opps = <&rpmhpd_opp_svs_l1>;
4370 };
4371
4372 opp-506666667 {
4373 opp-hz = /bits/ 64 <506666667>;
4374 required-opps = <&rpmhpd_opp_nom>;
4375 };
4376 };
4377 };
4378
4379 mdss_dsi: dsi@ae94000 {
4380 compatible = "qcom,sc7280-dsi-ctrl",
4381 "qcom,mdss-dsi-ctrl";
4382 reg = <0 0x0ae94000 0 0x400>;
4383 reg-names = "dsi_ctrl";
4384
4385 interrupt-parent = <&mdss>;
4386 interrupts = <4>;
4387
4388 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4389 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4390 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4391 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4392 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4393 <&gcc GCC_DISP_HF_AXI_CLK>;
4394 clock-names = "byte",
4395 "byte_intf",
4396 "pixel",
4397 "core",
4398 "iface",
4399 "bus";
4400
4401 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4402 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
4403
4404 operating-points-v2 = <&dsi_opp_table>;
4405 power-domains = <&rpmhpd SC7280_CX>;
4406
4407 phys = <&mdss_dsi_phy>;
4408
4409 #address-cells = <1>;
4410 #size-cells = <0>;
4411
4412 status = "disabled";
4413
4414 ports {
4415 #address-cells = <1>;
4416 #size-cells = <0>;
4417
4418 port@0 {
4419 reg = <0>;
4420 mdss_dsi0_in: endpoint {
4421 remote-endpoint = <&dpu_intf1_out>;
4422 };
4423 };
4424
4425 port@1 {
4426 reg = <1>;
4427 mdss_dsi0_out: endpoint {
4428 };
4429 };
4430 };
4431
4432 dsi_opp_table: opp-table {
4433 compatible = "operating-points-v2";
4434
4435 opp-187500000 {
4436 opp-hz = /bits/ 64 <187500000>;
4437 required-opps = <&rpmhpd_opp_low_svs>;
4438 };
4439
4440 opp-300000000 {
4441 opp-hz = /bits/ 64 <300000000>;
4442 required-opps = <&rpmhpd_opp_svs>;
4443 };
4444
4445 opp-358000000 {
4446 opp-hz = /bits/ 64 <358000000>;
4447 required-opps = <&rpmhpd_opp_svs_l1>;
4448 };
4449 };
4450 };
4451
4452 mdss_dsi_phy: phy@ae94400 {
4453 compatible = "qcom,sc7280-dsi-phy-7nm";
4454 reg = <0 0x0ae94400 0 0x200>,
4455 <0 0x0ae94600 0 0x280>,
4456 <0 0x0ae94900 0 0x280>;
4457 reg-names = "dsi_phy",
4458 "dsi_phy_lane",
4459 "dsi_pll";
4460
4461 #clock-cells = <1>;
4462 #phy-cells = <0>;
4463
4464 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4465 <&rpmhcc RPMH_CXO_CLK>;
4466 clock-names = "iface", "ref";
4467
4468 status = "disabled";
4469 };
4470
4471 mdss_edp: edp@aea0000 {
4472 compatible = "qcom,sc7280-edp";
4473 pinctrl-names = "default";
4474 pinctrl-0 = <&edp_hot_plug_det>;
4475
4476 reg = <0 0x0aea0000 0 0x200>,
4477 <0 0x0aea0200 0 0x200>,
4478 <0 0x0aea0400 0 0xc00>,
4479 <0 0x0aea1000 0 0x400>;
4480
4481 interrupt-parent = <&mdss>;
4482 interrupts = <14>;
4483
4484 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4485 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
4486 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
4487 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
4488 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
4489 clock-names = "core_iface",
4490 "core_aux",
4491 "ctrl_link",
4492 "ctrl_link_iface",
4493 "stream_pixel";
4494 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
4495 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
4496 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4497
4498 phys = <&mdss_edp_phy>;
4499 phy-names = "dp";
4500
4501 operating-points-v2 = <&edp_opp_table>;
4502 power-domains = <&rpmhpd SC7280_CX>;
4503
4504 status = "disabled";
4505
4506 ports {
4507 #address-cells = <1>;
4508 #size-cells = <0>;
4509
4510 port@0 {
4511 reg = <0>;
4512 edp_in: endpoint {
4513 remote-endpoint = <&dpu_intf5_out>;
4514 };
4515 };
4516
4517 port@1 {
4518 reg = <1>;
4519 mdss_edp_out: endpoint { };
4520 };
4521 };
4522
4523 edp_opp_table: opp-table {
4524 compatible = "operating-points-v2";
4525
4526 opp-160000000 {
4527 opp-hz = /bits/ 64 <160000000>;
4528 required-opps = <&rpmhpd_opp_low_svs>;
4529 };
4530
4531 opp-270000000 {
4532 opp-hz = /bits/ 64 <270000000>;
4533 required-opps = <&rpmhpd_opp_svs>;
4534 };
4535
4536 opp-540000000 {
4537 opp-hz = /bits/ 64 <540000000>;
4538 required-opps = <&rpmhpd_opp_nom>;
4539 };
4540
4541 opp-810000000 {
4542 opp-hz = /bits/ 64 <810000000>;
4543 required-opps = <&rpmhpd_opp_nom>;
4544 };
4545 };
4546 };
4547
4548 mdss_edp_phy: phy@aec2a00 {
4549 compatible = "qcom,sc7280-edp-phy";
4550
4551 reg = <0 0x0aec2a00 0 0x19c>,
4552 <0 0x0aec2200 0 0xa0>,
4553 <0 0x0aec2600 0 0xa0>,
4554 <0 0x0aec2000 0 0x1c0>;
4555
4556 clocks = <&rpmhcc RPMH_CXO_CLK>,
4557 <&gcc GCC_EDP_CLKREF_EN>;
4558 clock-names = "aux",
4559 "cfg_ahb";
4560
4561 #clock-cells = <1>;
4562 #phy-cells = <0>;
4563
4564 status = "disabled";
4565 };
4566
4567 mdss_dp: displayport-controller@ae90000 {
4568 compatible = "qcom,sc7280-dp";
4569
4570 reg = <0 0x0ae90000 0 0x200>,
4571 <0 0x0ae90200 0 0x200>,
4572 <0 0x0ae90400 0 0xc00>,
4573 <0 0x0ae91000 0 0x400>,
4574 <0 0x0ae91400 0 0x400>;
4575
4576 interrupt-parent = <&mdss>;
4577 interrupts = <12>;
4578
4579 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4580 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
4581 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
4582 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
4583 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
4584 clock-names = "core_iface",
4585 "core_aux",
4586 "ctrl_link",
4587 "ctrl_link_iface",
4588 "stream_pixel";
4589 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4590 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
4591 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4592 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4593 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
4594 phy-names = "dp";
4595
4596 operating-points-v2 = <&dp_opp_table>;
4597 power-domains = <&rpmhpd SC7280_CX>;
4598
4599 #sound-dai-cells = <0>;
4600
4601 status = "disabled";
4602
4603 ports {
4604 #address-cells = <1>;
4605 #size-cells = <0>;
4606
4607 port@0 {
4608 reg = <0>;
4609 dp_in: endpoint {
4610 remote-endpoint = <&dpu_intf0_out>;
4611 };
4612 };
4613
4614 port@1 {
4615 reg = <1>;
4616 mdss_dp_out: endpoint { };
4617 };
4618 };
4619
4620 dp_opp_table: opp-table {
4621 compatible = "operating-points-v2";
4622
4623 opp-160000000 {
4624 opp-hz = /bits/ 64 <160000000>;
4625 required-opps = <&rpmhpd_opp_low_svs>;
4626 };
4627
4628 opp-270000000 {
4629 opp-hz = /bits/ 64 <270000000>;
4630 required-opps = <&rpmhpd_opp_svs>;
4631 };
4632
4633 opp-540000000 {
4634 opp-hz = /bits/ 64 <540000000>;
4635 required-opps = <&rpmhpd_opp_svs_l1>;
4636 };
4637
4638 opp-810000000 {
4639 opp-hz = /bits/ 64 <810000000>;
4640 required-opps = <&rpmhpd_opp_nom>;
4641 };
4642 };
4643 };
4644 };
4645
4646 pdc: interrupt-controller@b220000 {
4647 compatible = "qcom,sc7280-pdc", "qcom,pdc";
4648 reg = <0 0x0b220000 0 0x30000>;
4649 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
4650 <55 306 4>, <59 312 3>, <62 374 2>,
4651 <64 434 2>, <66 438 3>, <69 86 1>,
4652 <70 520 54>, <124 609 31>, <155 63 1>,
4653 <156 716 12>;
4654 #interrupt-cells = <2>;
4655 interrupt-parent = <&intc>;
4656 interrupt-controller;
4657 };
4658
4659 pdc_reset: reset-controller@b5e0000 {
4660 compatible = "qcom,sc7280-pdc-global";
4661 reg = <0 0x0b5e0000 0 0x20000>;
4662 #reset-cells = <1>;
4663 status = "reserved"; /* Owned by firmware */
4664 };
4665
4666 tsens0: thermal-sensor@c263000 {
4667 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4668 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4669 <0 0x0c222000 0 0x1ff>; /* SROT */
4670 #qcom,sensors = <15>;
4671 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4672 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4673 interrupt-names = "uplow","critical";
4674 #thermal-sensor-cells = <1>;
4675 };
4676
4677 tsens1: thermal-sensor@c265000 {
4678 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4679 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4680 <0 0x0c223000 0 0x1ff>; /* SROT */
4681 #qcom,sensors = <12>;
4682 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4683 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4684 interrupt-names = "uplow","critical";
4685 #thermal-sensor-cells = <1>;
4686 };
4687
4688 aoss_reset: reset-controller@c2a0000 {
4689 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
4690 reg = <0 0x0c2a0000 0 0x31000>;
4691 #reset-cells = <1>;
4692 };
4693
4694 aoss_qmp: power-management@c300000 {
4695 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp";
4696 reg = <0 0x0c300000 0 0x400>;
4697 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
4698 IPCC_MPROC_SIGNAL_GLINK_QMP
4699 IRQ_TYPE_EDGE_RISING>;
4700 mboxes = <&ipcc IPCC_CLIENT_AOP
4701 IPCC_MPROC_SIGNAL_GLINK_QMP>;
4702
4703 #clock-cells = <0>;
4704 };
4705
4706 sram@c3f0000 {
4707 compatible = "qcom,rpmh-stats";
4708 reg = <0 0x0c3f0000 0 0x400>;
4709 };
4710
4711 spmi_bus: spmi@c440000 {
4712 compatible = "qcom,spmi-pmic-arb";
4713 reg = <0 0x0c440000 0 0x1100>,
4714 <0 0x0c600000 0 0x2000000>,
4715 <0 0x0e600000 0 0x100000>,
4716 <0 0x0e700000 0 0xa0000>,
4717 <0 0x0c40a000 0 0x26000>;
4718 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4719 interrupt-names = "periph_irq";
4720 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4721 qcom,ee = <0>;
4722 qcom,channel = <0>;
4723 #address-cells = <2>;
4724 #size-cells = <0>;
4725 interrupt-controller;
4726 #interrupt-cells = <4>;
4727 };
4728
4729 tlmm: pinctrl@f100000 {
4730 compatible = "qcom,sc7280-pinctrl";
4731 reg = <0 0x0f100000 0 0x300000>;
4732 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
4733 gpio-controller;
4734 #gpio-cells = <2>;
4735 interrupt-controller;
4736 #interrupt-cells = <2>;
4737 gpio-ranges = <&tlmm 0 0 175>;
4738 wakeup-parent = <&pdc>;
4739
4740 cci0_default: cci0-default-state {
4741 pins = "gpio69", "gpio70";
4742 function = "cci_i2c";
4743 drive-strength = <2>;
4744 bias-pull-up;
4745 };
4746
4747 cci0_sleep: cci0-sleep-state {
4748 pins = "gpio69", "gpio70";
4749 function = "cci_i2c";
4750 drive-strength = <2>;
4751 bias-pull-down;
4752 };
4753
4754 cci1_default: cci1-default-state {
4755 pins = "gpio71", "gpio72";
4756 function = "cci_i2c";
4757 drive-strength = <2>;
4758 bias-pull-up;
4759 };
4760
4761 cci1_sleep: cci1-sleep-state {
4762 pins = "gpio71", "gpio72";
4763 function = "cci_i2c";
4764 drive-strength = <2>;
4765 bias-pull-down;
4766 };
4767
4768 cci2_default: cci2-default-state {
4769 pins = "gpio73", "gpio74";
4770 function = "cci_i2c";
4771 drive-strength = <2>;
4772 bias-pull-up;
4773 };
4774
4775 cci2_sleep: cci2-sleep-state {
4776 pins = "gpio73", "gpio74";
4777 function = "cci_i2c";
4778 drive-strength = <2>;
4779 bias-pull-down;
4780 };
4781
4782 cci3_default: cci3-default-state {
4783 pins = "gpio75", "gpio76";
4784 function = "cci_i2c";
4785 drive-strength = <2>;
4786 bias-pull-up;
4787 };
4788
4789 cci3_sleep: cci3-sleep-state {
4790 pins = "gpio75", "gpio76";
4791 function = "cci_i2c";
4792 drive-strength = <2>;
4793 bias-pull-down;
4794 };
4795
4796 dp_hot_plug_det: dp-hot-plug-det-state {
4797 pins = "gpio47";
4798 function = "dp_hot";
4799 };
4800
4801 edp_hot_plug_det: edp-hot-plug-det-state {
4802 pins = "gpio60";
4803 function = "edp_hot";
4804 };
4805
4806 mi2s0_data0: mi2s0-data0-state {
4807 pins = "gpio98";
4808 function = "mi2s0_data0";
4809 };
4810
4811 mi2s0_data1: mi2s0-data1-state {
4812 pins = "gpio99";
4813 function = "mi2s0_data1";
4814 };
4815
4816 mi2s0_mclk: mi2s0-mclk-state {
4817 pins = "gpio96";
4818 function = "pri_mi2s";
4819 };
4820
4821 mi2s0_sclk: mi2s0-sclk-state {
4822 pins = "gpio97";
4823 function = "mi2s0_sck";
4824 };
4825
4826 mi2s0_ws: mi2s0-ws-state {
4827 pins = "gpio100";
4828 function = "mi2s0_ws";
4829 };
4830
4831 mi2s1_data0: mi2s1-data0-state {
4832 pins = "gpio107";
4833 function = "mi2s1_data0";
4834 };
4835
4836 mi2s1_sclk: mi2s1-sclk-state {
4837 pins = "gpio106";
4838 function = "mi2s1_sck";
4839 };
4840
4841 mi2s1_ws: mi2s1-ws-state {
4842 pins = "gpio108";
4843 function = "mi2s1_ws";
4844 };
4845
4846 pcie1_clkreq_n: pcie1-clkreq-n-state {
4847 pins = "gpio79";
4848 function = "pcie1_clkreqn";
4849 };
4850
4851 qspi_clk: qspi-clk-state {
4852 pins = "gpio14";
4853 function = "qspi_clk";
4854 };
4855
4856 qspi_cs0: qspi-cs0-state {
4857 pins = "gpio15";
4858 function = "qspi_cs";
4859 };
4860
4861 qspi_cs1: qspi-cs1-state {
4862 pins = "gpio19";
4863 function = "qspi_cs";
4864 };
4865
4866 qspi_data0: qspi-data0-state {
4867 pins = "gpio12";
4868 function = "qspi_data";
4869 };
4870
4871 qspi_data1: qspi-data1-state {
4872 pins = "gpio13";
4873 function = "qspi_data";
4874 };
4875
4876 qspi_data23: qspi-data23-state {
4877 pins = "gpio16", "gpio17";
4878 function = "qspi_data";
4879 };
4880
4881 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
4882 pins = "gpio0", "gpio1";
4883 function = "qup00";
4884 };
4885
4886 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
4887 pins = "gpio4", "gpio5";
4888 function = "qup01";
4889 };
4890
4891 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
4892 pins = "gpio8", "gpio9";
4893 function = "qup02";
4894 };
4895
4896 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
4897 pins = "gpio12", "gpio13";
4898 function = "qup03";
4899 };
4900
4901 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
4902 pins = "gpio16", "gpio17";
4903 function = "qup04";
4904 };
4905
4906 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
4907 pins = "gpio20", "gpio21";
4908 function = "qup05";
4909 };
4910
4911 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
4912 pins = "gpio24", "gpio25";
4913 function = "qup06";
4914 };
4915
4916 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
4917 pins = "gpio28", "gpio29";
4918 function = "qup07";
4919 };
4920
4921 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
4922 pins = "gpio32", "gpio33";
4923 function = "qup10";
4924 };
4925
4926 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
4927 pins = "gpio36", "gpio37";
4928 function = "qup11";
4929 };
4930
4931 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
4932 pins = "gpio40", "gpio41";
4933 function = "qup12";
4934 };
4935
4936 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
4937 pins = "gpio44", "gpio45";
4938 function = "qup13";
4939 };
4940
4941 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
4942 pins = "gpio48", "gpio49";
4943 function = "qup14";
4944 };
4945
4946 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
4947 pins = "gpio52", "gpio53";
4948 function = "qup15";
4949 };
4950
4951 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
4952 pins = "gpio56", "gpio57";
4953 function = "qup16";
4954 };
4955
4956 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
4957 pins = "gpio60", "gpio61";
4958 function = "qup17";
4959 };
4960
4961 qup_spi0_data_clk: qup-spi0-data-clk-state {
4962 pins = "gpio0", "gpio1", "gpio2";
4963 function = "qup00";
4964 };
4965
4966 qup_spi0_cs: qup-spi0-cs-state {
4967 pins = "gpio3";
4968 function = "qup00";
4969 };
4970
4971 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
4972 pins = "gpio3";
4973 function = "gpio";
4974 };
4975
4976 qup_spi1_data_clk: qup-spi1-data-clk-state {
4977 pins = "gpio4", "gpio5", "gpio6";
4978 function = "qup01";
4979 };
4980
4981 qup_spi1_cs: qup-spi1-cs-state {
4982 pins = "gpio7";
4983 function = "qup01";
4984 };
4985
4986 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
4987 pins = "gpio7";
4988 function = "gpio";
4989 };
4990
4991 qup_spi2_data_clk: qup-spi2-data-clk-state {
4992 pins = "gpio8", "gpio9", "gpio10";
4993 function = "qup02";
4994 };
4995
4996 qup_spi2_cs: qup-spi2-cs-state {
4997 pins = "gpio11";
4998 function = "qup02";
4999 };
5000
5001 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5002 pins = "gpio11";
5003 function = "gpio";
5004 };
5005
5006 qup_spi3_data_clk: qup-spi3-data-clk-state {
5007 pins = "gpio12", "gpio13", "gpio14";
5008 function = "qup03";
5009 };
5010
5011 qup_spi3_cs: qup-spi3-cs-state {
5012 pins = "gpio15";
5013 function = "qup03";
5014 };
5015
5016 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5017 pins = "gpio15";
5018 function = "gpio";
5019 };
5020
5021 qup_spi4_data_clk: qup-spi4-data-clk-state {
5022 pins = "gpio16", "gpio17", "gpio18";
5023 function = "qup04";
5024 };
5025
5026 qup_spi4_cs: qup-spi4-cs-state {
5027 pins = "gpio19";
5028 function = "qup04";
5029 };
5030
5031 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5032 pins = "gpio19";
5033 function = "gpio";
5034 };
5035
5036 qup_spi5_data_clk: qup-spi5-data-clk-state {
5037 pins = "gpio20", "gpio21", "gpio22";
5038 function = "qup05";
5039 };
5040
5041 qup_spi5_cs: qup-spi5-cs-state {
5042 pins = "gpio23";
5043 function = "qup05";
5044 };
5045
5046 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5047 pins = "gpio23";
5048 function = "gpio";
5049 };
5050
5051 qup_spi6_data_clk: qup-spi6-data-clk-state {
5052 pins = "gpio24", "gpio25", "gpio26";
5053 function = "qup06";
5054 };
5055
5056 qup_spi6_cs: qup-spi6-cs-state {
5057 pins = "gpio27";
5058 function = "qup06";
5059 };
5060
5061 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5062 pins = "gpio27";
5063 function = "gpio";
5064 };
5065
5066 qup_spi7_data_clk: qup-spi7-data-clk-state {
5067 pins = "gpio28", "gpio29", "gpio30";
5068 function = "qup07";
5069 };
5070
5071 qup_spi7_cs: qup-spi7-cs-state {
5072 pins = "gpio31";
5073 function = "qup07";
5074 };
5075
5076 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5077 pins = "gpio31";
5078 function = "gpio";
5079 };
5080
5081 qup_spi8_data_clk: qup-spi8-data-clk-state {
5082 pins = "gpio32", "gpio33", "gpio34";
5083 function = "qup10";
5084 };
5085
5086 qup_spi8_cs: qup-spi8-cs-state {
5087 pins = "gpio35";
5088 function = "qup10";
5089 };
5090
5091 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5092 pins = "gpio35";
5093 function = "gpio";
5094 };
5095
5096 qup_spi9_data_clk: qup-spi9-data-clk-state {
5097 pins = "gpio36", "gpio37", "gpio38";
5098 function = "qup11";
5099 };
5100
5101 qup_spi9_cs: qup-spi9-cs-state {
5102 pins = "gpio39";
5103 function = "qup11";
5104 };
5105
5106 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5107 pins = "gpio39";
5108 function = "gpio";
5109 };
5110
5111 qup_spi10_data_clk: qup-spi10-data-clk-state {
5112 pins = "gpio40", "gpio41", "gpio42";
5113 function = "qup12";
5114 };
5115
5116 qup_spi10_cs: qup-spi10-cs-state {
5117 pins = "gpio43";
5118 function = "qup12";
5119 };
5120
5121 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5122 pins = "gpio43";
5123 function = "gpio";
5124 };
5125
5126 qup_spi11_data_clk: qup-spi11-data-clk-state {
5127 pins = "gpio44", "gpio45", "gpio46";
5128 function = "qup13";
5129 };
5130
5131 qup_spi11_cs: qup-spi11-cs-state {
5132 pins = "gpio47";
5133 function = "qup13";
5134 };
5135
5136 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5137 pins = "gpio47";
5138 function = "gpio";
5139 };
5140
5141 qup_spi12_data_clk: qup-spi12-data-clk-state {
5142 pins = "gpio48", "gpio49", "gpio50";
5143 function = "qup14";
5144 };
5145
5146 qup_spi12_cs: qup-spi12-cs-state {
5147 pins = "gpio51";
5148 function = "qup14";
5149 };
5150
5151 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5152 pins = "gpio51";
5153 function = "gpio";
5154 };
5155
5156 qup_spi13_data_clk: qup-spi13-data-clk-state {
5157 pins = "gpio52", "gpio53", "gpio54";
5158 function = "qup15";
5159 };
5160
5161 qup_spi13_cs: qup-spi13-cs-state {
5162 pins = "gpio55";
5163 function = "qup15";
5164 };
5165
5166 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5167 pins = "gpio55";
5168 function = "gpio";
5169 };
5170
5171 qup_spi14_data_clk: qup-spi14-data-clk-state {
5172 pins = "gpio56", "gpio57", "gpio58";
5173 function = "qup16";
5174 };
5175
5176 qup_spi14_cs: qup-spi14-cs-state {
5177 pins = "gpio59";
5178 function = "qup16";
5179 };
5180
5181 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5182 pins = "gpio59";
5183 function = "gpio";
5184 };
5185
5186 qup_spi15_data_clk: qup-spi15-data-clk-state {
5187 pins = "gpio60", "gpio61", "gpio62";
5188 function = "qup17";
5189 };
5190
5191 qup_spi15_cs: qup-spi15-cs-state {
5192 pins = "gpio63";
5193 function = "qup17";
5194 };
5195
5196 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5197 pins = "gpio63";
5198 function = "gpio";
5199 };
5200
5201 qup_uart0_cts: qup-uart0-cts-state {
5202 pins = "gpio0";
5203 function = "qup00";
5204 };
5205
5206 qup_uart0_rts: qup-uart0-rts-state {
5207 pins = "gpio1";
5208 function = "qup00";
5209 };
5210
5211 qup_uart0_tx: qup-uart0-tx-state {
5212 pins = "gpio2";
5213 function = "qup00";
5214 };
5215
5216 qup_uart0_rx: qup-uart0-rx-state {
5217 pins = "gpio3";
5218 function = "qup00";
5219 };
5220
5221 qup_uart1_cts: qup-uart1-cts-state {
5222 pins = "gpio4";
5223 function = "qup01";
5224 };
5225
5226 qup_uart1_rts: qup-uart1-rts-state {
5227 pins = "gpio5";
5228 function = "qup01";
5229 };
5230
5231 qup_uart1_tx: qup-uart1-tx-state {
5232 pins = "gpio6";
5233 function = "qup01";
5234 };
5235
5236 qup_uart1_rx: qup-uart1-rx-state {
5237 pins = "gpio7";
5238 function = "qup01";
5239 };
5240
5241 qup_uart2_cts: qup-uart2-cts-state {
5242 pins = "gpio8";
5243 function = "qup02";
5244 };
5245
5246 qup_uart2_rts: qup-uart2-rts-state {
5247 pins = "gpio9";
5248 function = "qup02";
5249 };
5250
5251 qup_uart2_tx: qup-uart2-tx-state {
5252 pins = "gpio10";
5253 function = "qup02";
5254 };
5255
5256 qup_uart2_rx: qup-uart2-rx-state {
5257 pins = "gpio11";
5258 function = "qup02";
5259 };
5260
5261 qup_uart3_cts: qup-uart3-cts-state {
5262 pins = "gpio12";
5263 function = "qup03";
5264 };
5265
5266 qup_uart3_rts: qup-uart3-rts-state {
5267 pins = "gpio13";
5268 function = "qup03";
5269 };
5270
5271 qup_uart3_tx: qup-uart3-tx-state {
5272 pins = "gpio14";
5273 function = "qup03";
5274 };
5275
5276 qup_uart3_rx: qup-uart3-rx-state {
5277 pins = "gpio15";
5278 function = "qup03";
5279 };
5280
5281 qup_uart4_cts: qup-uart4-cts-state {
5282 pins = "gpio16";
5283 function = "qup04";
5284 };
5285
5286 qup_uart4_rts: qup-uart4-rts-state {
5287 pins = "gpio17";
5288 function = "qup04";
5289 };
5290
5291 qup_uart4_tx: qup-uart4-tx-state {
5292 pins = "gpio18";
5293 function = "qup04";
5294 };
5295
5296 qup_uart4_rx: qup-uart4-rx-state {
5297 pins = "gpio19";
5298 function = "qup04";
5299 };
5300
5301 qup_uart5_cts: qup-uart5-cts-state {
5302 pins = "gpio20";
5303 function = "qup05";
5304 };
5305
5306 qup_uart5_rts: qup-uart5-rts-state {
5307 pins = "gpio21";
5308 function = "qup05";
5309 };
5310
5311 qup_uart5_tx: qup-uart5-tx-state {
5312 pins = "gpio22";
5313 function = "qup05";
5314 };
5315
5316 qup_uart5_rx: qup-uart5-rx-state {
5317 pins = "gpio23";
5318 function = "qup05";
5319 };
5320
5321 qup_uart6_cts: qup-uart6-cts-state {
5322 pins = "gpio24";
5323 function = "qup06";
5324 };
5325
5326 qup_uart6_rts: qup-uart6-rts-state {
5327 pins = "gpio25";
5328 function = "qup06";
5329 };
5330
5331 qup_uart6_tx: qup-uart6-tx-state {
5332 pins = "gpio26";
5333 function = "qup06";
5334 };
5335
5336 qup_uart6_rx: qup-uart6-rx-state {
5337 pins = "gpio27";
5338 function = "qup06";
5339 };
5340
5341 qup_uart7_cts: qup-uart7-cts-state {
5342 pins = "gpio28";
5343 function = "qup07";
5344 };
5345
5346 qup_uart7_rts: qup-uart7-rts-state {
5347 pins = "gpio29";
5348 function = "qup07";
5349 };
5350
5351 qup_uart7_tx: qup-uart7-tx-state {
5352 pins = "gpio30";
5353 function = "qup07";
5354 };
5355
5356 qup_uart7_rx: qup-uart7-rx-state {
5357 pins = "gpio31";
5358 function = "qup07";
5359 };
5360
5361 qup_uart8_cts: qup-uart8-cts-state {
5362 pins = "gpio32";
5363 function = "qup10";
5364 };
5365
5366 qup_uart8_rts: qup-uart8-rts-state {
5367 pins = "gpio33";
5368 function = "qup10";
5369 };
5370
5371 qup_uart8_tx: qup-uart8-tx-state {
5372 pins = "gpio34";
5373 function = "qup10";
5374 };
5375
5376 qup_uart8_rx: qup-uart8-rx-state {
5377 pins = "gpio35";
5378 function = "qup10";
5379 };
5380
5381 qup_uart9_cts: qup-uart9-cts-state {
5382 pins = "gpio36";
5383 function = "qup11";
5384 };
5385
5386 qup_uart9_rts: qup-uart9-rts-state {
5387 pins = "gpio37";
5388 function = "qup11";
5389 };
5390
5391 qup_uart9_tx: qup-uart9-tx-state {
5392 pins = "gpio38";
5393 function = "qup11";
5394 };
5395
5396 qup_uart9_rx: qup-uart9-rx-state {
5397 pins = "gpio39";
5398 function = "qup11";
5399 };
5400
5401 qup_uart10_cts: qup-uart10-cts-state {
5402 pins = "gpio40";
5403 function = "qup12";
5404 };
5405
5406 qup_uart10_rts: qup-uart10-rts-state {
5407 pins = "gpio41";
5408 function = "qup12";
5409 };
5410
5411 qup_uart10_tx: qup-uart10-tx-state {
5412 pins = "gpio42";
5413 function = "qup12";
5414 };
5415
5416 qup_uart10_rx: qup-uart10-rx-state {
5417 pins = "gpio43";
5418 function = "qup12";
5419 };
5420
5421 qup_uart11_cts: qup-uart11-cts-state {
5422 pins = "gpio44";
5423 function = "qup13";
5424 };
5425
5426 qup_uart11_rts: qup-uart11-rts-state {
5427 pins = "gpio45";
5428 function = "qup13";
5429 };
5430
5431 qup_uart11_tx: qup-uart11-tx-state {
5432 pins = "gpio46";
5433 function = "qup13";
5434 };
5435
5436 qup_uart11_rx: qup-uart11-rx-state {
5437 pins = "gpio47";
5438 function = "qup13";
5439 };
5440
5441 qup_uart12_cts: qup-uart12-cts-state {
5442 pins = "gpio48";
5443 function = "qup14";
5444 };
5445
5446 qup_uart12_rts: qup-uart12-rts-state {
5447 pins = "gpio49";
5448 function = "qup14";
5449 };
5450
5451 qup_uart12_tx: qup-uart12-tx-state {
5452 pins = "gpio50";
5453 function = "qup14";
5454 };
5455
5456 qup_uart12_rx: qup-uart12-rx-state {
5457 pins = "gpio51";
5458 function = "qup14";
5459 };
5460
5461 qup_uart13_cts: qup-uart13-cts-state {
5462 pins = "gpio52";
5463 function = "qup15";
5464 };
5465
5466 qup_uart13_rts: qup-uart13-rts-state {
5467 pins = "gpio53";
5468 function = "qup15";
5469 };
5470
5471 qup_uart13_tx: qup-uart13-tx-state {
5472 pins = "gpio54";
5473 function = "qup15";
5474 };
5475
5476 qup_uart13_rx: qup-uart13-rx-state {
5477 pins = "gpio55";
5478 function = "qup15";
5479 };
5480
5481 qup_uart14_cts: qup-uart14-cts-state {
5482 pins = "gpio56";
5483 function = "qup16";
5484 };
5485
5486 qup_uart14_rts: qup-uart14-rts-state {
5487 pins = "gpio57";
5488 function = "qup16";
5489 };
5490
5491 qup_uart14_tx: qup-uart14-tx-state {
5492 pins = "gpio58";
5493 function = "qup16";
5494 };
5495
5496 qup_uart14_rx: qup-uart14-rx-state {
5497 pins = "gpio59";
5498 function = "qup16";
5499 };
5500
5501 qup_uart15_cts: qup-uart15-cts-state {
5502 pins = "gpio60";
5503 function = "qup17";
5504 };
5505
5506 qup_uart15_rts: qup-uart15-rts-state {
5507 pins = "gpio61";
5508 function = "qup17";
5509 };
5510
5511 qup_uart15_tx: qup-uart15-tx-state {
5512 pins = "gpio62";
5513 function = "qup17";
5514 };
5515
5516 qup_uart15_rx: qup-uart15-rx-state {
5517 pins = "gpio63";
5518 function = "qup17";
5519 };
5520
5521 sdc1_clk: sdc1-clk-state {
5522 pins = "sdc1_clk";
5523 };
5524
5525 sdc1_cmd: sdc1-cmd-state {
5526 pins = "sdc1_cmd";
5527 };
5528
5529 sdc1_data: sdc1-data-state {
5530 pins = "sdc1_data";
5531 };
5532
5533 sdc1_rclk: sdc1-rclk-state {
5534 pins = "sdc1_rclk";
5535 };
5536
5537 sdc1_clk_sleep: sdc1-clk-sleep-state {
5538 pins = "sdc1_clk";
5539 drive-strength = <2>;
5540 bias-bus-hold;
5541 };
5542
5543 sdc1_cmd_sleep: sdc1-cmd-sleep-state {
5544 pins = "sdc1_cmd";
5545 drive-strength = <2>;
5546 bias-bus-hold;
5547 };
5548
5549 sdc1_data_sleep: sdc1-data-sleep-state {
5550 pins = "sdc1_data";
5551 drive-strength = <2>;
5552 bias-bus-hold;
5553 };
5554
5555 sdc1_rclk_sleep: sdc1-rclk-sleep-state {
5556 pins = "sdc1_rclk";
5557 drive-strength = <2>;
5558 bias-bus-hold;
5559 };
5560
5561 sdc2_clk: sdc2-clk-state {
5562 pins = "sdc2_clk";
5563 };
5564
5565 sdc2_cmd: sdc2-cmd-state {
5566 pins = "sdc2_cmd";
5567 };
5568
5569 sdc2_data: sdc2-data-state {
5570 pins = "sdc2_data";
5571 };
5572
5573 sdc2_clk_sleep: sdc2-clk-sleep-state {
5574 pins = "sdc2_clk";
5575 drive-strength = <2>;
5576 bias-bus-hold;
5577 };
5578
5579 sdc2_cmd_sleep: sdc2-cmd-sleep-state {
5580 pins = "sdc2_cmd";
5581 drive-strength = <2>;
5582 bias-bus-hold;
5583 };
5584
5585 sdc2_data_sleep: sdc2-data-sleep-state {
5586 pins = "sdc2_data";
5587 drive-strength = <2>;
5588 bias-bus-hold;
5589 };
5590 };
5591
5592 sram@146a5000 {
5593 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd";
5594 reg = <0 0x146a5000 0 0x6000>;
5595
5596 #address-cells = <1>;
5597 #size-cells = <1>;
5598
5599 ranges = <0 0 0x146a5000 0x6000>;
5600
5601 pil-reloc@594c {
5602 compatible = "qcom,pil-reloc-info";
5603 reg = <0x594c 0xc8>;
5604 };
5605 };
5606
5607 apps_smmu: iommu@15000000 {
5608 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
5609 reg = <0 0x15000000 0 0x100000>;
5610 #iommu-cells = <2>;
5611 #global-interrupts = <1>;
5612 dma-coherent;
5613 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5614 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5615 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5616 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5617 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5618 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5619 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5620 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5621 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5622 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5623 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5624 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5625 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5626 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5627 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5628 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5629 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5630 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5631 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5632 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5633 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5634 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5635 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5636 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5637 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5638 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5639 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5640 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5641 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5642 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5643 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5644 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5645 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5646 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5647 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5648 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5649 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5650 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5651 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5652 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5653 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5654 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5655 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5656 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5657 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5658 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5659 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5660 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5661 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5662 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5663 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5664 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5665 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5666 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5667 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5668 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5669 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5670 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5671 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5672 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5673 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5674 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5675 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5676 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5677 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5678 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5679 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5680 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5681 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5682 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5683 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5684 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5685 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5686 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5687 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5688 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5689 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5690 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5691 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5692 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5693 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
5694 };
5695
5696 intc: interrupt-controller@17a00000 {
5697 compatible = "arm,gic-v3";
5698 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5699 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5700 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
5701 #interrupt-cells = <3>;
5702 interrupt-controller;
5703 #address-cells = <2>;
5704 #size-cells = <2>;
5705 ranges;
5706
5707 msi-controller@17a40000 {
5708 compatible = "arm,gic-v3-its";
5709 reg = <0 0x17a40000 0 0x20000>;
5710 msi-controller;
5711 #msi-cells = <1>;
5712 status = "disabled";
5713 };
5714 };
5715
5716 watchdog: watchdog@17c10000 {
5717 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
5718 reg = <0 0x17c10000 0 0x1000>;
5719 clocks = <&sleep_clk>;
5720 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
5721 status = "reserved"; /* Owned by Gunyah hyp */
5722 };
5723
5724 timer@17c20000 {
5725 #address-cells = <1>;
5726 #size-cells = <1>;
5727 ranges = <0 0 0 0x20000000>;
5728 compatible = "arm,armv7-timer-mem";
5729 reg = <0 0x17c20000 0 0x1000>;
5730
5731 frame@17c21000 {
5732 frame-number = <0>;
5733 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
5734 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5735 reg = <0x17c21000 0x1000>,
5736 <0x17c22000 0x1000>;
5737 };
5738
5739 frame@17c23000 {
5740 frame-number = <1>;
5741 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5742 reg = <0x17c23000 0x1000>;
5743 status = "disabled";
5744 };
5745
5746 frame@17c25000 {
5747 frame-number = <2>;
5748 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5749 reg = <0x17c25000 0x1000>;
5750 status = "disabled";
5751 };
5752
5753 frame@17c27000 {
5754 frame-number = <3>;
5755 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5756 reg = <0x17c27000 0x1000>;
5757 status = "disabled";
5758 };
5759
5760 frame@17c29000 {
5761 frame-number = <4>;
5762 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5763 reg = <0x17c29000 0x1000>;
5764 status = "disabled";
5765 };
5766
5767 frame@17c2b000 {
5768 frame-number = <5>;
5769 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5770 reg = <0x17c2b000 0x1000>;
5771 status = "disabled";
5772 };
5773
5774 frame@17c2d000 {
5775 frame-number = <6>;
5776 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
5777 reg = <0x17c2d000 0x1000>;
5778 status = "disabled";
5779 };
5780 };
5781
5782 apps_rsc: rsc@18200000 {
5783 compatible = "qcom,rpmh-rsc";
5784 reg = <0 0x18200000 0 0x10000>,
5785 <0 0x18210000 0 0x10000>,
5786 <0 0x18220000 0 0x10000>;
5787 reg-names = "drv-0", "drv-1", "drv-2";
5788 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5789 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5790 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5791 qcom,tcs-offset = <0xd00>;
5792 qcom,drv-id = <2>;
5793 qcom,tcs-config = <ACTIVE_TCS 2>,
5794 <SLEEP_TCS 3>,
5795 <WAKE_TCS 3>,
5796 <CONTROL_TCS 1>;
5797 power-domains = <&CLUSTER_PD>;
5798
5799 apps_bcm_voter: bcm-voter {
5800 compatible = "qcom,bcm-voter";
5801 };
5802
5803 rpmhpd: power-controller {
5804 compatible = "qcom,sc7280-rpmhpd";
5805 #power-domain-cells = <1>;
5806 operating-points-v2 = <&rpmhpd_opp_table>;
5807
5808 rpmhpd_opp_table: opp-table {
5809 compatible = "operating-points-v2";
5810
5811 rpmhpd_opp_ret: opp1 {
5812 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5813 };
5814
5815 rpmhpd_opp_low_svs: opp2 {
5816 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5817 };
5818
5819 rpmhpd_opp_svs: opp3 {
5820 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5821 };
5822
5823 rpmhpd_opp_svs_l1: opp4 {
5824 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5825 };
5826
5827 rpmhpd_opp_svs_l2: opp5 {
5828 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
5829 };
5830
5831 rpmhpd_opp_nom: opp6 {
5832 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5833 };
5834
5835 rpmhpd_opp_nom_l1: opp7 {
5836 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5837 };
5838
5839 rpmhpd_opp_turbo: opp8 {
5840 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5841 };
5842
5843 rpmhpd_opp_turbo_l1: opp9 {
5844 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5845 };
5846 };
5847 };
5848
5849 rpmhcc: clock-controller {
5850 compatible = "qcom,sc7280-rpmh-clk";
5851 clocks = <&xo_board>;
5852 clock-names = "xo";
5853 #clock-cells = <1>;
5854 };
5855 };
5856
5857 epss_l3: interconnect@18590000 {
5858 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3";
5859 reg = <0 0x18590000 0 0x1000>;
5860 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5861 clock-names = "xo", "alternate";
5862 #interconnect-cells = <1>;
5863 };
5864
5865 cpufreq_hw: cpufreq@18591000 {
5866 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss";
5867 reg = <0 0x18591000 0 0x1000>,
5868 <0 0x18592000 0 0x1000>,
5869 <0 0x18593000 0 0x1000>;
5870
5871 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
5872 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
5873 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
5874 interrupt-names = "dcvsh-irq-0",
5875 "dcvsh-irq-1",
5876 "dcvsh-irq-2";
5877
5878 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5879 clock-names = "xo", "alternate";
5880 #freq-domain-cells = <1>;
5881 #clock-cells = <1>;
5882 };
5883 };
5884
5885 thermal_zones: thermal-zones {
5886 cpu0-thermal {
5887 polling-delay-passive = <250>;
5888 polling-delay = <0>;
5889
5890 thermal-sensors = <&tsens0 1>;
5891
5892 trips {
5893 cpu0_alert0: trip-point0 {
5894 temperature = <90000>;
5895 hysteresis = <2000>;
5896 type = "passive";
5897 };
5898
5899 cpu0_alert1: trip-point1 {
5900 temperature = <95000>;
5901 hysteresis = <2000>;
5902 type = "passive";
5903 };
5904
5905 cpu0_crit: cpu-crit {
5906 temperature = <110000>;
5907 hysteresis = <0>;
5908 type = "critical";
5909 };
5910 };
5911
5912 cooling-maps {
5913 map0 {
5914 trip = <&cpu0_alert0>;
5915 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5916 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5917 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5918 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5919 };
5920 map1 {
5921 trip = <&cpu0_alert1>;
5922 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5923 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5924 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5925 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5926 };
5927 };
5928 };
5929
5930 cpu1-thermal {
5931 polling-delay-passive = <250>;
5932 polling-delay = <0>;
5933
5934 thermal-sensors = <&tsens0 2>;
5935
5936 trips {
5937 cpu1_alert0: trip-point0 {
5938 temperature = <90000>;
5939 hysteresis = <2000>;
5940 type = "passive";
5941 };
5942
5943 cpu1_alert1: trip-point1 {
5944 temperature = <95000>;
5945 hysteresis = <2000>;
5946 type = "passive";
5947 };
5948
5949 cpu1_crit: cpu-crit {
5950 temperature = <110000>;
5951 hysteresis = <0>;
5952 type = "critical";
5953 };
5954 };
5955
5956 cooling-maps {
5957 map0 {
5958 trip = <&cpu1_alert0>;
5959 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5960 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5961 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5962 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5963 };
5964 map1 {
5965 trip = <&cpu1_alert1>;
5966 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5967 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5968 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5969 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5970 };
5971 };
5972 };
5973
5974 cpu2-thermal {
5975 polling-delay-passive = <250>;
5976 polling-delay = <0>;
5977
5978 thermal-sensors = <&tsens0 3>;
5979
5980 trips {
5981 cpu2_alert0: trip-point0 {
5982 temperature = <90000>;
5983 hysteresis = <2000>;
5984 type = "passive";
5985 };
5986
5987 cpu2_alert1: trip-point1 {
5988 temperature = <95000>;
5989 hysteresis = <2000>;
5990 type = "passive";
5991 };
5992
5993 cpu2_crit: cpu-crit {
5994 temperature = <110000>;
5995 hysteresis = <0>;
5996 type = "critical";
5997 };
5998 };
5999
6000 cooling-maps {
6001 map0 {
6002 trip = <&cpu2_alert0>;
6003 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6004 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6005 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6006 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6007 };
6008 map1 {
6009 trip = <&cpu2_alert1>;
6010 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6011 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6012 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6013 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6014 };
6015 };
6016 };
6017
6018 cpu3-thermal {
6019 polling-delay-passive = <250>;
6020 polling-delay = <0>;
6021
6022 thermal-sensors = <&tsens0 4>;
6023
6024 trips {
6025 cpu3_alert0: trip-point0 {
6026 temperature = <90000>;
6027 hysteresis = <2000>;
6028 type = "passive";
6029 };
6030
6031 cpu3_alert1: trip-point1 {
6032 temperature = <95000>;
6033 hysteresis = <2000>;
6034 type = "passive";
6035 };
6036
6037 cpu3_crit: cpu-crit {
6038 temperature = <110000>;
6039 hysteresis = <0>;
6040 type = "critical";
6041 };
6042 };
6043
6044 cooling-maps {
6045 map0 {
6046 trip = <&cpu3_alert0>;
6047 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6048 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6049 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6050 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6051 };
6052 map1 {
6053 trip = <&cpu3_alert1>;
6054 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6055 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6056 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6057 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6058 };
6059 };
6060 };
6061
6062 cpu4-thermal {
6063 polling-delay-passive = <250>;
6064 polling-delay = <0>;
6065
6066 thermal-sensors = <&tsens0 7>;
6067
6068 trips {
6069 cpu4_alert0: trip-point0 {
6070 temperature = <90000>;
6071 hysteresis = <2000>;
6072 type = "passive";
6073 };
6074
6075 cpu4_alert1: trip-point1 {
6076 temperature = <95000>;
6077 hysteresis = <2000>;
6078 type = "passive";
6079 };
6080
6081 cpu4_crit: cpu-crit {
6082 temperature = <110000>;
6083 hysteresis = <0>;
6084 type = "critical";
6085 };
6086 };
6087
6088 cooling-maps {
6089 map0 {
6090 trip = <&cpu4_alert0>;
6091 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6092 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6093 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6094 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6095 };
6096 map1 {
6097 trip = <&cpu4_alert1>;
6098 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6099 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6100 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6101 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6102 };
6103 };
6104 };
6105
6106 cpu5-thermal {
6107 polling-delay-passive = <250>;
6108 polling-delay = <0>;
6109
6110 thermal-sensors = <&tsens0 8>;
6111
6112 trips {
6113 cpu5_alert0: trip-point0 {
6114 temperature = <90000>;
6115 hysteresis = <2000>;
6116 type = "passive";
6117 };
6118
6119 cpu5_alert1: trip-point1 {
6120 temperature = <95000>;
6121 hysteresis = <2000>;
6122 type = "passive";
6123 };
6124
6125 cpu5_crit: cpu-crit {
6126 temperature = <110000>;
6127 hysteresis = <0>;
6128 type = "critical";
6129 };
6130 };
6131
6132 cooling-maps {
6133 map0 {
6134 trip = <&cpu5_alert0>;
6135 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6136 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6137 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6138 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6139 };
6140 map1 {
6141 trip = <&cpu5_alert1>;
6142 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6143 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6144 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6145 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6146 };
6147 };
6148 };
6149
6150 cpu6-thermal {
6151 polling-delay-passive = <250>;
6152 polling-delay = <0>;
6153
6154 thermal-sensors = <&tsens0 9>;
6155
6156 trips {
6157 cpu6_alert0: trip-point0 {
6158 temperature = <90000>;
6159 hysteresis = <2000>;
6160 type = "passive";
6161 };
6162
6163 cpu6_alert1: trip-point1 {
6164 temperature = <95000>;
6165 hysteresis = <2000>;
6166 type = "passive";
6167 };
6168
6169 cpu6_crit: cpu-crit {
6170 temperature = <110000>;
6171 hysteresis = <0>;
6172 type = "critical";
6173 };
6174 };
6175
6176 cooling-maps {
6177 map0 {
6178 trip = <&cpu6_alert0>;
6179 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6180 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6181 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6182 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6183 };
6184 map1 {
6185 trip = <&cpu6_alert1>;
6186 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6187 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6188 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6189 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6190 };
6191 };
6192 };
6193
6194 cpu7-thermal {
6195 polling-delay-passive = <250>;
6196 polling-delay = <0>;
6197
6198 thermal-sensors = <&tsens0 10>;
6199
6200 trips {
6201 cpu7_alert0: trip-point0 {
6202 temperature = <90000>;
6203 hysteresis = <2000>;
6204 type = "passive";
6205 };
6206
6207 cpu7_alert1: trip-point1 {
6208 temperature = <95000>;
6209 hysteresis = <2000>;
6210 type = "passive";
6211 };
6212
6213 cpu7_crit: cpu-crit {
6214 temperature = <110000>;
6215 hysteresis = <0>;
6216 type = "critical";
6217 };
6218 };
6219
6220 cooling-maps {
6221 map0 {
6222 trip = <&cpu7_alert0>;
6223 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6224 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6225 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6226 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6227 };
6228 map1 {
6229 trip = <&cpu7_alert1>;
6230 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6231 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6232 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6233 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6234 };
6235 };
6236 };
6237
6238 cpu8-thermal {
6239 polling-delay-passive = <250>;
6240 polling-delay = <0>;
6241
6242 thermal-sensors = <&tsens0 11>;
6243
6244 trips {
6245 cpu8_alert0: trip-point0 {
6246 temperature = <90000>;
6247 hysteresis = <2000>;
6248 type = "passive";
6249 };
6250
6251 cpu8_alert1: trip-point1 {
6252 temperature = <95000>;
6253 hysteresis = <2000>;
6254 type = "passive";
6255 };
6256
6257 cpu8_crit: cpu-crit {
6258 temperature = <110000>;
6259 hysteresis = <0>;
6260 type = "critical";
6261 };
6262 };
6263
6264 cooling-maps {
6265 map0 {
6266 trip = <&cpu8_alert0>;
6267 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6268 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6269 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6270 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6271 };
6272 map1 {
6273 trip = <&cpu8_alert1>;
6274 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6275 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6276 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6277 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6278 };
6279 };
6280 };
6281
6282 cpu9-thermal {
6283 polling-delay-passive = <250>;
6284 polling-delay = <0>;
6285
6286 thermal-sensors = <&tsens0 12>;
6287
6288 trips {
6289 cpu9_alert0: trip-point0 {
6290 temperature = <90000>;
6291 hysteresis = <2000>;
6292 type = "passive";
6293 };
6294
6295 cpu9_alert1: trip-point1 {
6296 temperature = <95000>;
6297 hysteresis = <2000>;
6298 type = "passive";
6299 };
6300
6301 cpu9_crit: cpu-crit {
6302 temperature = <110000>;
6303 hysteresis = <0>;
6304 type = "critical";
6305 };
6306 };
6307
6308 cooling-maps {
6309 map0 {
6310 trip = <&cpu9_alert0>;
6311 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6312 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6313 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6314 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6315 };
6316 map1 {
6317 trip = <&cpu9_alert1>;
6318 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6319 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6320 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6321 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6322 };
6323 };
6324 };
6325
6326 cpu10-thermal {
6327 polling-delay-passive = <250>;
6328 polling-delay = <0>;
6329
6330 thermal-sensors = <&tsens0 13>;
6331
6332 trips {
6333 cpu10_alert0: trip-point0 {
6334 temperature = <90000>;
6335 hysteresis = <2000>;
6336 type = "passive";
6337 };
6338
6339 cpu10_alert1: trip-point1 {
6340 temperature = <95000>;
6341 hysteresis = <2000>;
6342 type = "passive";
6343 };
6344
6345 cpu10_crit: cpu-crit {
6346 temperature = <110000>;
6347 hysteresis = <0>;
6348 type = "critical";
6349 };
6350 };
6351
6352 cooling-maps {
6353 map0 {
6354 trip = <&cpu10_alert0>;
6355 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6356 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6357 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6358 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6359 };
6360 map1 {
6361 trip = <&cpu10_alert1>;
6362 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6363 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6364 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6365 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6366 };
6367 };
6368 };
6369
6370 cpu11-thermal {
6371 polling-delay-passive = <250>;
6372 polling-delay = <0>;
6373
6374 thermal-sensors = <&tsens0 14>;
6375
6376 trips {
6377 cpu11_alert0: trip-point0 {
6378 temperature = <90000>;
6379 hysteresis = <2000>;
6380 type = "passive";
6381 };
6382
6383 cpu11_alert1: trip-point1 {
6384 temperature = <95000>;
6385 hysteresis = <2000>;
6386 type = "passive";
6387 };
6388
6389 cpu11_crit: cpu-crit {
6390 temperature = <110000>;
6391 hysteresis = <0>;
6392 type = "critical";
6393 };
6394 };
6395
6396 cooling-maps {
6397 map0 {
6398 trip = <&cpu11_alert0>;
6399 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6400 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6401 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6402 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6403 };
6404 map1 {
6405 trip = <&cpu11_alert1>;
6406 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6407 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6408 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6409 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6410 };
6411 };
6412 };
6413
6414 aoss0-thermal {
6415 polling-delay-passive = <0>;
6416 polling-delay = <0>;
6417
6418 thermal-sensors = <&tsens0 0>;
6419
6420 trips {
6421 aoss0_alert0: trip-point0 {
6422 temperature = <90000>;
6423 hysteresis = <2000>;
6424 type = "hot";
6425 };
6426
6427 aoss0_crit: aoss0-crit {
6428 temperature = <110000>;
6429 hysteresis = <0>;
6430 type = "critical";
6431 };
6432 };
6433 };
6434
6435 aoss1-thermal {
6436 polling-delay-passive = <0>;
6437 polling-delay = <0>;
6438
6439 thermal-sensors = <&tsens1 0>;
6440
6441 trips {
6442 aoss1_alert0: trip-point0 {
6443 temperature = <90000>;
6444 hysteresis = <2000>;
6445 type = "hot";
6446 };
6447
6448 aoss1_crit: aoss1-crit {
6449 temperature = <110000>;
6450 hysteresis = <0>;
6451 type = "critical";
6452 };
6453 };
6454 };
6455
6456 cpuss0-thermal {
6457 polling-delay-passive = <0>;
6458 polling-delay = <0>;
6459
6460 thermal-sensors = <&tsens0 5>;
6461
6462 trips {
6463 cpuss0_alert0: trip-point0 {
6464 temperature = <90000>;
6465 hysteresis = <2000>;
6466 type = "hot";
6467 };
6468 cpuss0_crit: cluster0-crit {
6469 temperature = <110000>;
6470 hysteresis = <0>;
6471 type = "critical";
6472 };
6473 };
6474 };
6475
6476 cpuss1-thermal {
6477 polling-delay-passive = <0>;
6478 polling-delay = <0>;
6479
6480 thermal-sensors = <&tsens0 6>;
6481
6482 trips {
6483 cpuss1_alert0: trip-point0 {
6484 temperature = <90000>;
6485 hysteresis = <2000>;
6486 type = "hot";
6487 };
6488 cpuss1_crit: cluster0-crit {
6489 temperature = <110000>;
6490 hysteresis = <0>;
6491 type = "critical";
6492 };
6493 };
6494 };
6495
6496 gpuss0-thermal {
6497 polling-delay-passive = <100>;
6498 polling-delay = <0>;
6499
6500 thermal-sensors = <&tsens1 1>;
6501
6502 trips {
6503 gpuss0_alert0: trip-point0 {
6504 temperature = <95000>;
6505 hysteresis = <2000>;
6506 type = "passive";
6507 };
6508
6509 gpuss0_crit: gpuss0-crit {
6510 temperature = <110000>;
6511 hysteresis = <0>;
6512 type = "critical";
6513 };
6514 };
6515
6516 cooling-maps {
6517 map0 {
6518 trip = <&gpuss0_alert0>;
6519 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6520 };
6521 };
6522 };
6523
6524 gpuss1-thermal {
6525 polling-delay-passive = <100>;
6526 polling-delay = <0>;
6527
6528 thermal-sensors = <&tsens1 2>;
6529
6530 trips {
6531 gpuss1_alert0: trip-point0 {
6532 temperature = <95000>;
6533 hysteresis = <2000>;
6534 type = "passive";
6535 };
6536
6537 gpuss1_crit: gpuss1-crit {
6538 temperature = <110000>;
6539 hysteresis = <0>;
6540 type = "critical";
6541 };
6542 };
6543
6544 cooling-maps {
6545 map0 {
6546 trip = <&gpuss1_alert0>;
6547 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6548 };
6549 };
6550 };
6551
6552 nspss0-thermal {
6553 polling-delay-passive = <0>;
6554 polling-delay = <0>;
6555
6556 thermal-sensors = <&tsens1 3>;
6557
6558 trips {
6559 nspss0_alert0: trip-point0 {
6560 temperature = <90000>;
6561 hysteresis = <2000>;
6562 type = "hot";
6563 };
6564
6565 nspss0_crit: nspss0-crit {
6566 temperature = <110000>;
6567 hysteresis = <0>;
6568 type = "critical";
6569 };
6570 };
6571 };
6572
6573 nspss1-thermal {
6574 polling-delay-passive = <0>;
6575 polling-delay = <0>;
6576
6577 thermal-sensors = <&tsens1 4>;
6578
6579 trips {
6580 nspss1_alert0: trip-point0 {
6581 temperature = <90000>;
6582 hysteresis = <2000>;
6583 type = "hot";
6584 };
6585
6586 nspss1_crit: nspss1-crit {
6587 temperature = <110000>;
6588 hysteresis = <0>;
6589 type = "critical";
6590 };
6591 };
6592 };
6593
6594 video-thermal {
6595 polling-delay-passive = <0>;
6596 polling-delay = <0>;
6597
6598 thermal-sensors = <&tsens1 5>;
6599
6600 trips {
6601 video_alert0: trip-point0 {
6602 temperature = <90000>;
6603 hysteresis = <2000>;
6604 type = "hot";
6605 };
6606
6607 video_crit: video-crit {
6608 temperature = <110000>;
6609 hysteresis = <0>;
6610 type = "critical";
6611 };
6612 };
6613 };
6614
6615 ddr-thermal {
6616 polling-delay-passive = <0>;
6617 polling-delay = <0>;
6618
6619 thermal-sensors = <&tsens1 6>;
6620
6621 trips {
6622 ddr_alert0: trip-point0 {
6623 temperature = <90000>;
6624 hysteresis = <2000>;
6625 type = "hot";
6626 };
6627
6628 ddr_crit: ddr-crit {
6629 temperature = <110000>;
6630 hysteresis = <0>;
6631 type = "critical";
6632 };
6633 };
6634 };
6635
6636 mdmss0-thermal {
6637 polling-delay-passive = <0>;
6638 polling-delay = <0>;
6639
6640 thermal-sensors = <&tsens1 7>;
6641
6642 trips {
6643 mdmss0_alert0: trip-point0 {
6644 temperature = <90000>;
6645 hysteresis = <2000>;
6646 type = "hot";
6647 };
6648
6649 mdmss0_crit: mdmss0-crit {
6650 temperature = <110000>;
6651 hysteresis = <0>;
6652 type = "critical";
6653 };
6654 };
6655 };
6656
6657 mdmss1-thermal {
6658 polling-delay-passive = <0>;
6659 polling-delay = <0>;
6660
6661 thermal-sensors = <&tsens1 8>;
6662
6663 trips {
6664 mdmss1_alert0: trip-point0 {
6665 temperature = <90000>;
6666 hysteresis = <2000>;
6667 type = "hot";
6668 };
6669
6670 mdmss1_crit: mdmss1-crit {
6671 temperature = <110000>;
6672 hysteresis = <0>;
6673 type = "critical";
6674 };
6675 };
6676 };
6677
6678 mdmss2-thermal {
6679 polling-delay-passive = <0>;
6680 polling-delay = <0>;
6681
6682 thermal-sensors = <&tsens1 9>;
6683
6684 trips {
6685 mdmss2_alert0: trip-point0 {
6686 temperature = <90000>;
6687 hysteresis = <2000>;
6688 type = "hot";
6689 };
6690
6691 mdmss2_crit: mdmss2-crit {
6692 temperature = <110000>;
6693 hysteresis = <0>;
6694 type = "critical";
6695 };
6696 };
6697 };
6698
6699 mdmss3-thermal {
6700 polling-delay-passive = <0>;
6701 polling-delay = <0>;
6702
6703 thermal-sensors = <&tsens1 10>;
6704
6705 trips {
6706 mdmss3_alert0: trip-point0 {
6707 temperature = <90000>;
6708 hysteresis = <2000>;
6709 type = "hot";
6710 };
6711
6712 mdmss3_crit: mdmss3-crit {
6713 temperature = <110000>;
6714 hysteresis = <0>;
6715 type = "critical";
6716 };
6717 };
6718 };
6719
6720 camera0-thermal {
6721 polling-delay-passive = <0>;
6722 polling-delay = <0>;
6723
6724 thermal-sensors = <&tsens1 11>;
6725
6726 trips {
6727 camera0_alert0: trip-point0 {
6728 temperature = <90000>;
6729 hysteresis = <2000>;
6730 type = "hot";
6731 };
6732
6733 camera0_crit: camera0-crit {
6734 temperature = <110000>;
6735 hysteresis = <0>;
6736 type = "critical";
6737 };
6738 };
6739 };
6740 };
6741
6742 timer {
6743 compatible = "arm,armv8-timer";
6744 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
6745 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
6746 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
6747 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
6748 };
6749 };
"Das U-Boot" Source Tree