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[thirdparty/u-boot.git] / src / arm64 / qcom / sdm670.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SDM670 SoC device tree source, adapted from SDM845 SoC device tree
4 *
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2022, Richard Acayan. All rights reserved.
7 */
8
9 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/phy/phy-qcom-qusb2.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
19
20 / {
21 interrupt-parent = <&intc>;
22
23 #address-cells = <2>;
24 #size-cells = <2>;
25
26 aliases { };
27
28 chosen { };
29
30 cpus {
31 #address-cells = <2>;
32 #size-cells = <0>;
33
34 CPU0: cpu@0 {
35 device_type = "cpu";
36 compatible = "qcom,kryo360";
37 reg = <0x0 0x0>;
38 enable-method = "psci";
39 capacity-dmips-mhz = <610>;
40 dynamic-power-coefficient = <203>;
41 qcom,freq-domain = <&cpufreq_hw 0>;
42 operating-points-v2 = <&cpu0_opp_table>;
43 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
44 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
45 power-domains = <&CPU_PD0>;
46 power-domain-names = "psci";
47 next-level-cache = <&L2_0>;
48 L2_0: l2-cache {
49 compatible = "cache";
50 next-level-cache = <&L3_0>;
51 cache-level = <2>;
52 cache-unified;
53 L3_0: l3-cache {
54 compatible = "cache";
55 cache-level = <3>;
56 cache-unified;
57 };
58 };
59 };
60
61 CPU1: cpu@100 {
62 device_type = "cpu";
63 compatible = "qcom,kryo360";
64 reg = <0x0 0x100>;
65 enable-method = "psci";
66 capacity-dmips-mhz = <610>;
67 dynamic-power-coefficient = <203>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
69 operating-points-v2 = <&cpu0_opp_table>;
70 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
71 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
72 power-domains = <&CPU_PD1>;
73 power-domain-names = "psci";
74 next-level-cache = <&L2_100>;
75 L2_100: l2-cache {
76 compatible = "cache";
77 cache-level = <2>;
78 cache-unified;
79 next-level-cache = <&L3_0>;
80 };
81 };
82
83 CPU2: cpu@200 {
84 device_type = "cpu";
85 compatible = "qcom,kryo360";
86 reg = <0x0 0x200>;
87 enable-method = "psci";
88 capacity-dmips-mhz = <610>;
89 dynamic-power-coefficient = <203>;
90 qcom,freq-domain = <&cpufreq_hw 0>;
91 operating-points-v2 = <&cpu0_opp_table>;
92 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
93 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
94 power-domains = <&CPU_PD2>;
95 power-domain-names = "psci";
96 next-level-cache = <&L2_200>;
97 L2_200: l2-cache {
98 compatible = "cache";
99 cache-level = <2>;
100 cache-unified;
101 next-level-cache = <&L3_0>;
102 };
103 };
104
105 CPU3: cpu@300 {
106 device_type = "cpu";
107 compatible = "qcom,kryo360";
108 reg = <0x0 0x300>;
109 enable-method = "psci";
110 capacity-dmips-mhz = <610>;
111 dynamic-power-coefficient = <203>;
112 qcom,freq-domain = <&cpufreq_hw 0>;
113 operating-points-v2 = <&cpu0_opp_table>;
114 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
115 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
116 power-domains = <&CPU_PD3>;
117 power-domain-names = "psci";
118 next-level-cache = <&L2_300>;
119 L2_300: l2-cache {
120 compatible = "cache";
121 cache-level = <2>;
122 cache-unified;
123 next-level-cache = <&L3_0>;
124 };
125 };
126
127 CPU4: cpu@400 {
128 device_type = "cpu";
129 compatible = "qcom,kryo360";
130 reg = <0x0 0x400>;
131 enable-method = "psci";
132 capacity-dmips-mhz = <610>;
133 dynamic-power-coefficient = <203>;
134 qcom,freq-domain = <&cpufreq_hw 0>;
135 operating-points-v2 = <&cpu0_opp_table>;
136 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
137 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
138 power-domains = <&CPU_PD4>;
139 power-domain-names = "psci";
140 next-level-cache = <&L2_400>;
141 L2_400: l2-cache {
142 compatible = "cache";
143 cache-level = <2>;
144 cache-unified;
145 next-level-cache = <&L3_0>;
146 };
147 };
148
149 CPU5: cpu@500 {
150 device_type = "cpu";
151 compatible = "qcom,kryo360";
152 reg = <0x0 0x500>;
153 enable-method = "psci";
154 capacity-dmips-mhz = <610>;
155 dynamic-power-coefficient = <203>;
156 qcom,freq-domain = <&cpufreq_hw 0>;
157 operating-points-v2 = <&cpu0_opp_table>;
158 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
159 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
160 power-domains = <&CPU_PD5>;
161 power-domain-names = "psci";
162 next-level-cache = <&L2_500>;
163 L2_500: l2-cache {
164 compatible = "cache";
165 cache-level = <2>;
166 cache-unified;
167 next-level-cache = <&L3_0>;
168 };
169 };
170
171 CPU6: cpu@600 {
172 device_type = "cpu";
173 compatible = "qcom,kryo360";
174 reg = <0x0 0x600>;
175 enable-method = "psci";
176 capacity-dmips-mhz = <1024>;
177 dynamic-power-coefficient = <393>;
178 qcom,freq-domain = <&cpufreq_hw 1>;
179 operating-points-v2 = <&cpu6_opp_table>;
180 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
181 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
182 power-domains = <&CPU_PD6>;
183 power-domain-names = "psci";
184 next-level-cache = <&L2_600>;
185 L2_600: l2-cache {
186 compatible = "cache";
187 cache-level = <2>;
188 cache-unified;
189 next-level-cache = <&L3_0>;
190 };
191 };
192
193 CPU7: cpu@700 {
194 device_type = "cpu";
195 compatible = "qcom,kryo360";
196 reg = <0x0 0x700>;
197 enable-method = "psci";
198 capacity-dmips-mhz = <1024>;
199 dynamic-power-coefficient = <393>;
200 qcom,freq-domain = <&cpufreq_hw 1>;
201 operating-points-v2 = <&cpu6_opp_table>;
202 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>,
203 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
204 power-domains = <&CPU_PD7>;
205 power-domain-names = "psci";
206 next-level-cache = <&L2_700>;
207 L2_700: l2-cache {
208 compatible = "cache";
209 cache-level = <2>;
210 cache-unified;
211 next-level-cache = <&L3_0>;
212 };
213 };
214
215 cpu-map {
216 cluster0 {
217 core0 {
218 cpu = <&CPU0>;
219 };
220
221 core1 {
222 cpu = <&CPU1>;
223 };
224
225 core2 {
226 cpu = <&CPU2>;
227 };
228
229 core3 {
230 cpu = <&CPU3>;
231 };
232
233 core4 {
234 cpu = <&CPU4>;
235 };
236
237 core5 {
238 cpu = <&CPU5>;
239 };
240
241 core6 {
242 cpu = <&CPU6>;
243 };
244
245 core7 {
246 cpu = <&CPU7>;
247 };
248 };
249 };
250
251 idle-states {
252 entry-method = "psci";
253
254 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
255 compatible = "arm,idle-state";
256 idle-state-name = "little-rail-power-collapse";
257 arm,psci-suspend-param = <0x40000004>;
258 entry-latency-us = <702>;
259 exit-latency-us = <915>;
260 min-residency-us = <1617>;
261 local-timer-stop;
262 };
263
264 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
265 compatible = "arm,idle-state";
266 idle-state-name = "big-rail-power-collapse";
267 arm,psci-suspend-param = <0x40000004>;
268 entry-latency-us = <526>;
269 exit-latency-us = <1854>;
270 min-residency-us = <2380>;
271 local-timer-stop;
272 };
273 };
274
275 domain-idle-states {
276 CLUSTER_SLEEP_0: cluster-sleep-0 {
277 compatible = "domain-idle-state";
278 arm,psci-suspend-param = <0x4100c244>;
279 entry-latency-us = <3263>;
280 exit-latency-us = <6562>;
281 min-residency-us = <9825>;
282 };
283 };
284 };
285
286 firmware {
287 scm {
288 compatible = "qcom,scm-sdm670", "qcom,scm";
289 };
290 };
291
292 memory@80000000 {
293 device_type = "memory";
294 /* We expect the bootloader to fill in the size */
295 reg = <0x0 0x80000000 0x0 0x0>;
296 };
297
298 cpu0_opp_table: opp-table-cpu0 {
299 compatible = "operating-points-v2";
300 opp-shared;
301
302 cpu0_opp1: opp-300000000 {
303 opp-hz = /bits/ 64 <300000000>;
304 opp-peak-kBps = <400000 4800000>;
305 };
306
307 cpu0_opp2: opp-576000000 {
308 opp-hz = /bits/ 64 <576000000>;
309 opp-peak-kBps = <400000 4800000>;
310 };
311
312 cpu0_opp3: opp-748800000 {
313 opp-hz = /bits/ 64 <748800000>;
314 opp-peak-kBps = <1200000 4800000>;
315 };
316
317 cpu0_opp4: opp-998400000 {
318 opp-hz = /bits/ 64 <998400000>;
319 opp-peak-kBps = <1804000 8908800>;
320 };
321
322 cpu0_opp5: opp-1209600000 {
323 opp-hz = /bits/ 64 <1209600000>;
324 opp-peak-kBps = <2188000 8908800>;
325 };
326
327 cpu0_opp6: opp-1324800000 {
328 opp-hz = /bits/ 64 <1324800000>;
329 opp-peak-kBps = <2188000 13516800>;
330 };
331
332 cpu0_opp7: opp-1516800000 {
333 opp-hz = /bits/ 64 <1516800000>;
334 opp-peak-kBps = <3072000 15052800>;
335 };
336
337 cpu0_opp8: opp-1612800000 {
338 opp-hz = /bits/ 64 <1612800000>;
339 opp-peak-kBps = <3072000 22118400>;
340 };
341
342 cpu0_opp9: opp-1708800000 {
343 opp-hz = /bits/ 64 <1708800000>;
344 opp-peak-kBps = <4068000 23040000>;
345 };
346 };
347
348 cpu6_opp_table: opp-table-cpu6 {
349 compatible = "operating-points-v2";
350 opp-shared;
351
352 cpu6_opp1: opp-300000000 {
353 opp-hz = /bits/ 64 <300000000>;
354 opp-peak-kBps = <400000 4800000>;
355 };
356
357 cpu6_opp2: opp-652800000 {
358 opp-hz = /bits/ 64 <652800000>;
359 opp-peak-kBps = <400000 4800000>;
360 };
361
362 cpu6_opp3: opp-825600000 {
363 opp-hz = /bits/ 64 <825600000>;
364 opp-peak-kBps = <1200000 4800000>;
365 };
366
367 cpu6_opp4: opp-979200000 {
368 opp-hz = /bits/ 64 <979200000>;
369 opp-peak-kBps = <1200000 4800000>;
370 };
371
372 cpu6_opp5: opp-1132800000 {
373 opp-hz = /bits/ 64 <1132800000>;
374 opp-peak-kBps = <2188000 8908800>;
375 };
376
377 cpu6_opp6: opp-1363200000 {
378 opp-hz = /bits/ 64 <1363200000>;
379 opp-peak-kBps = <4068000 12902400>;
380 };
381
382 cpu6_opp7: opp-1536000000 {
383 opp-hz = /bits/ 64 <1536000000>;
384 opp-peak-kBps = <4068000 12902400>;
385 };
386
387 cpu6_opp8: opp-1747200000 {
388 opp-hz = /bits/ 64 <1747200000>;
389 opp-peak-kBps = <4068000 15052800>;
390 };
391
392 cpu6_opp9: opp-1843200000 {
393 opp-hz = /bits/ 64 <1843200000>;
394 opp-peak-kBps = <4068000 15052800>;
395 };
396
397 cpu6_opp10: opp-1996800000 {
398 opp-hz = /bits/ 64 <1996800000>;
399 opp-peak-kBps = <6220000 19046400>;
400 };
401 };
402
403 psci {
404 compatible = "arm,psci-1.0";
405 method = "smc";
406
407 CPU_PD0: power-domain-cpu0 {
408 #power-domain-cells = <0>;
409 power-domains = <&CLUSTER_PD>;
410 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
411 };
412
413 CPU_PD1: power-domain-cpu1 {
414 #power-domain-cells = <0>;
415 power-domains = <&CLUSTER_PD>;
416 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
417 };
418
419 CPU_PD2: power-domain-cpu2 {
420 #power-domain-cells = <0>;
421 power-domains = <&CLUSTER_PD>;
422 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
423 };
424
425 CPU_PD3: power-domain-cpu3 {
426 #power-domain-cells = <0>;
427 power-domains = <&CLUSTER_PD>;
428 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
429 };
430
431 CPU_PD4: power-domain-cpu4 {
432 #power-domain-cells = <0>;
433 power-domains = <&CLUSTER_PD>;
434 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
435 };
436
437 CPU_PD5: power-domain-cpu5 {
438 #power-domain-cells = <0>;
439 power-domains = <&CLUSTER_PD>;
440 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
441 };
442
443 CPU_PD6: power-domain-cpu6 {
444 #power-domain-cells = <0>;
445 power-domains = <&CLUSTER_PD>;
446 domain-idle-states = <&BIG_CPU_SLEEP_0>;
447 };
448
449 CPU_PD7: power-domain-cpu7 {
450 #power-domain-cells = <0>;
451 power-domains = <&CLUSTER_PD>;
452 domain-idle-states = <&BIG_CPU_SLEEP_0>;
453 };
454
455 CLUSTER_PD: power-domain-cluster {
456 #power-domain-cells = <0>;
457 domain-idle-states = <&CLUSTER_SLEEP_0>;
458 };
459 };
460
461 reserved-memory {
462 #address-cells = <2>;
463 #size-cells = <2>;
464 ranges;
465
466 hyp_mem: hyp-mem@85700000 {
467 reg = <0 0x85700000 0 0x600000>;
468 no-map;
469 };
470
471 xbl_mem: xbl-mem@85e00000 {
472 reg = <0 0x85e00000 0 0x100000>;
473 no-map;
474 };
475
476 aop_mem: aop-mem@85fc0000 {
477 reg = <0 0x85fc0000 0 0x20000>;
478 no-map;
479 };
480
481 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
482 compatible = "qcom,cmd-db";
483 reg = <0 0x85fe0000 0 0x20000>;
484 no-map;
485 };
486
487 camera_mem: camera-mem@8ab00000 {
488 reg = <0 0x8ab00000 0 0x500000>;
489 no-map;
490 };
491
492 mpss_region: mpss@8b000000 {
493 reg = <0 0x8b000000 0 0x7e00000>;
494 no-map;
495 };
496
497 venus_mem: venus@92e00000 {
498 reg = <0 0x92e00000 0 0x500000>;
499 no-map;
500 };
501
502 wlan_msa_mem: wlan-msa@93300000 {
503 reg = <0 0x93300000 0 0x100000>;
504 no-map;
505 };
506
507 cdsp_mem: cdsp@93400000 {
508 reg = <0 0x93400000 0 0x800000>;
509 no-map;
510 };
511
512 mba_region: mba@93c00000 {
513 reg = <0 0x93c00000 0 0x200000>;
514 no-map;
515 };
516
517 adsp_mem: adsp@93e00000 {
518 reg = <0 0x93e00000 0 0x1e00000>;
519 no-map;
520 };
521
522 ipa_fw_mem: ipa-fw@95c00000 {
523 reg = <0 0x95c00000 0 0x10000>;
524 no-map;
525 };
526
527 ipa_gsi_mem: ipa-gsi@95c10000 {
528 reg = <0 0x95c10000 0 0x5000>;
529 no-map;
530 };
531
532 gpu_mem: gpu@95c15000 {
533 reg = <0 0x95c15000 0 0x2000>;
534 no-map;
535 };
536
537 spss_mem: spss@97b00000 {
538 reg = <0 0x97b00000 0 0x100000>;
539 no-map;
540 };
541
542 qseecom_mem: qseecom@9e400000 {
543 reg = <0 0x9e400000 0 0x1400000>;
544 no-map;
545 };
546 };
547
548 timer {
549 compatible = "arm,armv8-timer";
550 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
551 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
552 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
553 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
554 };
555
556 soc: soc@0 {
557 #address-cells = <2>;
558 #size-cells = <2>;
559 ranges = <0 0 0 0 0x10 0>;
560 dma-ranges = <0 0 0 0 0x10 0>;
561 compatible = "simple-bus";
562
563 gcc: clock-controller@100000 {
564 compatible = "qcom,gcc-sdm670";
565 reg = <0 0x00100000 0 0x1f0000>;
566 clocks = <&rpmhcc RPMH_CXO_CLK>,
567 <&rpmhcc RPMH_CXO_CLK_A>,
568 <&sleep_clk>;
569 clock-names = "bi_tcxo",
570 "bi_tcxo_ao",
571 "sleep_clk";
572 #clock-cells = <1>;
573 #reset-cells = <1>;
574 #power-domain-cells = <1>;
575 };
576
577 qfprom: qfprom@784000 {
578 compatible = "qcom,sdm670-qfprom", "qcom,qfprom";
579 reg = <0 0x00784000 0 0x1000>;
580 #address-cells = <1>;
581 #size-cells = <1>;
582
583 qusb2_hstx_trim: hstx-trim@1eb {
584 reg = <0x1eb 0x1>;
585 bits = <1 4>;
586 };
587 };
588
589 sdhc_1: mmc@7c4000 {
590 compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5";
591 reg = <0 0x007c4000 0 0x1000>,
592 <0 0x007c5000 0 0x1000>,
593 <0 0x007c8000 0 0x8000>;
594 reg-names = "hc", "cqhci", "ice";
595
596 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
598 interrupt-names = "hc_irq", "pwr_irq";
599
600 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
601 <&gcc GCC_SDCC1_APPS_CLK>,
602 <&rpmhcc RPMH_CXO_CLK>,
603 <&gcc GCC_SDCC1_ICE_CORE_CLK>,
604 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
605 clock-names = "iface", "core", "xo", "ice", "bus";
606 interconnects = <&aggre1_noc MASTER_EMMC 0 &aggre1_noc SLAVE_A1NOC_SNOC 0>,
607 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_EMMC_CFG 0>;
608 interconnect-names = "sdhc-ddr", "cpu-sdhc";
609 operating-points-v2 = <&sdhc1_opp_table>;
610
611 iommus = <&apps_smmu 0x140 0xf>;
612
613 pinctrl-names = "default", "sleep";
614 pinctrl-0 = <&sdc1_state_on>;
615 pinctrl-1 = <&sdc1_state_off>;
616 power-domains = <&rpmhpd SDM670_CX>;
617
618 bus-width = <8>;
619 non-removable;
620
621 status = "disabled";
622
623 sdhc1_opp_table: opp-table {
624 compatible = "operating-points-v2";
625
626 opp-20000000 {
627 opp-hz = /bits/ 64 <20000000>;
628 required-opps = <&rpmhpd_opp_min_svs>;
629 opp-peak-kBps = <80000 80000>;
630 opp-avg-kBps = <52286 80000>;
631 };
632
633 opp-50000000 {
634 opp-hz = /bits/ 64 <50000000>;
635 required-opps = <&rpmhpd_opp_low_svs>;
636 opp-peak-kBps = <200000 100000>;
637 opp-avg-kBps = <130718 100000>;
638 };
639
640 opp-100000000 {
641 opp-hz = /bits/ 64 <100000000>;
642 required-opps = <&rpmhpd_opp_svs>;
643 opp-peak-kBps = <200000 130000>;
644 opp-avg-kBps = <130718 130000>;
645 };
646
647 opp-384000000 {
648 opp-hz = /bits/ 64 <384000000>;
649 required-opps = <&rpmhpd_opp_nom>;
650 opp-peak-kBps = <4096000 4096000>;
651 opp-avg-kBps = <1338562 1338562>;
652 };
653 };
654 };
655
656 gpi_dma0: dma-controller@800000 {
657 #dma-cells = <3>;
658 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
659 reg = <0 0x00800000 0 0x60000>;
660 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
668 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
669 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
670 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
671 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
673 dma-channels = <13>;
674 dma-channel-mask = <0xfa>;
675 iommus = <&apps_smmu 0x16 0x0>;
676 status = "disabled";
677 };
678
679 qupv3_id_0: geniqup@8c0000 {
680 compatible = "qcom,geni-se-qup";
681 reg = <0 0x008c0000 0 0x6000>;
682 clock-names = "m-ahb", "s-ahb";
683 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
684 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
685 iommus = <&apps_smmu 0x3 0x0>;
686 #address-cells = <2>;
687 #size-cells = <2>;
688 ranges;
689 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>;
690 interconnect-names = "qup-core";
691 status = "disabled";
692
693 i2c0: i2c@880000 {
694 compatible = "qcom,geni-i2c";
695 reg = <0 0x00880000 0 0x4000>;
696 clock-names = "se";
697 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
698 pinctrl-names = "default";
699 pinctrl-0 = <&qup_i2c0_default>;
700 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
701 #address-cells = <1>;
702 #size-cells = <0>;
703 power-domains = <&rpmhpd SDM670_CX>;
704 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
705 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
706 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
707 interconnect-names = "qup-core", "qup-config", "qup-memory";
708 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
709 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
710 dma-names = "tx", "rx";
711 status = "disabled";
712 };
713
714 i2c1: i2c@884000 {
715 compatible = "qcom,geni-i2c";
716 reg = <0 0x00884000 0 0x4000>;
717 clock-names = "se";
718 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
719 pinctrl-names = "default";
720 pinctrl-0 = <&qup_i2c1_default>;
721 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
722 #address-cells = <1>;
723 #size-cells = <0>;
724 power-domains = <&rpmhpd SDM670_CX>;
725 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
726 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
727 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
728 interconnect-names = "qup-core", "qup-config", "qup-memory";
729 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
730 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
731 dma-names = "tx", "rx";
732 status = "disabled";
733 };
734
735 i2c2: i2c@888000 {
736 compatible = "qcom,geni-i2c";
737 reg = <0 0x00888000 0 0x4000>;
738 clock-names = "se";
739 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
740 pinctrl-names = "default";
741 pinctrl-0 = <&qup_i2c2_default>;
742 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
743 #address-cells = <1>;
744 #size-cells = <0>;
745 power-domains = <&rpmhpd SDM670_CX>;
746 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
747 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
748 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
749 interconnect-names = "qup-core", "qup-config", "qup-memory";
750 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
751 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
752 dma-names = "tx", "rx";
753 status = "disabled";
754 };
755
756 i2c3: i2c@88c000 {
757 compatible = "qcom,geni-i2c";
758 reg = <0 0x0088c000 0 0x4000>;
759 clock-names = "se";
760 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
761 pinctrl-names = "default";
762 pinctrl-0 = <&qup_i2c3_default>;
763 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
764 #address-cells = <1>;
765 #size-cells = <0>;
766 power-domains = <&rpmhpd SDM670_CX>;
767 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
768 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
769 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
770 interconnect-names = "qup-core", "qup-config", "qup-memory";
771 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
772 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
773 dma-names = "tx", "rx";
774 status = "disabled";
775 };
776
777 i2c4: i2c@890000 {
778 compatible = "qcom,geni-i2c";
779 reg = <0 0x00890000 0 0x4000>;
780 clock-names = "se";
781 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
782 pinctrl-names = "default";
783 pinctrl-0 = <&qup_i2c4_default>;
784 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
785 #address-cells = <1>;
786 #size-cells = <0>;
787 power-domains = <&rpmhpd SDM670_CX>;
788 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
789 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
790 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
791 interconnect-names = "qup-core", "qup-config", "qup-memory";
792 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
793 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
794 dma-names = "tx", "rx";
795 status = "disabled";
796 };
797
798 i2c5: i2c@894000 {
799 compatible = "qcom,geni-i2c";
800 reg = <0 0x00894000 0 0x4000>;
801 clock-names = "se";
802 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
803 pinctrl-names = "default";
804 pinctrl-0 = <&qup_i2c5_default>;
805 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
806 #address-cells = <1>;
807 #size-cells = <0>;
808 power-domains = <&rpmhpd SDM670_CX>;
809 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
810 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
811 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
812 interconnect-names = "qup-core", "qup-config", "qup-memory";
813 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
814 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
815 dma-names = "tx", "rx";
816 status = "disabled";
817 };
818
819 i2c6: i2c@898000 {
820 compatible = "qcom,geni-i2c";
821 reg = <0 0x00898000 0 0x4000>;
822 clock-names = "se";
823 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
824 pinctrl-names = "default";
825 pinctrl-0 = <&qup_i2c6_default>;
826 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
827 #address-cells = <1>;
828 #size-cells = <0>;
829 power-domains = <&rpmhpd SDM670_CX>;
830 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
831 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
832 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
833 interconnect-names = "qup-core", "qup-config", "qup-memory";
834 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
835 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
836 dma-names = "tx", "rx";
837 status = "disabled";
838 };
839
840 i2c7: i2c@89c000 {
841 compatible = "qcom,geni-i2c";
842 reg = <0 0x0089c000 0 0x4000>;
843 clock-names = "se";
844 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
845 pinctrl-names = "default";
846 pinctrl-0 = <&qup_i2c7_default>;
847 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
848 #address-cells = <1>;
849 #size-cells = <0>;
850 power-domains = <&rpmhpd SDM670_CX>;
851 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
852 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
853 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
854 interconnect-names = "qup-core", "qup-config", "qup-memory";
855 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
856 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
857 dma-names = "tx", "rx";
858 status = "disabled";
859 };
860 };
861
862 gpi_dma1: dma-controller@a00000 {
863 #dma-cells = <3>;
864 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
865 reg = <0 0x00a00000 0 0x60000>;
866 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
867 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
868 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
869 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
870 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
871 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
872 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
873 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
874 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
875 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
876 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
877 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
879 dma-channels = <13>;
880 dma-channel-mask = <0xfa>;
881 iommus = <&apps_smmu 0x6d6 0x0>;
882 status = "disabled";
883 };
884
885 qupv3_id_1: geniqup@ac0000 {
886 compatible = "qcom,geni-se-qup";
887 reg = <0 0x00ac0000 0 0x6000>;
888 clock-names = "m-ahb", "s-ahb";
889 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
890 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
891 iommus = <&apps_smmu 0x6c3 0x0>;
892 #address-cells = <2>;
893 #size-cells = <2>;
894 ranges;
895 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>;
896 interconnect-names = "qup-core";
897 status = "disabled";
898
899 i2c8: i2c@a80000 {
900 compatible = "qcom,geni-i2c";
901 reg = <0 0x00a80000 0 0x4000>;
902 clock-names = "se";
903 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
904 pinctrl-names = "default";
905 pinctrl-0 = <&qup_i2c8_default>;
906 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
907 #address-cells = <1>;
908 #size-cells = <0>;
909 power-domains = <&rpmhpd SDM670_CX>;
910 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
911 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
912 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
913 interconnect-names = "qup-core", "qup-config", "qup-memory";
914 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
915 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
916 dma-names = "tx", "rx";
917 status = "disabled";
918 };
919
920 i2c9: i2c@a84000 {
921 compatible = "qcom,geni-i2c";
922 reg = <0 0x00a84000 0 0x4000>;
923 clock-names = "se";
924 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
925 pinctrl-names = "default";
926 pinctrl-0 = <&qup_i2c9_default>;
927 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
928 #address-cells = <1>;
929 #size-cells = <0>;
930 power-domains = <&rpmhpd SDM670_CX>;
931 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
932 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
933 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
934 interconnect-names = "qup-core", "qup-config", "qup-memory";
935 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
936 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
937 dma-names = "tx", "rx";
938 status = "disabled";
939 };
940
941 i2c10: i2c@a88000 {
942 compatible = "qcom,geni-i2c";
943 reg = <0 0x00a88000 0 0x4000>;
944 clock-names = "se";
945 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
946 pinctrl-names = "default";
947 pinctrl-0 = <&qup_i2c10_default>;
948 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
949 #address-cells = <1>;
950 #size-cells = <0>;
951 power-domains = <&rpmhpd SDM670_CX>;
952 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
953 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
954 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
955 interconnect-names = "qup-core", "qup-config", "qup-memory";
956 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
957 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
958 dma-names = "tx", "rx";
959 status = "disabled";
960 };
961
962 i2c11: i2c@a8c000 {
963 compatible = "qcom,geni-i2c";
964 reg = <0 0x00a8c000 0 0x4000>;
965 clock-names = "se";
966 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
967 pinctrl-names = "default";
968 pinctrl-0 = <&qup_i2c11_default>;
969 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
970 #address-cells = <1>;
971 #size-cells = <0>;
972 power-domains = <&rpmhpd SDM670_CX>;
973 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
974 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
975 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
976 interconnect-names = "qup-core", "qup-config", "qup-memory";
977 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
978 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
979 dma-names = "tx", "rx";
980 status = "disabled";
981 };
982
983 i2c12: i2c@a90000 {
984 compatible = "qcom,geni-i2c";
985 reg = <0 0x00a90000 0 0x4000>;
986 clock-names = "se";
987 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
988 pinctrl-names = "default";
989 pinctrl-0 = <&qup_i2c12_default>;
990 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
991 #address-cells = <1>;
992 #size-cells = <0>;
993 power-domains = <&rpmhpd SDM670_CX>;
994 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
995 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
996 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
997 interconnect-names = "qup-core", "qup-config", "qup-memory";
998 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
999 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1000 dma-names = "tx", "rx";
1001 status = "disabled";
1002 };
1003
1004 i2c13: i2c@a94000 {
1005 compatible = "qcom,geni-i2c";
1006 reg = <0 0x00a94000 0 0x4000>;
1007 clock-names = "se";
1008 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1009 pinctrl-names = "default";
1010 pinctrl-0 = <&qup_i2c13_default>;
1011 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1012 #address-cells = <1>;
1013 #size-cells = <0>;
1014 power-domains = <&rpmhpd SDM670_CX>;
1015 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1016 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1017 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1018 interconnect-names = "qup-core", "qup-config", "qup-memory";
1019 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1020 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1021 dma-names = "tx", "rx";
1022 status = "disabled";
1023 };
1024
1025 i2c14: i2c@a98000 {
1026 compatible = "qcom,geni-i2c";
1027 reg = <0 0x00a98000 0 0x4000>;
1028 clock-names = "se";
1029 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1030 pinctrl-names = "default";
1031 pinctrl-0 = <&qup_i2c14_default>;
1032 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1033 #address-cells = <1>;
1034 #size-cells = <0>;
1035 power-domains = <&rpmhpd SDM670_CX>;
1036 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1037 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1038 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1039 interconnect-names = "qup-core", "qup-config", "qup-memory";
1040 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1041 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1042 dma-names = "tx", "rx";
1043 status = "disabled";
1044 };
1045
1046 i2c15: i2c@a9c000 {
1047 compatible = "qcom,geni-i2c";
1048 reg = <0 0x00a9c000 0 0x4000>;
1049 clock-names = "se";
1050 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1051 pinctrl-names = "default";
1052 pinctrl-0 = <&qup_i2c15_default>;
1053 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1054 #address-cells = <1>;
1055 #size-cells = <0>;
1056 power-domains = <&rpmhpd SDM670_CX>;
1057 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1058 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1059 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1060 interconnect-names = "qup-core", "qup-config", "qup-memory";
1061 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1062 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
1063 dma-names = "tx", "rx";
1064 status = "disabled";
1065 };
1066 };
1067
1068 mem_noc: interconnect@1380000 {
1069 compatible = "qcom,sdm670-mem-noc";
1070 reg = <0 0x01380000 0 0x27200>;
1071 #interconnect-cells = <2>;
1072 qcom,bcm-voters = <&apps_bcm_voter>;
1073 };
1074
1075 dc_noc: interconnect@14e0000 {
1076 compatible = "qcom,sdm670-dc-noc";
1077 reg = <0 0x014e0000 0 0x400>;
1078 #interconnect-cells = <2>;
1079 qcom,bcm-voters = <&apps_bcm_voter>;
1080 };
1081
1082 config_noc: interconnect@1500000 {
1083 compatible = "qcom,sdm670-config-noc";
1084 reg = <0 0x01500000 0 0x5080>;
1085 #interconnect-cells = <2>;
1086 qcom,bcm-voters = <&apps_bcm_voter>;
1087 };
1088
1089 system_noc: interconnect@1620000 {
1090 compatible = "qcom,sdm670-system-noc";
1091 reg = <0 0x01620000 0 0x18080>;
1092 #interconnect-cells = <2>;
1093 qcom,bcm-voters = <&apps_bcm_voter>;
1094 };
1095
1096 aggre1_noc: interconnect@16e0000 {
1097 compatible = "qcom,sdm670-aggre1-noc";
1098 reg = <0 0x016e0000 0 0x15080>;
1099 #interconnect-cells = <2>;
1100 qcom,bcm-voters = <&apps_bcm_voter>;
1101 };
1102
1103 aggre2_noc: interconnect@1700000 {
1104 compatible = "qcom,sdm670-aggre2-noc";
1105 reg = <0 0x01700000 0 0x1f300>;
1106 #interconnect-cells = <2>;
1107 qcom,bcm-voters = <&apps_bcm_voter>;
1108 };
1109
1110 mmss_noc: interconnect@1740000 {
1111 compatible = "qcom,sdm670-mmss-noc";
1112 reg = <0 0x01740000 0 0x1c100>;
1113 #interconnect-cells = <2>;
1114 qcom,bcm-voters = <&apps_bcm_voter>;
1115 };
1116
1117 tlmm: pinctrl@3400000 {
1118 compatible = "qcom,sdm670-tlmm";
1119 reg = <0 0x03400000 0 0xc00000>;
1120 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1121 gpio-controller;
1122 #gpio-cells = <2>;
1123 interrupt-controller;
1124 #interrupt-cells = <2>;
1125 gpio-ranges = <&tlmm 0 0 151>;
1126 wakeup-parent = <&pdc>;
1127
1128 qup_i2c0_default: qup-i2c0-default-state {
1129 pins = "gpio0", "gpio1";
1130 function = "qup0";
1131 };
1132
1133 qup_i2c1_default: qup-i2c1-default-state {
1134 pins = "gpio17", "gpio18";
1135 function = "qup1";
1136 };
1137
1138 qup_i2c2_default: qup-i2c2-default-state {
1139 pins = "gpio27", "gpio28";
1140 function = "qup2";
1141 };
1142
1143 qup_i2c3_default: qup-i2c3-default-state {
1144 pins = "gpio41", "gpio42";
1145 function = "qup3";
1146 };
1147
1148 qup_i2c4_default: qup-i2c4-default-state {
1149 pins = "gpio89", "gpio90";
1150 function = "qup4";
1151 };
1152
1153 qup_i2c5_default: qup-i2c5-default-state {
1154 pins = "gpio85", "gpio86";
1155 function = "qup5";
1156 };
1157
1158 qup_i2c6_default: qup-i2c6-default-state {
1159 pins = "gpio45", "gpio46";
1160 function = "qup6";
1161 };
1162
1163 qup_i2c7_default: qup-i2c7-default-state {
1164 pins = "gpio93", "gpio94";
1165 function = "qup7";
1166 };
1167
1168 qup_i2c8_default: qup-i2c8-default-state {
1169 pins = "gpio65", "gpio66";
1170 function = "qup8";
1171 };
1172
1173 qup_i2c9_default: qup-i2c9-default-state {
1174 pins = "gpio6", "gpio7";
1175 function = "qup9";
1176 };
1177
1178 qup_i2c10_default: qup-i2c10-default-state {
1179 pins = "gpio55", "gpio56";
1180 function = "qup10";
1181 };
1182
1183 qup_i2c11_default: qup-i2c11-default-state {
1184 pins = "gpio31", "gpio32";
1185 function = "qup11";
1186 };
1187
1188 qup_i2c12_default: qup-i2c12-default-state {
1189 pins = "gpio49", "gpio50";
1190 function = "qup12";
1191 };
1192
1193 qup_i2c13_default: qup-i2c13-default-state {
1194 pins = "gpio105", "gpio106";
1195 function = "qup13";
1196 };
1197
1198 qup_i2c14_default: qup-i2c14-default-state {
1199 pins = "gpio33", "gpio34";
1200 function = "qup14";
1201 };
1202
1203 qup_i2c15_default: qup-i2c15-default-state {
1204 pins = "gpio81", "gpio82";
1205 function = "qup15";
1206 };
1207
1208 sdc1_state_on: sdc1-on-state {
1209 clk-pins {
1210 pins = "sdc1_clk";
1211 bias-disable;
1212 drive-strength = <16>;
1213 };
1214
1215 cmd-pins {
1216 pins = "sdc1_cmd";
1217 bias-pull-up;
1218 drive-strength = <10>;
1219 };
1220
1221 data-pins {
1222 pins = "sdc1_data";
1223 bias-pull-up;
1224 drive-strength = <10>;
1225 };
1226
1227 rclk-pins {
1228 pins = "sdc1_rclk";
1229 bias-pull-down;
1230 };
1231 };
1232
1233 sdc1_state_off: sdc1-off-state {
1234 clk-pins {
1235 pins = "sdc1_clk";
1236 bias-disable;
1237 drive-strength = <2>;
1238 };
1239
1240 cmd-pins {
1241 pins = "sdc1_cmd";
1242 bias-pull-up;
1243 drive-strength = <2>;
1244 };
1245
1246 data-pins {
1247 pins = "sdc1_data";
1248 bias-pull-up;
1249 drive-strength = <2>;
1250 };
1251
1252 rclk-pins {
1253 pins = "sdc1_rclk";
1254 bias-pull-down;
1255 };
1256 };
1257 };
1258
1259 usb_1_hsphy: phy@88e2000 {
1260 compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy";
1261 reg = <0 0x088e2000 0 0x400>;
1262 #phy-cells = <0>;
1263
1264 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1265 <&rpmhcc RPMH_CXO_CLK>;
1266 clock-names = "cfg_ahb", "ref";
1267
1268 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1269
1270 nvmem-cells = <&qusb2_hstx_trim>;
1271
1272 status = "disabled";
1273 };
1274
1275 usb_1: usb@a6f8800 {
1276 compatible = "qcom,sdm670-dwc3", "qcom,dwc3";
1277 reg = <0 0x0a6f8800 0 0x400>;
1278 #address-cells = <2>;
1279 #size-cells = <2>;
1280 ranges;
1281 dma-ranges;
1282
1283 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1284 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1285 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1286 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1287 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
1288 clock-names = "cfg_noc",
1289 "core",
1290 "iface",
1291 "sleep",
1292 "mock_utmi";
1293
1294 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1295 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1296 assigned-clock-rates = <19200000>, <150000000>;
1297
1298 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1299 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
1300 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
1301 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
1302 interrupt-names = "hs_phy_irq", "ss_phy_irq",
1303 "dm_hs_phy_irq", "dp_hs_phy_irq";
1304
1305 power-domains = <&gcc USB30_PRIM_GDSC>;
1306
1307 resets = <&gcc GCC_USB30_PRIM_BCR>;
1308
1309 interconnects = <&aggre2_noc MASTER_USB3 0 &mem_noc SLAVE_EBI_CH0 0>,
1310 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
1311 interconnect-names = "usb-ddr", "apps-usb";
1312
1313 status = "disabled";
1314
1315 usb_1_dwc3: usb@a600000 {
1316 compatible = "snps,dwc3";
1317 reg = <0 0x0a600000 0 0xcd00>;
1318 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1319 iommus = <&apps_smmu 0x740 0>;
1320 snps,dis_u2_susphy_quirk;
1321 snps,dis_enblslpm_quirk;
1322 phys = <&usb_1_hsphy>;
1323 phy-names = "usb2-phy";
1324 };
1325 };
1326
1327 pdc: interrupt-controller@b220000 {
1328 compatible = "qcom,sdm670-pdc", "qcom,pdc";
1329 reg = <0 0x0b220000 0 0x30000>;
1330 qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>,
1331 <54 534 24>, <79 559 15>, <94 609 15>,
1332 <115 630 7>;
1333 #interrupt-cells = <2>;
1334 interrupt-parent = <&intc>;
1335 interrupt-controller;
1336 };
1337
1338 spmi_bus: spmi@c440000 {
1339 compatible = "qcom,spmi-pmic-arb";
1340 reg = <0 0x0c440000 0 0x1100>,
1341 <0 0x0c600000 0 0x2000000>,
1342 <0 0x0e600000 0 0x100000>,
1343 <0 0x0e700000 0 0xa0000>,
1344 <0 0x0c40a000 0 0x26000>;
1345 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1346 interrupt-names = "periph_irq";
1347 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
1348 qcom,ee = <0>;
1349 qcom,channel = <0>;
1350 #address-cells = <2>;
1351 #size-cells = <0>;
1352 interrupt-controller;
1353 #interrupt-cells = <4>;
1354 };
1355
1356 apps_smmu: iommu@15000000 {
1357 compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1358 reg = <0 0x15000000 0 0x80000>;
1359 #iommu-cells = <2>;
1360 #global-interrupts = <1>;
1361 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1362 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1363 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1365 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1378 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1379 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1380 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1383 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1384 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1385 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1386 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1387 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1388 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1389 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1390 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1391 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1392 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1393 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1394 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1395 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1396 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1397 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1398 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1399 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1400 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1401 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1402 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1403 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1404 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1405 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1406 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1407 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1408 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1409 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1410 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1411 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1412 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1413 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1414 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1415 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1416 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1417 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1418 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1419 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1420 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1421 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1422 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1423 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1424 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1425 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1426 };
1427
1428 gladiator_noc: interconnect@17900000 {
1429 compatible = "qcom,sdm670-gladiator-noc";
1430 reg = <0 0x17900000 0 0xd080>;
1431 #interconnect-cells = <2>;
1432 qcom,bcm-voters = <&apps_bcm_voter>;
1433 };
1434
1435 apps_rsc: rsc@179c0000 {
1436 compatible = "qcom,rpmh-rsc";
1437 reg = <0 0x179c0000 0 0x10000>,
1438 <0 0x179d0000 0 0x10000>,
1439 <0 0x179e0000 0 0x10000>;
1440 reg-names = "drv-0", "drv-1", "drv-2";
1441 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1442 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1443 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1444 label = "apps_rsc";
1445 qcom,tcs-offset = <0xd00>;
1446 qcom,drv-id = <2>;
1447 qcom,tcs-config = <ACTIVE_TCS 2>,
1448 <SLEEP_TCS 3>,
1449 <WAKE_TCS 3>,
1450 <CONTROL_TCS 1>;
1451 power-domains = <&CLUSTER_PD>;
1452
1453 apps_bcm_voter: bcm-voter {
1454 compatible = "qcom,bcm-voter";
1455 };
1456
1457 rpmhcc: clock-controller {
1458 compatible = "qcom,sdm670-rpmh-clk";
1459 #clock-cells = <1>;
1460 clock-names = "xo";
1461 clocks = <&xo_board>;
1462 };
1463
1464 rpmhpd: power-controller {
1465 compatible = "qcom,sdm670-rpmhpd";
1466 #power-domain-cells = <1>;
1467 operating-points-v2 = <&rpmhpd_opp_table>;
1468
1469 rpmhpd_opp_table: opp-table {
1470 compatible = "operating-points-v2";
1471
1472 rpmhpd_opp_ret: opp1 {
1473 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1474 };
1475
1476 rpmhpd_opp_min_svs: opp2 {
1477 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1478 };
1479
1480 rpmhpd_opp_low_svs: opp3 {
1481 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1482 };
1483
1484 rpmhpd_opp_svs: opp4 {
1485 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1486 };
1487
1488 rpmhpd_opp_svs_l1: opp5 {
1489 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1490 };
1491
1492 rpmhpd_opp_nom: opp6 {
1493 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1494 };
1495
1496 rpmhpd_opp_nom_l1: opp7 {
1497 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1498 };
1499
1500 rpmhpd_opp_nom_l2: opp8 {
1501 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1502 };
1503
1504 rpmhpd_opp_turbo: opp9 {
1505 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1506 };
1507
1508 rpmhpd_opp_turbo_l1: opp10 {
1509 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1510 };
1511 };
1512 };
1513 };
1514
1515 intc: interrupt-controller@17a00000 {
1516 compatible = "arm,gic-v3";
1517 reg = <0 0x17a00000 0 0x10000>, /* GICD */
1518 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
1519 interrupt-controller;
1520 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1521 #interrupt-cells = <3>;
1522 };
1523
1524 osm_l3: interconnect@17d41000 {
1525 compatible = "qcom,sdm670-osm-l3", "qcom,osm-l3";
1526 reg = <0 0x17d41000 0 0x1400>;
1527
1528 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
1529 clock-names = "xo", "alternate";
1530
1531 #interconnect-cells = <1>;
1532 };
1533
1534 cpufreq_hw: cpufreq@17d43000 {
1535 compatible = "qcom,cpufreq-hw";
1536 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
1537 reg-names = "freq-domain0", "freq-domain1";
1538
1539 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
1540 clock-names = "xo", "alternate";
1541
1542 #freq-domain-cells = <1>;
1543 };
1544 };
1545 };
"Das U-Boot" Source Tree