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[thirdparty/u-boot.git] / src / arm64 / renesas / r8a774e1.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for the r8a774e1 SoC
4 *
5 * Copyright (C) 2020 Renesas Electronics Corp.
6 */
7
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
11 #include <dt-bindings/power/r8a774e1-sysc.h>
12
13 / {
14 compatible = "renesas,r8a774e1";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 /*
19 * The external audio clocks are configured as 0 Hz fixed frequency
20 * clocks by default.
21 * Boards that provide audio clocks should override them.
22 */
23 audio_clk_a: audio_clk_a {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <0>;
27 };
28
29 audio_clk_b: audio_clk_b {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <0>;
33 };
34
35 audio_clk_c: audio_clk_c {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <0>;
39 };
40
41 /* External CAN clock - to be overridden by boards that provide it */
42 can_clk: can {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <0>;
46 };
47
48 cluster0_opp: opp-table-0 {
49 compatible = "operating-points-v2";
50 opp-shared;
51
52 opp-500000000 {
53 opp-hz = /bits/ 64 <500000000>;
54 opp-microvolt = <820000>;
55 clock-latency-ns = <300000>;
56 };
57 opp-1000000000 {
58 opp-hz = /bits/ 64 <1000000000>;
59 opp-microvolt = <820000>;
60 clock-latency-ns = <300000>;
61 };
62 opp-1500000000 {
63 opp-hz = /bits/ 64 <1500000000>;
64 opp-microvolt = <820000>;
65 clock-latency-ns = <300000>;
66 opp-suspend;
67 };
68 };
69
70 cluster1_opp: opp-table-1 {
71 compatible = "operating-points-v2";
72 opp-shared;
73
74 opp-800000000 {
75 opp-hz = /bits/ 64 <800000000>;
76 opp-microvolt = <820000>;
77 clock-latency-ns = <300000>;
78 };
79 opp-1000000000 {
80 opp-hz = /bits/ 64 <1000000000>;
81 opp-microvolt = <820000>;
82 clock-latency-ns = <300000>;
83 };
84 opp-1200000000 {
85 opp-hz = /bits/ 64 <1200000000>;
86 opp-microvolt = <820000>;
87 clock-latency-ns = <300000>;
88 };
89 };
90
91 cpus {
92 #address-cells = <1>;
93 #size-cells = <0>;
94
95 cpu-map {
96 cluster0 {
97 core0 {
98 cpu = <&a57_0>;
99 };
100 core1 {
101 cpu = <&a57_1>;
102 };
103 core2 {
104 cpu = <&a57_2>;
105 };
106 core3 {
107 cpu = <&a57_3>;
108 };
109 };
110
111 cluster1 {
112 core0 {
113 cpu = <&a53_0>;
114 };
115 core1 {
116 cpu = <&a53_1>;
117 };
118 core2 {
119 cpu = <&a53_2>;
120 };
121 core3 {
122 cpu = <&a53_3>;
123 };
124 };
125 };
126
127 a57_0: cpu@0 {
128 compatible = "arm,cortex-a57";
129 reg = <0x0>;
130 device_type = "cpu";
131 power-domains = <&sysc R8A774E1_PD_CA57_CPU0>;
132 next-level-cache = <&L2_CA57>;
133 enable-method = "psci";
134 cpu-idle-states = <&CPU_SLEEP_0>;
135 dynamic-power-coefficient = <854>;
136 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
137 operating-points-v2 = <&cluster0_opp>;
138 capacity-dmips-mhz = <1024>;
139 #cooling-cells = <2>;
140 };
141
142 a57_1: cpu@1 {
143 compatible = "arm,cortex-a57";
144 reg = <0x1>;
145 device_type = "cpu";
146 power-domains = <&sysc R8A774E1_PD_CA57_CPU1>;
147 next-level-cache = <&L2_CA57>;
148 enable-method = "psci";
149 cpu-idle-states = <&CPU_SLEEP_0>;
150 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
151 operating-points-v2 = <&cluster0_opp>;
152 capacity-dmips-mhz = <1024>;
153 #cooling-cells = <2>;
154 };
155
156 a57_2: cpu@2 {
157 compatible = "arm,cortex-a57";
158 reg = <0x2>;
159 device_type = "cpu";
160 power-domains = <&sysc R8A774E1_PD_CA57_CPU2>;
161 next-level-cache = <&L2_CA57>;
162 enable-method = "psci";
163 cpu-idle-states = <&CPU_SLEEP_0>;
164 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
165 operating-points-v2 = <&cluster0_opp>;
166 capacity-dmips-mhz = <1024>;
167 #cooling-cells = <2>;
168 };
169
170 a57_3: cpu@3 {
171 compatible = "arm,cortex-a57";
172 reg = <0x3>;
173 device_type = "cpu";
174 power-domains = <&sysc R8A774E1_PD_CA57_CPU3>;
175 next-level-cache = <&L2_CA57>;
176 enable-method = "psci";
177 cpu-idle-states = <&CPU_SLEEP_0>;
178 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
179 operating-points-v2 = <&cluster0_opp>;
180 capacity-dmips-mhz = <1024>;
181 #cooling-cells = <2>;
182 };
183
184 a53_0: cpu@100 {
185 compatible = "arm,cortex-a53";
186 reg = <0x100>;
187 device_type = "cpu";
188 power-domains = <&sysc R8A774E1_PD_CA53_CPU0>;
189 next-level-cache = <&L2_CA53>;
190 enable-method = "psci";
191 cpu-idle-states = <&CPU_SLEEP_1>;
192 #cooling-cells = <2>;
193 dynamic-power-coefficient = <277>;
194 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
195 operating-points-v2 = <&cluster1_opp>;
196 capacity-dmips-mhz = <535>;
197 };
198
199 a53_1: cpu@101 {
200 compatible = "arm,cortex-a53";
201 reg = <0x101>;
202 device_type = "cpu";
203 power-domains = <&sysc R8A774E1_PD_CA53_CPU1>;
204 next-level-cache = <&L2_CA53>;
205 enable-method = "psci";
206 cpu-idle-states = <&CPU_SLEEP_1>;
207 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
208 operating-points-v2 = <&cluster1_opp>;
209 capacity-dmips-mhz = <535>;
210 };
211
212 a53_2: cpu@102 {
213 compatible = "arm,cortex-a53";
214 reg = <0x102>;
215 device_type = "cpu";
216 power-domains = <&sysc R8A774E1_PD_CA53_CPU2>;
217 next-level-cache = <&L2_CA53>;
218 enable-method = "psci";
219 cpu-idle-states = <&CPU_SLEEP_1>;
220 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
221 operating-points-v2 = <&cluster1_opp>;
222 capacity-dmips-mhz = <535>;
223 };
224
225 a53_3: cpu@103 {
226 compatible = "arm,cortex-a53";
227 reg = <0x103>;
228 device_type = "cpu";
229 power-domains = <&sysc R8A774E1_PD_CA53_CPU3>;
230 next-level-cache = <&L2_CA53>;
231 enable-method = "psci";
232 cpu-idle-states = <&CPU_SLEEP_1>;
233 clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
234 operating-points-v2 = <&cluster1_opp>;
235 capacity-dmips-mhz = <535>;
236 };
237
238 L2_CA57: cache-controller-0 {
239 compatible = "cache";
240 power-domains = <&sysc R8A774E1_PD_CA57_SCU>;
241 cache-unified;
242 cache-level = <2>;
243 };
244
245 L2_CA53: cache-controller-1 {
246 compatible = "cache";
247 power-domains = <&sysc R8A774E1_PD_CA53_SCU>;
248 cache-unified;
249 cache-level = <2>;
250 };
251
252 idle-states {
253 entry-method = "psci";
254
255 CPU_SLEEP_0: cpu-sleep-0 {
256 compatible = "arm,idle-state";
257 arm,psci-suspend-param = <0x0010000>;
258 local-timer-stop;
259 entry-latency-us = <400>;
260 exit-latency-us = <500>;
261 min-residency-us = <4000>;
262 };
263
264 CPU_SLEEP_1: cpu-sleep-1 {
265 compatible = "arm,idle-state";
266 arm,psci-suspend-param = <0x0010000>;
267 local-timer-stop;
268 entry-latency-us = <700>;
269 exit-latency-us = <700>;
270 min-residency-us = <5000>;
271 };
272 };
273 };
274
275 extal_clk: extal {
276 compatible = "fixed-clock";
277 #clock-cells = <0>;
278 /* This value must be overridden by the board */
279 clock-frequency = <0>;
280 };
281
282 extalr_clk: extalr {
283 compatible = "fixed-clock";
284 #clock-cells = <0>;
285 /* This value must be overridden by the board */
286 clock-frequency = <0>;
287 };
288
289 /* External PCIe clock - can be overridden by the board */
290 pcie_bus_clk: pcie_bus {
291 compatible = "fixed-clock";
292 #clock-cells = <0>;
293 clock-frequency = <0>;
294 };
295
296 pmu_a53 {
297 compatible = "arm,cortex-a53-pmu";
298 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
299 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
300 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
301 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
302 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
303 };
304
305 pmu_a57 {
306 compatible = "arm,cortex-a57-pmu";
307 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
308 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
309 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
310 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
311 interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>;
312 };
313
314 psci {
315 compatible = "arm,psci-1.0", "arm,psci-0.2";
316 method = "smc";
317 };
318
319 /* External SCIF clock - to be overridden by boards that provide it */
320 scif_clk: scif {
321 compatible = "fixed-clock";
322 #clock-cells = <0>;
323 clock-frequency = <0>;
324 };
325
326 soc {
327 compatible = "simple-bus";
328 interrupt-parent = <&gic>;
329 #address-cells = <2>;
330 #size-cells = <2>;
331 ranges;
332
333 rwdt: watchdog@e6020000 {
334 compatible = "renesas,r8a774e1-wdt",
335 "renesas,rcar-gen3-wdt";
336 reg = <0 0xe6020000 0 0x0c>;
337 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&cpg CPG_MOD 402>;
339 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
340 resets = <&cpg 402>;
341 status = "disabled";
342 };
343
344 gpio0: gpio@e6050000 {
345 compatible = "renesas,gpio-r8a774e1",
346 "renesas,rcar-gen3-gpio";
347 reg = <0 0xe6050000 0 0x50>;
348 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
349 #gpio-cells = <2>;
350 gpio-controller;
351 gpio-ranges = <&pfc 0 0 16>;
352 #interrupt-cells = <2>;
353 interrupt-controller;
354 clocks = <&cpg CPG_MOD 912>;
355 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
356 resets = <&cpg 912>;
357 };
358
359 gpio1: gpio@e6051000 {
360 compatible = "renesas,gpio-r8a774e1",
361 "renesas,rcar-gen3-gpio";
362 reg = <0 0xe6051000 0 0x50>;
363 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
364 #gpio-cells = <2>;
365 gpio-controller;
366 gpio-ranges = <&pfc 0 32 29>;
367 #interrupt-cells = <2>;
368 interrupt-controller;
369 clocks = <&cpg CPG_MOD 911>;
370 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
371 resets = <&cpg 911>;
372 };
373
374 gpio2: gpio@e6052000 {
375 compatible = "renesas,gpio-r8a774e1",
376 "renesas,rcar-gen3-gpio";
377 reg = <0 0xe6052000 0 0x50>;
378 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
379 #gpio-cells = <2>;
380 gpio-controller;
381 gpio-ranges = <&pfc 0 64 15>;
382 #interrupt-cells = <2>;
383 interrupt-controller;
384 clocks = <&cpg CPG_MOD 910>;
385 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
386 resets = <&cpg 910>;
387 };
388
389 gpio3: gpio@e6053000 {
390 compatible = "renesas,gpio-r8a774e1",
391 "renesas,rcar-gen3-gpio";
392 reg = <0 0xe6053000 0 0x50>;
393 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
394 #gpio-cells = <2>;
395 gpio-controller;
396 gpio-ranges = <&pfc 0 96 16>;
397 #interrupt-cells = <2>;
398 interrupt-controller;
399 clocks = <&cpg CPG_MOD 909>;
400 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
401 resets = <&cpg 909>;
402 };
403
404 gpio4: gpio@e6054000 {
405 compatible = "renesas,gpio-r8a774e1",
406 "renesas,rcar-gen3-gpio";
407 reg = <0 0xe6054000 0 0x50>;
408 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
409 #gpio-cells = <2>;
410 gpio-controller;
411 gpio-ranges = <&pfc 0 128 18>;
412 #interrupt-cells = <2>;
413 interrupt-controller;
414 clocks = <&cpg CPG_MOD 908>;
415 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
416 resets = <&cpg 908>;
417 };
418
419 gpio5: gpio@e6055000 {
420 compatible = "renesas,gpio-r8a774e1",
421 "renesas,rcar-gen3-gpio";
422 reg = <0 0xe6055000 0 0x50>;
423 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
424 #gpio-cells = <2>;
425 gpio-controller;
426 gpio-ranges = <&pfc 0 160 26>;
427 #interrupt-cells = <2>;
428 interrupt-controller;
429 clocks = <&cpg CPG_MOD 907>;
430 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
431 resets = <&cpg 907>;
432 };
433
434 gpio6: gpio@e6055400 {
435 compatible = "renesas,gpio-r8a774e1",
436 "renesas,rcar-gen3-gpio";
437 reg = <0 0xe6055400 0 0x50>;
438 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
439 #gpio-cells = <2>;
440 gpio-controller;
441 gpio-ranges = <&pfc 0 192 32>;
442 #interrupt-cells = <2>;
443 interrupt-controller;
444 clocks = <&cpg CPG_MOD 906>;
445 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
446 resets = <&cpg 906>;
447 };
448
449 gpio7: gpio@e6055800 {
450 compatible = "renesas,gpio-r8a774e1",
451 "renesas,rcar-gen3-gpio";
452 reg = <0 0xe6055800 0 0x50>;
453 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
454 #gpio-cells = <2>;
455 gpio-controller;
456 gpio-ranges = <&pfc 0 224 4>;
457 #interrupt-cells = <2>;
458 interrupt-controller;
459 clocks = <&cpg CPG_MOD 905>;
460 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
461 resets = <&cpg 905>;
462 };
463
464 pfc: pinctrl@e6060000 {
465 compatible = "renesas,pfc-r8a774e1";
466 reg = <0 0xe6060000 0 0x50c>;
467 };
468
469 cmt0: timer@e60f0000 {
470 compatible = "renesas,r8a774e1-cmt0",
471 "renesas,rcar-gen3-cmt0";
472 reg = <0 0xe60f0000 0 0x1004>;
473 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&cpg CPG_MOD 303>;
476 clock-names = "fck";
477 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
478 resets = <&cpg 303>;
479 status = "disabled";
480 };
481
482 cmt1: timer@e6130000 {
483 compatible = "renesas,r8a774e1-cmt1",
484 "renesas,rcar-gen3-cmt1";
485 reg = <0 0xe6130000 0 0x1004>;
486 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
487 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
490 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&cpg CPG_MOD 302>;
495 clock-names = "fck";
496 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
497 resets = <&cpg 302>;
498 status = "disabled";
499 };
500
501 cmt2: timer@e6140000 {
502 compatible = "renesas,r8a774e1-cmt1",
503 "renesas,rcar-gen3-cmt1";
504 reg = <0 0xe6140000 0 0x1004>;
505 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&cpg CPG_MOD 301>;
514 clock-names = "fck";
515 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
516 resets = <&cpg 301>;
517 status = "disabled";
518 };
519
520 cmt3: timer@e6148000 {
521 compatible = "renesas,r8a774e1-cmt1",
522 "renesas,rcar-gen3-cmt1";
523 reg = <0 0xe6148000 0 0x1004>;
524 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&cpg CPG_MOD 300>;
533 clock-names = "fck";
534 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
535 resets = <&cpg 300>;
536 status = "disabled";
537 };
538
539 cpg: clock-controller@e6150000 {
540 compatible = "renesas,r8a774e1-cpg-mssr";
541 reg = <0 0xe6150000 0 0x1000>;
542 clocks = <&extal_clk>, <&extalr_clk>;
543 clock-names = "extal", "extalr";
544 #clock-cells = <2>;
545 #power-domain-cells = <0>;
546 #reset-cells = <1>;
547 };
548
549 rst: reset-controller@e6160000 {
550 compatible = "renesas,r8a774e1-rst";
551 reg = <0 0xe6160000 0 0x0200>;
552 };
553
554 sysc: system-controller@e6180000 {
555 compatible = "renesas,r8a774e1-sysc";
556 reg = <0 0xe6180000 0 0x0400>;
557 #power-domain-cells = <1>;
558 };
559
560 tsc: thermal@e6198000 {
561 compatible = "renesas,r8a774e1-thermal";
562 reg = <0 0xe6198000 0 0x100>,
563 <0 0xe61a0000 0 0x100>,
564 <0 0xe61a8000 0 0x100>;
565 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&cpg CPG_MOD 522>;
569 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
570 resets = <&cpg 522>;
571 #thermal-sensor-cells = <1>;
572 };
573
574 intc_ex: interrupt-controller@e61c0000 {
575 compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc";
576 #interrupt-cells = <2>;
577 interrupt-controller;
578 reg = <0 0xe61c0000 0 0x200>;
579 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
581 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&cpg CPG_MOD 407>;
586 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
587 resets = <&cpg 407>;
588 };
589
590 tmu0: timer@e61e0000 {
591 compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
592 reg = <0 0xe61e0000 0 0x30>;
593 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&cpg CPG_MOD 125>;
597 clock-names = "fck";
598 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
599 resets = <&cpg 125>;
600 status = "disabled";
601 };
602
603 tmu1: timer@e6fc0000 {
604 compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
605 reg = <0 0xe6fc0000 0 0x30>;
606 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
609 clocks = <&cpg CPG_MOD 124>;
610 clock-names = "fck";
611 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
612 resets = <&cpg 124>;
613 status = "disabled";
614 };
615
616 tmu2: timer@e6fd0000 {
617 compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
618 reg = <0 0xe6fd0000 0 0x30>;
619 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
621 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&cpg CPG_MOD 123>;
623 clock-names = "fck";
624 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
625 resets = <&cpg 123>;
626 status = "disabled";
627 };
628
629 tmu3: timer@e6fe0000 {
630 compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
631 reg = <0 0xe6fe0000 0 0x30>;
632 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
633 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
634 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&cpg CPG_MOD 122>;
636 clock-names = "fck";
637 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
638 resets = <&cpg 122>;
639 status = "disabled";
640 };
641
642 tmu4: timer@ffc00000 {
643 compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
644 reg = <0 0xffc00000 0 0x30>;
645 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&cpg CPG_MOD 121>;
649 clock-names = "fck";
650 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
651 resets = <&cpg 121>;
652 status = "disabled";
653 };
654
655 i2c0: i2c@e6500000 {
656 #address-cells = <1>;
657 #size-cells = <0>;
658 compatible = "renesas,i2c-r8a774e1",
659 "renesas,rcar-gen3-i2c";
660 reg = <0 0xe6500000 0 0x40>;
661 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
662 clocks = <&cpg CPG_MOD 931>;
663 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
664 resets = <&cpg 931>;
665 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
666 <&dmac2 0x91>, <&dmac2 0x90>;
667 dma-names = "tx", "rx", "tx", "rx";
668 i2c-scl-internal-delay-ns = <110>;
669 status = "disabled";
670 };
671
672 i2c1: i2c@e6508000 {
673 #address-cells = <1>;
674 #size-cells = <0>;
675 compatible = "renesas,i2c-r8a774e1",
676 "renesas,rcar-gen3-i2c";
677 reg = <0 0xe6508000 0 0x40>;
678 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&cpg CPG_MOD 930>;
680 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
681 resets = <&cpg 930>;
682 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
683 <&dmac2 0x93>, <&dmac2 0x92>;
684 dma-names = "tx", "rx", "tx", "rx";
685 i2c-scl-internal-delay-ns = <6>;
686 status = "disabled";
687 };
688
689 i2c2: i2c@e6510000 {
690 #address-cells = <1>;
691 #size-cells = <0>;
692 compatible = "renesas,i2c-r8a774e1",
693 "renesas,rcar-gen3-i2c";
694 reg = <0 0xe6510000 0 0x40>;
695 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
696 clocks = <&cpg CPG_MOD 929>;
697 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
698 resets = <&cpg 929>;
699 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
700 <&dmac2 0x95>, <&dmac2 0x94>;
701 dma-names = "tx", "rx", "tx", "rx";
702 i2c-scl-internal-delay-ns = <6>;
703 status = "disabled";
704 };
705
706 i2c3: i2c@e66d0000 {
707 #address-cells = <1>;
708 #size-cells = <0>;
709 compatible = "renesas,i2c-r8a774e1",
710 "renesas,rcar-gen3-i2c";
711 reg = <0 0xe66d0000 0 0x40>;
712 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&cpg CPG_MOD 928>;
714 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
715 resets = <&cpg 928>;
716 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
717 dma-names = "tx", "rx";
718 i2c-scl-internal-delay-ns = <110>;
719 status = "disabled";
720 };
721
722 i2c4: i2c@e66d8000 {
723 #address-cells = <1>;
724 #size-cells = <0>;
725 compatible = "renesas,i2c-r8a774e1",
726 "renesas,rcar-gen3-i2c";
727 reg = <0 0xe66d8000 0 0x40>;
728 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
729 clocks = <&cpg CPG_MOD 927>;
730 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
731 resets = <&cpg 927>;
732 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
733 dma-names = "tx", "rx";
734 i2c-scl-internal-delay-ns = <110>;
735 status = "disabled";
736 };
737
738 i2c5: i2c@e66e0000 {
739 #address-cells = <1>;
740 #size-cells = <0>;
741 compatible = "renesas,i2c-r8a774e1",
742 "renesas,rcar-gen3-i2c";
743 reg = <0 0xe66e0000 0 0x40>;
744 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&cpg CPG_MOD 919>;
746 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
747 resets = <&cpg 919>;
748 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
749 dma-names = "tx", "rx";
750 i2c-scl-internal-delay-ns = <110>;
751 status = "disabled";
752 };
753
754 i2c6: i2c@e66e8000 {
755 #address-cells = <1>;
756 #size-cells = <0>;
757 compatible = "renesas,i2c-r8a774e1",
758 "renesas,rcar-gen3-i2c";
759 reg = <0 0xe66e8000 0 0x40>;
760 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
761 clocks = <&cpg CPG_MOD 918>;
762 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
763 resets = <&cpg 918>;
764 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
765 dma-names = "tx", "rx";
766 i2c-scl-internal-delay-ns = <6>;
767 status = "disabled";
768 };
769
770 iic_pmic: i2c@e60b0000 {
771 #address-cells = <1>;
772 #size-cells = <0>;
773 compatible = "renesas,iic-r8a774e1",
774 "renesas,rcar-gen3-iic",
775 "renesas,rmobile-iic";
776 reg = <0 0xe60b0000 0 0x425>;
777 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&cpg CPG_MOD 926>;
779 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
780 resets = <&cpg 926>;
781 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
782 dma-names = "tx", "rx";
783 status = "disabled";
784 };
785
786 hscif0: serial@e6540000 {
787 compatible = "renesas,hscif-r8a774e1",
788 "renesas,rcar-gen3-hscif",
789 "renesas,hscif";
790 reg = <0 0xe6540000 0 0x60>;
791 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&cpg CPG_MOD 520>,
793 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
794 <&scif_clk>;
795 clock-names = "fck", "brg_int", "scif_clk";
796 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
797 <&dmac2 0x31>, <&dmac2 0x30>;
798 dma-names = "tx", "rx", "tx", "rx";
799 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
800 resets = <&cpg 520>;
801 status = "disabled";
802 };
803
804 hscif1: serial@e6550000 {
805 compatible = "renesas,hscif-r8a774e1",
806 "renesas,rcar-gen3-hscif",
807 "renesas,hscif";
808 reg = <0 0xe6550000 0 0x60>;
809 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&cpg CPG_MOD 519>,
811 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
812 <&scif_clk>;
813 clock-names = "fck", "brg_int", "scif_clk";
814 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
815 <&dmac2 0x33>, <&dmac2 0x32>;
816 dma-names = "tx", "rx", "tx", "rx";
817 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
818 resets = <&cpg 519>;
819 status = "disabled";
820 };
821
822 hscif2: serial@e6560000 {
823 compatible = "renesas,hscif-r8a774e1",
824 "renesas,rcar-gen3-hscif",
825 "renesas,hscif";
826 reg = <0 0xe6560000 0 0x60>;
827 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
828 clocks = <&cpg CPG_MOD 518>,
829 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
830 <&scif_clk>;
831 clock-names = "fck", "brg_int", "scif_clk";
832 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
833 <&dmac2 0x35>, <&dmac2 0x34>;
834 dma-names = "tx", "rx", "tx", "rx";
835 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
836 resets = <&cpg 518>;
837 status = "disabled";
838 };
839
840 hscif3: serial@e66a0000 {
841 compatible = "renesas,hscif-r8a774e1",
842 "renesas,rcar-gen3-hscif",
843 "renesas,hscif";
844 reg = <0 0xe66a0000 0 0x60>;
845 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&cpg CPG_MOD 517>,
847 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
848 <&scif_clk>;
849 clock-names = "fck", "brg_int", "scif_clk";
850 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
851 dma-names = "tx", "rx";
852 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
853 resets = <&cpg 517>;
854 status = "disabled";
855 };
856
857 hscif4: serial@e66b0000 {
858 compatible = "renesas,hscif-r8a774e1",
859 "renesas,rcar-gen3-hscif",
860 "renesas,hscif";
861 reg = <0 0xe66b0000 0 0x60>;
862 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
863 clocks = <&cpg CPG_MOD 516>,
864 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
865 <&scif_clk>;
866 clock-names = "fck", "brg_int", "scif_clk";
867 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
868 dma-names = "tx", "rx";
869 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
870 resets = <&cpg 516>;
871 status = "disabled";
872 };
873
874 hsusb: usb@e6590000 {
875 compatible = "renesas,usbhs-r8a774e1",
876 "renesas,rcar-gen3-usbhs";
877 reg = <0 0xe6590000 0 0x200>;
878 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
880 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
881 <&usb_dmac1 0>, <&usb_dmac1 1>;
882 dma-names = "ch0", "ch1", "ch2", "ch3";
883 renesas,buswait = <11>;
884 phys = <&usb2_phy0 3>;
885 phy-names = "usb";
886 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
887 resets = <&cpg 704>, <&cpg 703>;
888 status = "disabled";
889 };
890
891 usb2_clksel: clock-controller@e6590630 {
892 compatible = "renesas,r8a774e1-rcar-usb2-clock-sel",
893 "renesas,rcar-gen3-usb2-clock-sel";
894 reg = <0 0xe6590630 0 0x02>;
895 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
896 <&usb_extal_clk>, <&usb3s0_clk>;
897 clock-names = "ehci_ohci", "hs-usb-if",
898 "usb_extal", "usb_xtal";
899 #clock-cells = <0>;
900 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
901 resets = <&cpg 703>, <&cpg 704>;
902 reset-names = "ehci_ohci", "hs-usb-if";
903 status = "disabled";
904 };
905
906 usb_dmac0: dma-controller@e65a0000 {
907 compatible = "renesas,r8a774e1-usb-dmac",
908 "renesas,usb-dmac";
909 reg = <0 0xe65a0000 0 0x100>;
910 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
911 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
912 interrupt-names = "ch0", "ch1";
913 clocks = <&cpg CPG_MOD 330>;
914 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
915 resets = <&cpg 330>;
916 #dma-cells = <1>;
917 dma-channels = <2>;
918 };
919
920 usb_dmac1: dma-controller@e65b0000 {
921 compatible = "renesas,r8a774e1-usb-dmac",
922 "renesas,usb-dmac";
923 reg = <0 0xe65b0000 0 0x100>;
924 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
926 interrupt-names = "ch0", "ch1";
927 clocks = <&cpg CPG_MOD 331>;
928 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
929 resets = <&cpg 331>;
930 #dma-cells = <1>;
931 dma-channels = <2>;
932 };
933
934 usb3_phy0: usb-phy@e65ee000 {
935 compatible = "renesas,r8a774e1-usb3-phy",
936 "renesas,rcar-gen3-usb3-phy";
937 reg = <0 0xe65ee000 0 0x90>;
938 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
939 <&usb_extal_clk>;
940 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
941 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
942 resets = <&cpg 328>;
943 #phy-cells = <0>;
944 status = "disabled";
945 };
946
947 dmac0: dma-controller@e6700000 {
948 compatible = "renesas,dmac-r8a774e1",
949 "renesas,rcar-dmac";
950 reg = <0 0xe6700000 0 0x10000>;
951 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
955 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
956 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
959 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
960 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
961 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
962 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
963 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
964 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
965 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
966 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
968 interrupt-names = "error",
969 "ch0", "ch1", "ch2", "ch3",
970 "ch4", "ch5", "ch6", "ch7",
971 "ch8", "ch9", "ch10", "ch11",
972 "ch12", "ch13", "ch14", "ch15";
973 clocks = <&cpg CPG_MOD 219>;
974 clock-names = "fck";
975 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
976 resets = <&cpg 219>;
977 #dma-cells = <1>;
978 dma-channels = <16>;
979 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
980 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
981 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
982 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
983 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
984 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
985 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
986 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
987 };
988
989 dmac1: dma-controller@e7300000 {
990 compatible = "renesas,dmac-r8a774e1",
991 "renesas,rcar-dmac";
992 reg = <0 0xe7300000 0 0x10000>;
993 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
996 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
999 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
1000 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
1002 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1003 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1004 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1005 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1006 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1007 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1008 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1009 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
1010 interrupt-names = "error",
1011 "ch0", "ch1", "ch2", "ch3",
1012 "ch4", "ch5", "ch6", "ch7",
1013 "ch8", "ch9", "ch10", "ch11",
1014 "ch12", "ch13", "ch14", "ch15";
1015 clocks = <&cpg CPG_MOD 218>;
1016 clock-names = "fck";
1017 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1018 resets = <&cpg 218>;
1019 #dma-cells = <1>;
1020 dma-channels = <16>;
1021 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1022 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
1023 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
1024 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
1025 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
1026 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
1027 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
1028 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
1029 };
1030
1031 dmac2: dma-controller@e7310000 {
1032 compatible = "renesas,dmac-r8a774e1",
1033 "renesas,rcar-dmac";
1034 reg = <0 0xe7310000 0 0x10000>;
1035 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1036 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1037 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1038 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1039 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
1040 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1041 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
1042 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1043 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1044 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
1045 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
1046 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
1047 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
1048 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
1049 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
1050 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
1051 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
1052 interrupt-names = "error",
1053 "ch0", "ch1", "ch2", "ch3",
1054 "ch4", "ch5", "ch6", "ch7",
1055 "ch8", "ch9", "ch10", "ch11",
1056 "ch12", "ch13", "ch14", "ch15";
1057 clocks = <&cpg CPG_MOD 217>;
1058 clock-names = "fck";
1059 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1060 resets = <&cpg 217>;
1061 #dma-cells = <1>;
1062 dma-channels = <16>;
1063 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
1064 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
1065 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
1066 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
1067 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
1068 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
1069 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
1070 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
1071 };
1072
1073 ipmmu_ds0: iommu@e6740000 {
1074 compatible = "renesas,ipmmu-r8a774e1";
1075 reg = <0 0xe6740000 0 0x1000>;
1076 renesas,ipmmu-main = <&ipmmu_mm 0>;
1077 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1078 #iommu-cells = <1>;
1079 };
1080
1081 ipmmu_ds1: iommu@e7740000 {
1082 compatible = "renesas,ipmmu-r8a774e1";
1083 reg = <0 0xe7740000 0 0x1000>;
1084 renesas,ipmmu-main = <&ipmmu_mm 1>;
1085 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1086 #iommu-cells = <1>;
1087 };
1088
1089 ipmmu_hc: iommu@e6570000 {
1090 compatible = "renesas,ipmmu-r8a774e1";
1091 reg = <0 0xe6570000 0 0x1000>;
1092 renesas,ipmmu-main = <&ipmmu_mm 2>;
1093 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1094 #iommu-cells = <1>;
1095 };
1096
1097 ipmmu_mm: iommu@e67b0000 {
1098 compatible = "renesas,ipmmu-r8a774e1";
1099 reg = <0 0xe67b0000 0 0x1000>;
1100 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1101 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1102 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1103 #iommu-cells = <1>;
1104 };
1105
1106 ipmmu_mp0: iommu@ec670000 {
1107 compatible = "renesas,ipmmu-r8a774e1";
1108 reg = <0 0xec670000 0 0x1000>;
1109 renesas,ipmmu-main = <&ipmmu_mm 4>;
1110 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1111 #iommu-cells = <1>;
1112 };
1113
1114 ipmmu_pv0: iommu@fd800000 {
1115 compatible = "renesas,ipmmu-r8a774e1";
1116 reg = <0 0xfd800000 0 0x1000>;
1117 renesas,ipmmu-main = <&ipmmu_mm 6>;
1118 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1119 #iommu-cells = <1>;
1120 };
1121
1122 ipmmu_pv1: iommu@fd950000 {
1123 compatible = "renesas,ipmmu-r8a774e1";
1124 reg = <0 0xfd950000 0 0x1000>;
1125 renesas,ipmmu-main = <&ipmmu_mm 7>;
1126 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1127 #iommu-cells = <1>;
1128 };
1129
1130 ipmmu_pv2: iommu@fd960000 {
1131 compatible = "renesas,ipmmu-r8a774e1";
1132 reg = <0 0xfd960000 0 0x1000>;
1133 renesas,ipmmu-main = <&ipmmu_mm 8>;
1134 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1135 #iommu-cells = <1>;
1136 };
1137
1138 ipmmu_pv3: iommu@fd970000 {
1139 compatible = "renesas,ipmmu-r8a774e1";
1140 reg = <0 0xfd970000 0 0x1000>;
1141 renesas,ipmmu-main = <&ipmmu_mm 9>;
1142 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1143 #iommu-cells = <1>;
1144 };
1145
1146 ipmmu_vc0: iommu@fe6b0000 {
1147 compatible = "renesas,ipmmu-r8a774e1";
1148 reg = <0 0xfe6b0000 0 0x1000>;
1149 renesas,ipmmu-main = <&ipmmu_mm 12>;
1150 power-domains = <&sysc R8A774E1_PD_A3VC>;
1151 #iommu-cells = <1>;
1152 };
1153
1154 ipmmu_vc1: iommu@fe6f0000 {
1155 compatible = "renesas,ipmmu-r8a774e1";
1156 reg = <0 0xfe6f0000 0 0x1000>;
1157 renesas,ipmmu-main = <&ipmmu_mm 13>;
1158 power-domains = <&sysc R8A774E1_PD_A3VC>;
1159 #iommu-cells = <1>;
1160 };
1161
1162 ipmmu_vi0: iommu@febd0000 {
1163 compatible = "renesas,ipmmu-r8a774e1";
1164 reg = <0 0xfebd0000 0 0x1000>;
1165 renesas,ipmmu-main = <&ipmmu_mm 14>;
1166 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1167 #iommu-cells = <1>;
1168 };
1169
1170 ipmmu_vi1: iommu@febe0000 {
1171 compatible = "renesas,ipmmu-r8a774e1";
1172 reg = <0 0xfebe0000 0 0x1000>;
1173 renesas,ipmmu-main = <&ipmmu_mm 15>;
1174 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1175 #iommu-cells = <1>;
1176 };
1177
1178 ipmmu_vp0: iommu@fe990000 {
1179 compatible = "renesas,ipmmu-r8a774e1";
1180 reg = <0 0xfe990000 0 0x1000>;
1181 renesas,ipmmu-main = <&ipmmu_mm 16>;
1182 power-domains = <&sysc R8A774E1_PD_A3VP>;
1183 #iommu-cells = <1>;
1184 };
1185
1186 ipmmu_vp1: iommu@fe980000 {
1187 compatible = "renesas,ipmmu-r8a774e1";
1188 reg = <0 0xfe980000 0 0x1000>;
1189 renesas,ipmmu-main = <&ipmmu_mm 17>;
1190 power-domains = <&sysc R8A774E1_PD_A3VP>;
1191 #iommu-cells = <1>;
1192 };
1193
1194 avb: ethernet@e6800000 {
1195 compatible = "renesas,etheravb-r8a774e1",
1196 "renesas,etheravb-rcar-gen3";
1197 reg = <0 0xe6800000 0 0x800>;
1198 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1199 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1200 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1201 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1202 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1203 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1204 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1205 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1206 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1207 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1208 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1209 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1210 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1211 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
1212 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1213 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
1214 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
1215 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1216 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1217 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1218 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1219 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1221 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
1222 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1223 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1224 "ch4", "ch5", "ch6", "ch7",
1225 "ch8", "ch9", "ch10", "ch11",
1226 "ch12", "ch13", "ch14", "ch15",
1227 "ch16", "ch17", "ch18", "ch19",
1228 "ch20", "ch21", "ch22", "ch23",
1229 "ch24";
1230 clocks = <&cpg CPG_MOD 812>;
1231 clock-names = "fck";
1232 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1233 resets = <&cpg 812>;
1234 phy-mode = "rgmii";
1235 rx-internal-delay-ps = <0>;
1236 tx-internal-delay-ps = <0>;
1237 iommus = <&ipmmu_ds0 16>;
1238 #address-cells = <1>;
1239 #size-cells = <0>;
1240 status = "disabled";
1241 };
1242
1243 can0: can@e6c30000 {
1244 compatible = "renesas,can-r8a774e1",
1245 "renesas,rcar-gen3-can";
1246 reg = <0 0xe6c30000 0 0x1000>;
1247 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1248 clocks = <&cpg CPG_MOD 916>,
1249 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1250 <&can_clk>;
1251 clock-names = "clkp1", "clkp2", "can_clk";
1252 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1253 assigned-clock-rates = <40000000>;
1254 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1255 resets = <&cpg 916>;
1256 status = "disabled";
1257 };
1258
1259 can1: can@e6c38000 {
1260 compatible = "renesas,can-r8a774e1",
1261 "renesas,rcar-gen3-can";
1262 reg = <0 0xe6c38000 0 0x1000>;
1263 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1264 clocks = <&cpg CPG_MOD 915>,
1265 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1266 <&can_clk>;
1267 clock-names = "clkp1", "clkp2", "can_clk";
1268 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1269 assigned-clock-rates = <40000000>;
1270 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1271 resets = <&cpg 915>;
1272 status = "disabled";
1273 };
1274
1275 canfd: can@e66c0000 {
1276 compatible = "renesas,r8a774e1-canfd",
1277 "renesas,rcar-gen3-canfd";
1278 reg = <0 0xe66c0000 0 0x8000>;
1279 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1280 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1281 interrupt-names = "ch_int", "g_int";
1282 clocks = <&cpg CPG_MOD 914>,
1283 <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
1284 <&can_clk>;
1285 clock-names = "fck", "canfd", "can_clk";
1286 assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
1287 assigned-clock-rates = <40000000>;
1288 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1289 resets = <&cpg 914>;
1290 status = "disabled";
1291
1292 channel0 {
1293 status = "disabled";
1294 };
1295
1296 channel1 {
1297 status = "disabled";
1298 };
1299 };
1300
1301 pwm0: pwm@e6e30000 {
1302 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1303 reg = <0 0xe6e30000 0 0x8>;
1304 clocks = <&cpg CPG_MOD 523>;
1305 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1306 resets = <&cpg 523>;
1307 #pwm-cells = <2>;
1308 status = "disabled";
1309 };
1310
1311 pwm1: pwm@e6e31000 {
1312 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1313 reg = <0 0xe6e31000 0 0x8>;
1314 clocks = <&cpg CPG_MOD 523>;
1315 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1316 resets = <&cpg 523>;
1317 #pwm-cells = <2>;
1318 status = "disabled";
1319 };
1320
1321 pwm2: pwm@e6e32000 {
1322 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1323 reg = <0 0xe6e32000 0 0x8>;
1324 clocks = <&cpg CPG_MOD 523>;
1325 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1326 resets = <&cpg 523>;
1327 #pwm-cells = <2>;
1328 status = "disabled";
1329 };
1330
1331 pwm3: pwm@e6e33000 {
1332 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1333 reg = <0 0xe6e33000 0 0x8>;
1334 clocks = <&cpg CPG_MOD 523>;
1335 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1336 resets = <&cpg 523>;
1337 #pwm-cells = <2>;
1338 status = "disabled";
1339 };
1340
1341 pwm4: pwm@e6e34000 {
1342 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1343 reg = <0 0xe6e34000 0 0x8>;
1344 clocks = <&cpg CPG_MOD 523>;
1345 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1346 resets = <&cpg 523>;
1347 #pwm-cells = <2>;
1348 status = "disabled";
1349 };
1350
1351 pwm5: pwm@e6e35000 {
1352 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1353 reg = <0 0xe6e35000 0 0x8>;
1354 clocks = <&cpg CPG_MOD 523>;
1355 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1356 resets = <&cpg 523>;
1357 #pwm-cells = <2>;
1358 status = "disabled";
1359 };
1360
1361 pwm6: pwm@e6e36000 {
1362 compatible = "renesas,pwm-r8a774e1", "renesas,pwm-rcar";
1363 reg = <0 0xe6e36000 0 0x8>;
1364 clocks = <&cpg CPG_MOD 523>;
1365 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1366 resets = <&cpg 523>;
1367 #pwm-cells = <2>;
1368 status = "disabled";
1369 };
1370
1371 scif0: serial@e6e60000 {
1372 compatible = "renesas,scif-r8a774e1",
1373 "renesas,rcar-gen3-scif", "renesas,scif";
1374 reg = <0 0xe6e60000 0 0x40>;
1375 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1376 clocks = <&cpg CPG_MOD 207>,
1377 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1378 <&scif_clk>;
1379 clock-names = "fck", "brg_int", "scif_clk";
1380 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1381 <&dmac2 0x51>, <&dmac2 0x50>;
1382 dma-names = "tx", "rx", "tx", "rx";
1383 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1384 resets = <&cpg 207>;
1385 status = "disabled";
1386 };
1387
1388 scif1: serial@e6e68000 {
1389 compatible = "renesas,scif-r8a774e1",
1390 "renesas,rcar-gen3-scif", "renesas,scif";
1391 reg = <0 0xe6e68000 0 0x40>;
1392 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1393 clocks = <&cpg CPG_MOD 206>,
1394 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1395 <&scif_clk>;
1396 clock-names = "fck", "brg_int", "scif_clk";
1397 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1398 <&dmac2 0x53>, <&dmac2 0x52>;
1399 dma-names = "tx", "rx", "tx", "rx";
1400 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1401 resets = <&cpg 206>;
1402 status = "disabled";
1403 };
1404
1405 scif2: serial@e6e88000 {
1406 compatible = "renesas,scif-r8a774e1",
1407 "renesas,rcar-gen3-scif", "renesas,scif";
1408 reg = <0 0xe6e88000 0 0x40>;
1409 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1410 clocks = <&cpg CPG_MOD 310>,
1411 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1412 <&scif_clk>;
1413 clock-names = "fck", "brg_int", "scif_clk";
1414 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1415 <&dmac2 0x13>, <&dmac2 0x12>;
1416 dma-names = "tx", "rx", "tx", "rx";
1417 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1418 resets = <&cpg 310>;
1419 status = "disabled";
1420 };
1421
1422 scif3: serial@e6c50000 {
1423 compatible = "renesas,scif-r8a774e1",
1424 "renesas,rcar-gen3-scif", "renesas,scif";
1425 reg = <0 0xe6c50000 0 0x40>;
1426 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1427 clocks = <&cpg CPG_MOD 204>,
1428 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1429 <&scif_clk>;
1430 clock-names = "fck", "brg_int", "scif_clk";
1431 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1432 dma-names = "tx", "rx";
1433 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1434 resets = <&cpg 204>;
1435 status = "disabled";
1436 };
1437
1438 scif4: serial@e6c40000 {
1439 compatible = "renesas,scif-r8a774e1",
1440 "renesas,rcar-gen3-scif", "renesas,scif";
1441 reg = <0 0xe6c40000 0 0x40>;
1442 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1443 clocks = <&cpg CPG_MOD 203>,
1444 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1445 <&scif_clk>;
1446 clock-names = "fck", "brg_int", "scif_clk";
1447 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1448 dma-names = "tx", "rx";
1449 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1450 resets = <&cpg 203>;
1451 status = "disabled";
1452 };
1453
1454 scif5: serial@e6f30000 {
1455 compatible = "renesas,scif-r8a774e1",
1456 "renesas,rcar-gen3-scif", "renesas,scif";
1457 reg = <0 0xe6f30000 0 0x40>;
1458 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1459 clocks = <&cpg CPG_MOD 202>,
1460 <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
1461 <&scif_clk>;
1462 clock-names = "fck", "brg_int", "scif_clk";
1463 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1464 <&dmac2 0x5b>, <&dmac2 0x5a>;
1465 dma-names = "tx", "rx", "tx", "rx";
1466 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1467 resets = <&cpg 202>;
1468 status = "disabled";
1469 };
1470
1471 msiof0: spi@e6e90000 {
1472 compatible = "renesas,msiof-r8a774e1",
1473 "renesas,rcar-gen3-msiof";
1474 reg = <0 0xe6e90000 0 0x0064>;
1475 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1476 clocks = <&cpg CPG_MOD 211>;
1477 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1478 <&dmac2 0x41>, <&dmac2 0x40>;
1479 dma-names = "tx", "rx", "tx", "rx";
1480 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1481 resets = <&cpg 211>;
1482 #address-cells = <1>;
1483 #size-cells = <0>;
1484 status = "disabled";
1485 };
1486
1487 msiof1: spi@e6ea0000 {
1488 compatible = "renesas,msiof-r8a774e1",
1489 "renesas,rcar-gen3-msiof";
1490 reg = <0 0xe6ea0000 0 0x0064>;
1491 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1492 clocks = <&cpg CPG_MOD 210>;
1493 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1494 <&dmac2 0x43>, <&dmac2 0x42>;
1495 dma-names = "tx", "rx", "tx", "rx";
1496 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1497 resets = <&cpg 210>;
1498 #address-cells = <1>;
1499 #size-cells = <0>;
1500 status = "disabled";
1501 };
1502
1503 msiof2: spi@e6c00000 {
1504 compatible = "renesas,msiof-r8a774e1",
1505 "renesas,rcar-gen3-msiof";
1506 reg = <0 0xe6c00000 0 0x0064>;
1507 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1508 clocks = <&cpg CPG_MOD 209>;
1509 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1510 dma-names = "tx", "rx";
1511 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1512 resets = <&cpg 209>;
1513 #address-cells = <1>;
1514 #size-cells = <0>;
1515 status = "disabled";
1516 };
1517
1518 msiof3: spi@e6c10000 {
1519 compatible = "renesas,msiof-r8a774e1",
1520 "renesas,rcar-gen3-msiof";
1521 reg = <0 0xe6c10000 0 0x0064>;
1522 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1523 clocks = <&cpg CPG_MOD 208>;
1524 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1525 dma-names = "tx", "rx";
1526 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1527 resets = <&cpg 208>;
1528 #address-cells = <1>;
1529 #size-cells = <0>;
1530 status = "disabled";
1531 };
1532
1533 vin0: video@e6ef0000 {
1534 compatible = "renesas,vin-r8a774e1";
1535 reg = <0 0xe6ef0000 0 0x1000>;
1536 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1537 clocks = <&cpg CPG_MOD 811>;
1538 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1539 resets = <&cpg 811>;
1540 renesas,id = <0>;
1541 status = "disabled";
1542
1543 ports {
1544 #address-cells = <1>;
1545 #size-cells = <0>;
1546
1547 port@1 {
1548 #address-cells = <1>;
1549 #size-cells = <0>;
1550
1551 reg = <1>;
1552
1553 vin0csi20: endpoint@0 {
1554 reg = <0>;
1555 remote-endpoint = <&csi20vin0>;
1556 };
1557 vin0csi40: endpoint@2 {
1558 reg = <2>;
1559 remote-endpoint = <&csi40vin0>;
1560 };
1561 };
1562 };
1563 };
1564
1565 vin1: video@e6ef1000 {
1566 compatible = "renesas,vin-r8a774e1";
1567 reg = <0 0xe6ef1000 0 0x1000>;
1568 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1569 clocks = <&cpg CPG_MOD 810>;
1570 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1571 resets = <&cpg 810>;
1572 renesas,id = <1>;
1573 status = "disabled";
1574
1575 ports {
1576 #address-cells = <1>;
1577 #size-cells = <0>;
1578
1579 port@1 {
1580 #address-cells = <1>;
1581 #size-cells = <0>;
1582
1583 reg = <1>;
1584
1585 vin1csi20: endpoint@0 {
1586 reg = <0>;
1587 remote-endpoint = <&csi20vin1>;
1588 };
1589 vin1csi40: endpoint@2 {
1590 reg = <2>;
1591 remote-endpoint = <&csi40vin1>;
1592 };
1593 };
1594 };
1595 };
1596
1597 vin2: video@e6ef2000 {
1598 compatible = "renesas,vin-r8a774e1";
1599 reg = <0 0xe6ef2000 0 0x1000>;
1600 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1601 clocks = <&cpg CPG_MOD 809>;
1602 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1603 resets = <&cpg 809>;
1604 renesas,id = <2>;
1605 status = "disabled";
1606
1607 ports {
1608 #address-cells = <1>;
1609 #size-cells = <0>;
1610
1611 port@1 {
1612 #address-cells = <1>;
1613 #size-cells = <0>;
1614
1615 reg = <1>;
1616
1617 vin2csi20: endpoint@0 {
1618 reg = <0>;
1619 remote-endpoint = <&csi20vin2>;
1620 };
1621 vin2csi40: endpoint@2 {
1622 reg = <2>;
1623 remote-endpoint = <&csi40vin2>;
1624 };
1625 };
1626 };
1627 };
1628
1629 vin3: video@e6ef3000 {
1630 compatible = "renesas,vin-r8a774e1";
1631 reg = <0 0xe6ef3000 0 0x1000>;
1632 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1633 clocks = <&cpg CPG_MOD 808>;
1634 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1635 resets = <&cpg 808>;
1636 renesas,id = <3>;
1637 status = "disabled";
1638
1639 ports {
1640 #address-cells = <1>;
1641 #size-cells = <0>;
1642
1643 port@1 {
1644 #address-cells = <1>;
1645 #size-cells = <0>;
1646
1647 reg = <1>;
1648
1649 vin3csi20: endpoint@0 {
1650 reg = <0>;
1651 remote-endpoint = <&csi20vin3>;
1652 };
1653 vin3csi40: endpoint@2 {
1654 reg = <2>;
1655 remote-endpoint = <&csi40vin3>;
1656 };
1657 };
1658 };
1659 };
1660
1661 vin4: video@e6ef4000 {
1662 compatible = "renesas,vin-r8a774e1";
1663 reg = <0 0xe6ef4000 0 0x1000>;
1664 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1665 clocks = <&cpg CPG_MOD 807>;
1666 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1667 resets = <&cpg 807>;
1668 renesas,id = <4>;
1669 status = "disabled";
1670
1671 ports {
1672 #address-cells = <1>;
1673 #size-cells = <0>;
1674
1675 port@1 {
1676 #address-cells = <1>;
1677 #size-cells = <0>;
1678
1679 reg = <1>;
1680
1681 vin4csi20: endpoint@0 {
1682 reg = <0>;
1683 remote-endpoint = <&csi20vin4>;
1684 };
1685 };
1686 };
1687 };
1688
1689 vin5: video@e6ef5000 {
1690 compatible = "renesas,vin-r8a774e1";
1691 reg = <0 0xe6ef5000 0 0x1000>;
1692 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1693 clocks = <&cpg CPG_MOD 806>;
1694 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1695 resets = <&cpg 806>;
1696 renesas,id = <5>;
1697 status = "disabled";
1698
1699 ports {
1700 #address-cells = <1>;
1701 #size-cells = <0>;
1702
1703 port@1 {
1704 #address-cells = <1>;
1705 #size-cells = <0>;
1706
1707 reg = <1>;
1708
1709 vin5csi20: endpoint@0 {
1710 reg = <0>;
1711 remote-endpoint = <&csi20vin5>;
1712 };
1713 };
1714 };
1715 };
1716
1717 vin6: video@e6ef6000 {
1718 compatible = "renesas,vin-r8a774e1";
1719 reg = <0 0xe6ef6000 0 0x1000>;
1720 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1721 clocks = <&cpg CPG_MOD 805>;
1722 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1723 resets = <&cpg 805>;
1724 renesas,id = <6>;
1725 status = "disabled";
1726
1727 ports {
1728 #address-cells = <1>;
1729 #size-cells = <0>;
1730
1731 port@1 {
1732 #address-cells = <1>;
1733 #size-cells = <0>;
1734
1735 reg = <1>;
1736
1737 vin6csi20: endpoint@0 {
1738 reg = <0>;
1739 remote-endpoint = <&csi20vin6>;
1740 };
1741 };
1742 };
1743 };
1744
1745 vin7: video@e6ef7000 {
1746 compatible = "renesas,vin-r8a774e1";
1747 reg = <0 0xe6ef7000 0 0x1000>;
1748 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1749 clocks = <&cpg CPG_MOD 804>;
1750 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1751 resets = <&cpg 804>;
1752 renesas,id = <7>;
1753 status = "disabled";
1754
1755 ports {
1756 #address-cells = <1>;
1757 #size-cells = <0>;
1758
1759 port@1 {
1760 #address-cells = <1>;
1761 #size-cells = <0>;
1762
1763 reg = <1>;
1764
1765 vin7csi20: endpoint@0 {
1766 reg = <0>;
1767 remote-endpoint = <&csi20vin7>;
1768 };
1769 };
1770 };
1771 };
1772
1773 rcar_sound: sound@ec500000 {
1774 /*
1775 * #sound-dai-cells is required if simple-card
1776 *
1777 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1778 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1779 */
1780 /*
1781 * #clock-cells is required for audio_clkout0/1/2/3
1782 *
1783 * clkout : #clock-cells = <0>; <&rcar_sound>;
1784 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1785 */
1786 compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3";
1787 reg = <0 0xec500000 0 0x1000>, /* SCU */
1788 <0 0xec5a0000 0 0x100>, /* ADG */
1789 <0 0xec540000 0 0x1000>, /* SSIU */
1790 <0 0xec541000 0 0x280>, /* SSI */
1791 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1792 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1793
1794 clocks = <&cpg CPG_MOD 1005>,
1795 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1796 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1797 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1798 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1799 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1800 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1801 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1802 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1803 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1804 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1805 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1806 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1807 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1808 <&audio_clk_a>, <&audio_clk_b>,
1809 <&audio_clk_c>,
1810 <&cpg CPG_MOD 922>;
1811 clock-names = "ssi-all",
1812 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1813 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1814 "ssi.1", "ssi.0",
1815 "src.9", "src.8", "src.7", "src.6",
1816 "src.5", "src.4", "src.3", "src.2",
1817 "src.1", "src.0",
1818 "mix.1", "mix.0",
1819 "ctu.1", "ctu.0",
1820 "dvc.0", "dvc.1",
1821 "clk_a", "clk_b", "clk_c", "clk_i";
1822 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
1823 resets = <&cpg 1005>,
1824 <&cpg 1006>, <&cpg 1007>,
1825 <&cpg 1008>, <&cpg 1009>,
1826 <&cpg 1010>, <&cpg 1011>,
1827 <&cpg 1012>, <&cpg 1013>,
1828 <&cpg 1014>, <&cpg 1015>;
1829 reset-names = "ssi-all",
1830 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1831 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1832 "ssi.1", "ssi.0";
1833 status = "disabled";
1834
1835 rcar_sound,dvc {
1836 dvc0: dvc-0 {
1837 dmas = <&audma1 0xbc>;
1838 dma-names = "tx";
1839 };
1840 dvc1: dvc-1 {
1841 dmas = <&audma1 0xbe>;
1842 dma-names = "tx";
1843 };
1844 };
1845
1846 rcar_sound,mix {
1847 mix0: mix-0 { };
1848 mix1: mix-1 { };
1849 };
1850
1851 rcar_sound,ctu {
1852 ctu00: ctu-0 { };
1853 ctu01: ctu-1 { };
1854 ctu02: ctu-2 { };
1855 ctu03: ctu-3 { };
1856 ctu10: ctu-4 { };
1857 ctu11: ctu-5 { };
1858 ctu12: ctu-6 { };
1859 ctu13: ctu-7 { };
1860 };
1861
1862 rcar_sound,src {
1863 src0: src-0 {
1864 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1865 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1866 dma-names = "rx", "tx";
1867 };
1868 src1: src-1 {
1869 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1870 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1871 dma-names = "rx", "tx";
1872 };
1873 src2: src-2 {
1874 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1875 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1876 dma-names = "rx", "tx";
1877 };
1878 src3: src-3 {
1879 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1880 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1881 dma-names = "rx", "tx";
1882 };
1883 src4: src-4 {
1884 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1885 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1886 dma-names = "rx", "tx";
1887 };
1888 src5: src-5 {
1889 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1890 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1891 dma-names = "rx", "tx";
1892 };
1893 src6: src-6 {
1894 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1895 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1896 dma-names = "rx", "tx";
1897 };
1898 src7: src-7 {
1899 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1900 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1901 dma-names = "rx", "tx";
1902 };
1903 src8: src-8 {
1904 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1905 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1906 dma-names = "rx", "tx";
1907 };
1908 src9: src-9 {
1909 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1910 dmas = <&audma0 0x97>, <&audma1 0xba>;
1911 dma-names = "rx", "tx";
1912 };
1913 };
1914
1915 rcar_sound,ssiu {
1916 ssiu00: ssiu-0 {
1917 dmas = <&audma0 0x15>, <&audma1 0x16>;
1918 dma-names = "rx", "tx";
1919 };
1920 ssiu01: ssiu-1 {
1921 dmas = <&audma0 0x35>, <&audma1 0x36>;
1922 dma-names = "rx", "tx";
1923 };
1924 ssiu02: ssiu-2 {
1925 dmas = <&audma0 0x37>, <&audma1 0x38>;
1926 dma-names = "rx", "tx";
1927 };
1928 ssiu03: ssiu-3 {
1929 dmas = <&audma0 0x47>, <&audma1 0x48>;
1930 dma-names = "rx", "tx";
1931 };
1932 ssiu04: ssiu-4 {
1933 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1934 dma-names = "rx", "tx";
1935 };
1936 ssiu05: ssiu-5 {
1937 dmas = <&audma0 0x43>, <&audma1 0x44>;
1938 dma-names = "rx", "tx";
1939 };
1940 ssiu06: ssiu-6 {
1941 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1942 dma-names = "rx", "tx";
1943 };
1944 ssiu07: ssiu-7 {
1945 dmas = <&audma0 0x53>, <&audma1 0x54>;
1946 dma-names = "rx", "tx";
1947 };
1948 ssiu10: ssiu-8 {
1949 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1950 dma-names = "rx", "tx";
1951 };
1952 ssiu11: ssiu-9 {
1953 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1954 dma-names = "rx", "tx";
1955 };
1956 ssiu12: ssiu-10 {
1957 dmas = <&audma0 0x57>, <&audma1 0x58>;
1958 dma-names = "rx", "tx";
1959 };
1960 ssiu13: ssiu-11 {
1961 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1962 dma-names = "rx", "tx";
1963 };
1964 ssiu14: ssiu-12 {
1965 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1966 dma-names = "rx", "tx";
1967 };
1968 ssiu15: ssiu-13 {
1969 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1970 dma-names = "rx", "tx";
1971 };
1972 ssiu16: ssiu-14 {
1973 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1974 dma-names = "rx", "tx";
1975 };
1976 ssiu17: ssiu-15 {
1977 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1978 dma-names = "rx", "tx";
1979 };
1980 ssiu20: ssiu-16 {
1981 dmas = <&audma0 0x63>, <&audma1 0x64>;
1982 dma-names = "rx", "tx";
1983 };
1984 ssiu21: ssiu-17 {
1985 dmas = <&audma0 0x67>, <&audma1 0x68>;
1986 dma-names = "rx", "tx";
1987 };
1988 ssiu22: ssiu-18 {
1989 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1990 dma-names = "rx", "tx";
1991 };
1992 ssiu23: ssiu-19 {
1993 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1994 dma-names = "rx", "tx";
1995 };
1996 ssiu24: ssiu-20 {
1997 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1998 dma-names = "rx", "tx";
1999 };
2000 ssiu25: ssiu-21 {
2001 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2002 dma-names = "rx", "tx";
2003 };
2004 ssiu26: ssiu-22 {
2005 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2006 dma-names = "rx", "tx";
2007 };
2008 ssiu27: ssiu-23 {
2009 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2010 dma-names = "rx", "tx";
2011 };
2012 ssiu30: ssiu-24 {
2013 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2014 dma-names = "rx", "tx";
2015 };
2016 ssiu31: ssiu-25 {
2017 dmas = <&audma0 0x21>, <&audma1 0x22>;
2018 dma-names = "rx", "tx";
2019 };
2020 ssiu32: ssiu-26 {
2021 dmas = <&audma0 0x23>, <&audma1 0x24>;
2022 dma-names = "rx", "tx";
2023 };
2024 ssiu33: ssiu-27 {
2025 dmas = <&audma0 0x25>, <&audma1 0x26>;
2026 dma-names = "rx", "tx";
2027 };
2028 ssiu34: ssiu-28 {
2029 dmas = <&audma0 0x27>, <&audma1 0x28>;
2030 dma-names = "rx", "tx";
2031 };
2032 ssiu35: ssiu-29 {
2033 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2034 dma-names = "rx", "tx";
2035 };
2036 ssiu36: ssiu-30 {
2037 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2038 dma-names = "rx", "tx";
2039 };
2040 ssiu37: ssiu-31 {
2041 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2042 dma-names = "rx", "tx";
2043 };
2044 ssiu40: ssiu-32 {
2045 dmas = <&audma0 0x71>, <&audma1 0x72>;
2046 dma-names = "rx", "tx";
2047 };
2048 ssiu41: ssiu-33 {
2049 dmas = <&audma0 0x17>, <&audma1 0x18>;
2050 dma-names = "rx", "tx";
2051 };
2052 ssiu42: ssiu-34 {
2053 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2054 dma-names = "rx", "tx";
2055 };
2056 ssiu43: ssiu-35 {
2057 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2058 dma-names = "rx", "tx";
2059 };
2060 ssiu44: ssiu-36 {
2061 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2062 dma-names = "rx", "tx";
2063 };
2064 ssiu45: ssiu-37 {
2065 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2066 dma-names = "rx", "tx";
2067 };
2068 ssiu46: ssiu-38 {
2069 dmas = <&audma0 0x31>, <&audma1 0x32>;
2070 dma-names = "rx", "tx";
2071 };
2072 ssiu47: ssiu-39 {
2073 dmas = <&audma0 0x33>, <&audma1 0x34>;
2074 dma-names = "rx", "tx";
2075 };
2076 ssiu50: ssiu-40 {
2077 dmas = <&audma0 0x73>, <&audma1 0x74>;
2078 dma-names = "rx", "tx";
2079 };
2080 ssiu60: ssiu-41 {
2081 dmas = <&audma0 0x75>, <&audma1 0x76>;
2082 dma-names = "rx", "tx";
2083 };
2084 ssiu70: ssiu-42 {
2085 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2086 dma-names = "rx", "tx";
2087 };
2088 ssiu80: ssiu-43 {
2089 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2090 dma-names = "rx", "tx";
2091 };
2092 ssiu90: ssiu-44 {
2093 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2094 dma-names = "rx", "tx";
2095 };
2096 ssiu91: ssiu-45 {
2097 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2098 dma-names = "rx", "tx";
2099 };
2100 ssiu92: ssiu-46 {
2101 dmas = <&audma0 0x81>, <&audma1 0x82>;
2102 dma-names = "rx", "tx";
2103 };
2104 ssiu93: ssiu-47 {
2105 dmas = <&audma0 0x83>, <&audma1 0x84>;
2106 dma-names = "rx", "tx";
2107 };
2108 ssiu94: ssiu-48 {
2109 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2110 dma-names = "rx", "tx";
2111 };
2112 ssiu95: ssiu-49 {
2113 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2114 dma-names = "rx", "tx";
2115 };
2116 ssiu96: ssiu-50 {
2117 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2118 dma-names = "rx", "tx";
2119 };
2120 ssiu97: ssiu-51 {
2121 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2122 dma-names = "rx", "tx";
2123 };
2124 };
2125
2126 rcar_sound,ssi {
2127 ssi0: ssi-0 {
2128 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
2129 dmas = <&audma0 0x01>, <&audma1 0x02>;
2130 dma-names = "rx", "tx";
2131 };
2132 ssi1: ssi-1 {
2133 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
2134 dmas = <&audma0 0x03>, <&audma1 0x04>;
2135 dma-names = "rx", "tx";
2136 };
2137 ssi2: ssi-2 {
2138 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
2139 dmas = <&audma0 0x05>, <&audma1 0x06>;
2140 dma-names = "rx", "tx";
2141 };
2142 ssi3: ssi-3 {
2143 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
2144 dmas = <&audma0 0x07>, <&audma1 0x08>;
2145 dma-names = "rx", "tx";
2146 };
2147 ssi4: ssi-4 {
2148 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
2149 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2150 dma-names = "rx", "tx";
2151 };
2152 ssi5: ssi-5 {
2153 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
2154 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2155 dma-names = "rx", "tx";
2156 };
2157 ssi6: ssi-6 {
2158 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
2159 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2160 dma-names = "rx", "tx";
2161 };
2162 ssi7: ssi-7 {
2163 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
2164 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2165 dma-names = "rx", "tx";
2166 };
2167 ssi8: ssi-8 {
2168 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
2169 dmas = <&audma0 0x11>, <&audma1 0x12>;
2170 dma-names = "rx", "tx";
2171 };
2172 ssi9: ssi-9 {
2173 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
2174 dmas = <&audma0 0x13>, <&audma1 0x14>;
2175 dma-names = "rx", "tx";
2176 };
2177 };
2178 };
2179
2180 audma0: dma-controller@ec700000 {
2181 compatible = "renesas,dmac-r8a774e1",
2182 "renesas,rcar-dmac";
2183 reg = <0 0xec700000 0 0x10000>;
2184 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
2185 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2186 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2187 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2188 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2189 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2190 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2191 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2192 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2193 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2194 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2195 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2196 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2197 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2198 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2199 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2200 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
2201 interrupt-names = "error",
2202 "ch0", "ch1", "ch2", "ch3",
2203 "ch4", "ch5", "ch6", "ch7",
2204 "ch8", "ch9", "ch10", "ch11",
2205 "ch12", "ch13", "ch14", "ch15";
2206 clocks = <&cpg CPG_MOD 502>;
2207 clock-names = "fck";
2208 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2209 resets = <&cpg 502>;
2210 #dma-cells = <1>;
2211 dma-channels = <16>;
2212 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
2213 <&ipmmu_mp0 2>, <&ipmmu_mp0 3>,
2214 <&ipmmu_mp0 4>, <&ipmmu_mp0 5>,
2215 <&ipmmu_mp0 6>, <&ipmmu_mp0 7>,
2216 <&ipmmu_mp0 8>, <&ipmmu_mp0 9>,
2217 <&ipmmu_mp0 10>, <&ipmmu_mp0 11>,
2218 <&ipmmu_mp0 12>, <&ipmmu_mp0 13>,
2219 <&ipmmu_mp0 14>, <&ipmmu_mp0 15>;
2220 };
2221
2222 audma1: dma-controller@ec720000 {
2223 compatible = "renesas,dmac-r8a774e1",
2224 "renesas,rcar-dmac";
2225 reg = <0 0xec720000 0 0x10000>;
2226 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
2227 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2228 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2230 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2231 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2232 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2233 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2234 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2235 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2236 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2237 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
2238 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2239 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
2240 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
2241 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
2242 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
2243 interrupt-names = "error",
2244 "ch0", "ch1", "ch2", "ch3",
2245 "ch4", "ch5", "ch6", "ch7",
2246 "ch8", "ch9", "ch10", "ch11",
2247 "ch12", "ch13", "ch14", "ch15";
2248 clocks = <&cpg CPG_MOD 501>;
2249 clock-names = "fck";
2250 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2251 resets = <&cpg 501>;
2252 #dma-cells = <1>;
2253 dma-channels = <16>;
2254 iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>,
2255 <&ipmmu_mp0 18>, <&ipmmu_mp0 19>,
2256 <&ipmmu_mp0 20>, <&ipmmu_mp0 21>,
2257 <&ipmmu_mp0 22>, <&ipmmu_mp0 23>,
2258 <&ipmmu_mp0 24>, <&ipmmu_mp0 25>,
2259 <&ipmmu_mp0 26>, <&ipmmu_mp0 27>,
2260 <&ipmmu_mp0 28>, <&ipmmu_mp0 29>,
2261 <&ipmmu_mp0 30>, <&ipmmu_mp0 31>;
2262 };
2263
2264 xhci0: usb@ee000000 {
2265 compatible = "renesas,xhci-r8a774e1",
2266 "renesas,rcar-gen3-xhci";
2267 reg = <0 0xee000000 0 0xc00>;
2268 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2269 clocks = <&cpg CPG_MOD 328>;
2270 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2271 resets = <&cpg 328>;
2272 status = "disabled";
2273 };
2274
2275 usb3_peri0: usb@ee020000 {
2276 compatible = "renesas,r8a774e1-usb3-peri",
2277 "renesas,rcar-gen3-usb3-peri";
2278 reg = <0 0xee020000 0 0x400>;
2279 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2280 clocks = <&cpg CPG_MOD 328>;
2281 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2282 resets = <&cpg 328>;
2283 status = "disabled";
2284 };
2285
2286 ohci0: usb@ee080000 {
2287 compatible = "generic-ohci";
2288 reg = <0 0xee080000 0 0x100>;
2289 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2290 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2291 phys = <&usb2_phy0 1>;
2292 phy-names = "usb";
2293 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2294 resets = <&cpg 703>, <&cpg 704>;
2295 status = "disabled";
2296 };
2297
2298 ohci1: usb@ee0a0000 {
2299 compatible = "generic-ohci";
2300 reg = <0 0xee0a0000 0 0x100>;
2301 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2302 clocks = <&cpg CPG_MOD 702>;
2303 phys = <&usb2_phy1 1>;
2304 phy-names = "usb";
2305 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2306 resets = <&cpg 702>;
2307 status = "disabled";
2308 };
2309
2310 ehci0: usb@ee080100 {
2311 compatible = "generic-ehci";
2312 reg = <0 0xee080100 0 0x100>;
2313 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2314 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2315 phys = <&usb2_phy0 2>;
2316 phy-names = "usb";
2317 companion = <&ohci0>;
2318 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2319 resets = <&cpg 703>, <&cpg 704>;
2320 status = "disabled";
2321 };
2322
2323 ehci1: usb@ee0a0100 {
2324 compatible = "generic-ehci";
2325 reg = <0 0xee0a0100 0 0x100>;
2326 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2327 clocks = <&cpg CPG_MOD 702>;
2328 phys = <&usb2_phy1 2>;
2329 phy-names = "usb";
2330 companion = <&ohci1>;
2331 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2332 resets = <&cpg 702>;
2333 status = "disabled";
2334 };
2335
2336 usb2_phy0: usb-phy@ee080200 {
2337 compatible = "renesas,usb2-phy-r8a774e1",
2338 "renesas,rcar-gen3-usb2-phy";
2339 reg = <0 0xee080200 0 0x700>;
2340 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2341 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2342 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2343 resets = <&cpg 703>, <&cpg 704>;
2344 #phy-cells = <1>;
2345 status = "disabled";
2346 };
2347
2348 usb2_phy1: usb-phy@ee0a0200 {
2349 compatible = "renesas,usb2-phy-r8a774e1",
2350 "renesas,rcar-gen3-usb2-phy";
2351 reg = <0 0xee0a0200 0 0x700>;
2352 clocks = <&cpg CPG_MOD 702>;
2353 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2354 resets = <&cpg 702>;
2355 #phy-cells = <1>;
2356 status = "disabled";
2357 };
2358
2359 sdhi0: mmc@ee100000 {
2360 compatible = "renesas,sdhi-r8a774e1",
2361 "renesas,rcar-gen3-sdhi";
2362 reg = <0 0xee100000 0 0x2000>;
2363 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2364 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774E1_CLK_SD0H>;
2365 clock-names = "core", "clkh";
2366 max-frequency = <200000000>;
2367 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2368 resets = <&cpg 314>;
2369 iommus = <&ipmmu_ds1 32>;
2370 status = "disabled";
2371 };
2372
2373 sdhi1: mmc@ee120000 {
2374 compatible = "renesas,sdhi-r8a774e1",
2375 "renesas,rcar-gen3-sdhi";
2376 reg = <0 0xee120000 0 0x2000>;
2377 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2378 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774E1_CLK_SD1H>;
2379 clock-names = "core", "clkh";
2380 max-frequency = <200000000>;
2381 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2382 resets = <&cpg 313>;
2383 iommus = <&ipmmu_ds1 33>;
2384 status = "disabled";
2385 };
2386
2387 sdhi2: mmc@ee140000 {
2388 compatible = "renesas,sdhi-r8a774e1",
2389 "renesas,rcar-gen3-sdhi";
2390 reg = <0 0xee140000 0 0x2000>;
2391 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2392 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774E1_CLK_SD2H>;
2393 clock-names = "core", "clkh";
2394 max-frequency = <200000000>;
2395 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2396 resets = <&cpg 312>;
2397 iommus = <&ipmmu_ds1 34>;
2398 status = "disabled";
2399 };
2400
2401 sdhi3: mmc@ee160000 {
2402 compatible = "renesas,sdhi-r8a774e1",
2403 "renesas,rcar-gen3-sdhi";
2404 reg = <0 0xee160000 0 0x2000>;
2405 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2406 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774E1_CLK_SD3H>;
2407 clock-names = "core", "clkh";
2408 max-frequency = <200000000>;
2409 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2410 resets = <&cpg 311>;
2411 iommus = <&ipmmu_ds1 35>;
2412 status = "disabled";
2413 };
2414
2415 rpc: spi@ee200000 {
2416 compatible = "renesas,r8a774e1-rpc-if",
2417 "renesas,rcar-gen3-rpc-if";
2418 reg = <0 0xee200000 0 0x200>,
2419 <0 0x08000000 0 0x4000000>,
2420 <0 0xee208000 0 0x100>;
2421 reg-names = "regs", "dirmap", "wbuf";
2422 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2423 clocks = <&cpg CPG_MOD 917>;
2424 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2425 resets = <&cpg 917>;
2426 #address-cells = <1>;
2427 #size-cells = <0>;
2428 status = "disabled";
2429 };
2430
2431 sata: sata@ee300000 {
2432 compatible = "renesas,sata-r8a774e1",
2433 "renesas,rcar-gen3-sata";
2434 reg = <0 0xee300000 0 0x200000>;
2435 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2436 clocks = <&cpg CPG_MOD 815>;
2437 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2438 resets = <&cpg 815>;
2439 iommus = <&ipmmu_hc 2>;
2440 status = "disabled";
2441 };
2442
2443 gic: interrupt-controller@f1010000 {
2444 compatible = "arm,gic-400";
2445 #interrupt-cells = <3>;
2446 #address-cells = <0>;
2447 interrupt-controller;
2448 reg = <0x0 0xf1010000 0 0x1000>,
2449 <0x0 0xf1020000 0 0x20000>,
2450 <0x0 0xf1040000 0 0x20000>,
2451 <0x0 0xf1060000 0 0x20000>;
2452 interrupts = <GIC_PPI 9
2453 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2454 clocks = <&cpg CPG_MOD 408>;
2455 clock-names = "clk";
2456 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2457 resets = <&cpg 408>;
2458 };
2459
2460 pciec0: pcie@fe000000 {
2461 compatible = "renesas,pcie-r8a774e1",
2462 "renesas,pcie-rcar-gen3";
2463 reg = <0 0xfe000000 0 0x80000>;
2464 #address-cells = <3>;
2465 #size-cells = <2>;
2466 bus-range = <0x00 0xff>;
2467 device_type = "pci";
2468 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2469 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2470 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2471 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2472 /* Map all possible DDR/IOMMU as inbound ranges */
2473 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2474 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2475 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2476 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2477 #interrupt-cells = <1>;
2478 interrupt-map-mask = <0 0 0 0>;
2479 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2480 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2481 clock-names = "pcie", "pcie_bus";
2482 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2483 resets = <&cpg 319>;
2484 iommu-map = <0 &ipmmu_hc 0 1>;
2485 iommu-map-mask = <0>;
2486 status = "disabled";
2487 };
2488
2489 pciec1: pcie@ee800000 {
2490 compatible = "renesas,pcie-r8a774e1",
2491 "renesas,pcie-rcar-gen3";
2492 reg = <0 0xee800000 0 0x80000>;
2493 #address-cells = <3>;
2494 #size-cells = <2>;
2495 bus-range = <0x00 0xff>;
2496 device_type = "pci";
2497 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2498 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2499 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2500 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2501 /* Map all possible DDR/IOMMU as inbound ranges */
2502 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2503 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2504 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2505 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2506 #interrupt-cells = <1>;
2507 interrupt-map-mask = <0 0 0 0>;
2508 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2509 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2510 clock-names = "pcie", "pcie_bus";
2511 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2512 resets = <&cpg 318>;
2513 iommu-map = <0 &ipmmu_hc 1 1>;
2514 iommu-map-mask = <0>;
2515 status = "disabled";
2516 };
2517
2518 pciec0_ep: pcie-ep@fe000000 {
2519 compatible = "renesas,r8a774e1-pcie-ep",
2520 "renesas,rcar-gen3-pcie-ep";
2521 reg = <0x0 0xfe000000 0 0x80000>,
2522 <0x0 0xfe100000 0 0x100000>,
2523 <0x0 0xfe200000 0 0x200000>,
2524 <0x0 0x30000000 0 0x8000000>,
2525 <0x0 0x38000000 0 0x8000000>;
2526 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2527 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2528 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2529 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2530 clocks = <&cpg CPG_MOD 319>;
2531 clock-names = "pcie";
2532 resets = <&cpg 319>;
2533 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2534 status = "disabled";
2535 };
2536
2537 pciec1_ep: pcie-ep@ee800000 {
2538 compatible = "renesas,r8a774e1-pcie-ep",
2539 "renesas,rcar-gen3-pcie-ep";
2540 reg = <0x0 0xee800000 0 0x80000>,
2541 <0x0 0xee900000 0 0x100000>,
2542 <0x0 0xeea00000 0 0x200000>,
2543 <0x0 0xc0000000 0 0x8000000>,
2544 <0x0 0xc8000000 0 0x8000000>;
2545 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
2546 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2547 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2548 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2549 clocks = <&cpg CPG_MOD 318>;
2550 clock-names = "pcie";
2551 resets = <&cpg 318>;
2552 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2553 status = "disabled";
2554 };
2555
2556 vspbc: vsp@fe920000 {
2557 compatible = "renesas,vsp2";
2558 reg = <0 0xfe920000 0 0x8000>;
2559 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
2560 clocks = <&cpg CPG_MOD 624>;
2561 power-domains = <&sysc R8A774E1_PD_A3VP>;
2562 resets = <&cpg 624>;
2563
2564 renesas,fcp = <&fcpvb1>;
2565 };
2566
2567 vspbd: vsp@fe960000 {
2568 compatible = "renesas,vsp2";
2569 reg = <0 0xfe960000 0 0x8000>;
2570 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2571 clocks = <&cpg CPG_MOD 626>;
2572 power-domains = <&sysc R8A774E1_PD_A3VP>;
2573 resets = <&cpg 626>;
2574
2575 renesas,fcp = <&fcpvb0>;
2576 };
2577
2578 vspd0: vsp@fea20000 {
2579 compatible = "renesas,vsp2";
2580 reg = <0 0xfea20000 0 0x5000>;
2581 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
2582 clocks = <&cpg CPG_MOD 623>;
2583 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2584 resets = <&cpg 623>;
2585
2586 renesas,fcp = <&fcpvd0>;
2587 };
2588
2589 vspd1: vsp@fea28000 {
2590 compatible = "renesas,vsp2";
2591 reg = <0 0xfea28000 0 0x5000>;
2592 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
2593 clocks = <&cpg CPG_MOD 622>;
2594 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2595 resets = <&cpg 622>;
2596
2597 renesas,fcp = <&fcpvd1>;
2598 };
2599
2600 vspi0: vsp@fe9a0000 {
2601 compatible = "renesas,vsp2";
2602 reg = <0 0xfe9a0000 0 0x8000>;
2603 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2604 clocks = <&cpg CPG_MOD 631>;
2605 power-domains = <&sysc R8A774E1_PD_A3VP>;
2606 resets = <&cpg 631>;
2607
2608 renesas,fcp = <&fcpvi0>;
2609 };
2610
2611 vspi1: vsp@fe9b0000 {
2612 compatible = "renesas,vsp2";
2613 reg = <0 0xfe9b0000 0 0x8000>;
2614 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
2615 clocks = <&cpg CPG_MOD 630>;
2616 power-domains = <&sysc R8A774E1_PD_A3VP>;
2617 resets = <&cpg 630>;
2618
2619 renesas,fcp = <&fcpvi1>;
2620 };
2621
2622 fdp1@fe940000 {
2623 compatible = "renesas,fdp1";
2624 reg = <0 0xfe940000 0 0x2400>;
2625 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2626 clocks = <&cpg CPG_MOD 119>;
2627 power-domains = <&sysc R8A774E1_PD_A3VP>;
2628 resets = <&cpg 119>;
2629 renesas,fcp = <&fcpf0>;
2630 };
2631
2632 fdp1@fe944000 {
2633 compatible = "renesas,fdp1";
2634 reg = <0 0xfe944000 0 0x2400>;
2635 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
2636 clocks = <&cpg CPG_MOD 118>;
2637 power-domains = <&sysc R8A774E1_PD_A3VP>;
2638 resets = <&cpg 118>;
2639 renesas,fcp = <&fcpf1>;
2640 };
2641
2642 fcpf0: fcp@fe950000 {
2643 compatible = "renesas,fcpf";
2644 reg = <0 0xfe950000 0 0x200>;
2645 clocks = <&cpg CPG_MOD 615>;
2646 power-domains = <&sysc R8A774E1_PD_A3VP>;
2647 resets = <&cpg 615>;
2648 };
2649
2650 fcpf1: fcp@fe951000 {
2651 compatible = "renesas,fcpf";
2652 reg = <0 0xfe951000 0 0x200>;
2653 clocks = <&cpg CPG_MOD 614>;
2654 power-domains = <&sysc R8A774E1_PD_A3VP>;
2655 resets = <&cpg 614>;
2656 };
2657
2658 fcpvb0: fcp@fe96f000 {
2659 compatible = "renesas,fcpv";
2660 reg = <0 0xfe96f000 0 0x200>;
2661 clocks = <&cpg CPG_MOD 607>;
2662 power-domains = <&sysc R8A774E1_PD_A3VP>;
2663 resets = <&cpg 607>;
2664 };
2665
2666 fcpvb1: fcp@fe92f000 {
2667 compatible = "renesas,fcpv";
2668 reg = <0 0xfe92f000 0 0x200>;
2669 clocks = <&cpg CPG_MOD 606>;
2670 power-domains = <&sysc R8A774E1_PD_A3VP>;
2671 resets = <&cpg 606>;
2672 };
2673
2674 fcpvi0: fcp@fe9af000 {
2675 compatible = "renesas,fcpv";
2676 reg = <0 0xfe9af000 0 0x200>;
2677 clocks = <&cpg CPG_MOD 611>;
2678 power-domains = <&sysc R8A774E1_PD_A3VP>;
2679 resets = <&cpg 611>;
2680 };
2681
2682 fcpvi1: fcp@fe9bf000 {
2683 compatible = "renesas,fcpv";
2684 reg = <0 0xfe9bf000 0 0x200>;
2685 clocks = <&cpg CPG_MOD 610>;
2686 power-domains = <&sysc R8A774E1_PD_A3VP>;
2687 resets = <&cpg 610>;
2688 };
2689
2690 fcpvd0: fcp@fea27000 {
2691 compatible = "renesas,fcpv";
2692 reg = <0 0xfea27000 0 0x200>;
2693 clocks = <&cpg CPG_MOD 603>;
2694 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2695 resets = <&cpg 603>;
2696 };
2697
2698 fcpvd1: fcp@fea2f000 {
2699 compatible = "renesas,fcpv";
2700 reg = <0 0xfea2f000 0 0x200>;
2701 clocks = <&cpg CPG_MOD 602>;
2702 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2703 resets = <&cpg 602>;
2704 };
2705
2706 csi20: csi2@fea80000 {
2707 compatible = "renesas,r8a774e1-csi2";
2708 reg = <0 0xfea80000 0 0x10000>;
2709 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2710 clocks = <&cpg CPG_MOD 714>;
2711 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2712 resets = <&cpg 714>;
2713 status = "disabled";
2714
2715 ports {
2716 #address-cells = <1>;
2717 #size-cells = <0>;
2718
2719 port@0 {
2720 reg = <0>;
2721 };
2722
2723 port@1 {
2724 #address-cells = <1>;
2725 #size-cells = <0>;
2726
2727 reg = <1>;
2728
2729 csi20vin0: endpoint@0 {
2730 reg = <0>;
2731 remote-endpoint = <&vin0csi20>;
2732 };
2733 csi20vin1: endpoint@1 {
2734 reg = <1>;
2735 remote-endpoint = <&vin1csi20>;
2736 };
2737 csi20vin2: endpoint@2 {
2738 reg = <2>;
2739 remote-endpoint = <&vin2csi20>;
2740 };
2741 csi20vin3: endpoint@3 {
2742 reg = <3>;
2743 remote-endpoint = <&vin3csi20>;
2744 };
2745 csi20vin4: endpoint@4 {
2746 reg = <4>;
2747 remote-endpoint = <&vin4csi20>;
2748 };
2749 csi20vin5: endpoint@5 {
2750 reg = <5>;
2751 remote-endpoint = <&vin5csi20>;
2752 };
2753 csi20vin6: endpoint@6 {
2754 reg = <6>;
2755 remote-endpoint = <&vin6csi20>;
2756 };
2757 csi20vin7: endpoint@7 {
2758 reg = <7>;
2759 remote-endpoint = <&vin7csi20>;
2760 };
2761 };
2762 };
2763 };
2764
2765 csi40: csi2@feaa0000 {
2766 compatible = "renesas,r8a774e1-csi2";
2767 reg = <0 0xfeaa0000 0 0x10000>;
2768 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2769 clocks = <&cpg CPG_MOD 716>;
2770 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2771 resets = <&cpg 716>;
2772 status = "disabled";
2773
2774 ports {
2775 #address-cells = <1>;
2776 #size-cells = <0>;
2777
2778 port@0 {
2779 reg = <0>;
2780 };
2781
2782 port@1 {
2783 #address-cells = <1>;
2784 #size-cells = <0>;
2785
2786 reg = <1>;
2787
2788 csi40vin0: endpoint@0 {
2789 reg = <0>;
2790 remote-endpoint = <&vin0csi40>;
2791 };
2792 csi40vin1: endpoint@1 {
2793 reg = <1>;
2794 remote-endpoint = <&vin1csi40>;
2795 };
2796 csi40vin2: endpoint@2 {
2797 reg = <2>;
2798 remote-endpoint = <&vin2csi40>;
2799 };
2800 csi40vin3: endpoint@3 {
2801 reg = <3>;
2802 remote-endpoint = <&vin3csi40>;
2803 };
2804 };
2805 };
2806 };
2807
2808 hdmi0: hdmi@fead0000 {
2809 compatible = "renesas,r8a774e1-hdmi",
2810 "renesas,rcar-gen3-hdmi";
2811 reg = <0 0xfead0000 0 0x10000>;
2812 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
2813 clocks = <&cpg CPG_MOD 729>,
2814 <&cpg CPG_CORE R8A774E1_CLK_HDMI>;
2815 clock-names = "iahb", "isfr";
2816 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2817 resets = <&cpg 729>;
2818 status = "disabled";
2819
2820 ports {
2821 #address-cells = <1>;
2822 #size-cells = <0>;
2823
2824 port@0 {
2825 reg = <0>;
2826 dw_hdmi0_in: endpoint {
2827 remote-endpoint = <&du_out_hdmi0>;
2828 };
2829 };
2830 port@1 {
2831 reg = <1>;
2832 };
2833 port@2 {
2834 /* HDMI sound */
2835 reg = <2>;
2836 };
2837 };
2838 };
2839
2840 du: display@feb00000 {
2841 compatible = "renesas,du-r8a774e1";
2842 reg = <0 0xfeb00000 0 0x80000>;
2843 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2844 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2845 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
2846 clocks = <&cpg CPG_MOD 724>,
2847 <&cpg CPG_MOD 723>,
2848 <&cpg CPG_MOD 721>;
2849 clock-names = "du.0", "du.1", "du.3";
2850 resets = <&cpg 724>, <&cpg 722>;
2851 reset-names = "du.0", "du.3";
2852 status = "disabled";
2853
2854 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
2855
2856 ports {
2857 #address-cells = <1>;
2858 #size-cells = <0>;
2859
2860 port@0 {
2861 reg = <0>;
2862 };
2863 port@1 {
2864 reg = <1>;
2865 du_out_hdmi0: endpoint {
2866 remote-endpoint = <&dw_hdmi0_in>;
2867 };
2868 };
2869 port@2 {
2870 reg = <2>;
2871 du_out_lvds0: endpoint {
2872 remote-endpoint = <&lvds0_in>;
2873 };
2874 };
2875 };
2876 };
2877
2878 lvds0: lvds@feb90000 {
2879 compatible = "renesas,r8a774e1-lvds";
2880 reg = <0 0xfeb90000 0 0x14>;
2881 clocks = <&cpg CPG_MOD 727>;
2882 power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
2883 resets = <&cpg 727>;
2884 status = "disabled";
2885
2886 ports {
2887 #address-cells = <1>;
2888 #size-cells = <0>;
2889
2890 port@0 {
2891 reg = <0>;
2892 lvds0_in: endpoint {
2893 remote-endpoint = <&du_out_lvds0>;
2894 };
2895 };
2896 port@1 {
2897 reg = <1>;
2898 };
2899 };
2900 };
2901
2902 prr: chipid@fff00044 {
2903 compatible = "renesas,prr";
2904 reg = <0 0xfff00044 0 4>;
2905 };
2906 };
2907
2908 thermal-zones {
2909 sensor1_thermal: sensor1-thermal {
2910 polling-delay-passive = <250>;
2911 polling-delay = <1000>;
2912 thermal-sensors = <&tsc 0>;
2913 sustainable-power = <6313>;
2914
2915 trips {
2916 sensor1_crit: sensor1-crit {
2917 temperature = <120000>;
2918 hysteresis = <1000>;
2919 type = "critical";
2920 };
2921 };
2922 };
2923
2924 sensor2_thermal: sensor2-thermal {
2925 polling-delay-passive = <250>;
2926 polling-delay = <1000>;
2927 thermal-sensors = <&tsc 1>;
2928 sustainable-power = <6313>;
2929
2930 trips {
2931 sensor2_crit: sensor2-crit {
2932 temperature = <120000>;
2933 hysteresis = <1000>;
2934 type = "critical";
2935 };
2936 };
2937 };
2938
2939 sensor3_thermal: sensor3-thermal {
2940 polling-delay-passive = <250>;
2941 polling-delay = <1000>;
2942 thermal-sensors = <&tsc 2>;
2943 sustainable-power = <6313>;
2944
2945 trips {
2946 target: trip-point1 {
2947 temperature = <100000>;
2948 hysteresis = <1000>;
2949 type = "passive";
2950 };
2951
2952 sensor3_crit: sensor3-crit {
2953 temperature = <120000>;
2954 hysteresis = <1000>;
2955 type = "critical";
2956 };
2957 };
2958
2959 cooling-maps {
2960 map0 {
2961 trip = <&target>;
2962 cooling-device = <&a57_0 0 2>;
2963 contribution = <1024>;
2964 };
2965
2966 map1 {
2967 trip = <&target>;
2968 cooling-device = <&a53_0 0 2>;
2969 contribution = <1024>;
2970 };
2971 };
2972 };
2973 };
2974
2975 timer {
2976 compatible = "arm,armv8-timer";
2977 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2978 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2979 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2980 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2981 };
2982
2983 /* External USB clocks - can be overridden by the board */
2984 usb3s0_clk: usb3s0 {
2985 compatible = "fixed-clock";
2986 #clock-cells = <0>;
2987 clock-frequency = <0>;
2988 };
2989
2990 usb_extal_clk: usb_extal {
2991 compatible = "fixed-clock";
2992 #clock-cells = <0>;
2993 clock-frequency = <0>;
2994 };
2995 };
"Das U-Boot" Source Tree