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[thirdparty/u-boot.git] / src / arm64 / renesas / r8a77960.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for the R-Car M3-W (R8A77960) SoC
4 *
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
6 */
7
8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7796-sysc.h>
11
12 / {
13 compatible = "renesas,r8a7796";
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 /*
18 * The external audio clocks are configured as 0 Hz fixed frequency
19 * clocks by default.
20 * Boards that provide audio clocks should override them.
21 */
22 audio_clk_a: audio_clk_a {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <0>;
26 };
27
28 audio_clk_b: audio_clk_b {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <0>;
32 };
33
34 audio_clk_c: audio_clk_c {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <0>;
38 };
39
40 /* External CAN clock - to be overridden by boards that provide it */
41 can_clk: can {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <0>;
45 };
46
47 cluster0_opp: opp-table-0 {
48 compatible = "operating-points-v2";
49 opp-shared;
50
51 opp-500000000 {
52 opp-hz = /bits/ 64 <500000000>;
53 opp-microvolt = <830000>;
54 clock-latency-ns = <300000>;
55 };
56 opp-1000000000 {
57 opp-hz = /bits/ 64 <1000000000>;
58 opp-microvolt = <830000>;
59 clock-latency-ns = <300000>;
60 };
61 opp-1500000000 {
62 opp-hz = /bits/ 64 <1500000000>;
63 opp-microvolt = <830000>;
64 clock-latency-ns = <300000>;
65 opp-suspend;
66 };
67 opp-1600000000 {
68 opp-hz = /bits/ 64 <1600000000>;
69 opp-microvolt = <900000>;
70 clock-latency-ns = <300000>;
71 };
72 opp-1700000000 {
73 opp-hz = /bits/ 64 <1700000000>;
74 opp-microvolt = <900000>;
75 clock-latency-ns = <300000>;
76 };
77 opp-1800000000 {
78 opp-hz = /bits/ 64 <1800000000>;
79 opp-microvolt = <960000>;
80 clock-latency-ns = <300000>;
81 turbo-mode;
82 };
83 };
84
85 cluster1_opp: opp-table-1 {
86 compatible = "operating-points-v2";
87 opp-shared;
88
89 opp-800000000 {
90 opp-hz = /bits/ 64 <800000000>;
91 opp-microvolt = <820000>;
92 clock-latency-ns = <300000>;
93 };
94 opp-1000000000 {
95 opp-hz = /bits/ 64 <1000000000>;
96 opp-microvolt = <820000>;
97 clock-latency-ns = <300000>;
98 };
99 opp-1200000000 {
100 opp-hz = /bits/ 64 <1200000000>;
101 opp-microvolt = <820000>;
102 clock-latency-ns = <300000>;
103 };
104 opp-1300000000 {
105 opp-hz = /bits/ 64 <1300000000>;
106 opp-microvolt = <820000>;
107 clock-latency-ns = <300000>;
108 turbo-mode;
109 };
110 };
111
112 cpus {
113 #address-cells = <1>;
114 #size-cells = <0>;
115
116 cpu-map {
117 cluster0 {
118 core0 {
119 cpu = <&a57_0>;
120 };
121 core1 {
122 cpu = <&a57_1>;
123 };
124 };
125
126 cluster1 {
127 core0 {
128 cpu = <&a53_0>;
129 };
130 core1 {
131 cpu = <&a53_1>;
132 };
133 core2 {
134 cpu = <&a53_2>;
135 };
136 core3 {
137 cpu = <&a53_3>;
138 };
139 };
140 };
141
142 a57_0: cpu@0 {
143 compatible = "arm,cortex-a57";
144 reg = <0x0>;
145 device_type = "cpu";
146 power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
147 next-level-cache = <&L2_CA57>;
148 enable-method = "psci";
149 cpu-idle-states = <&CPU_SLEEP_0>;
150 dynamic-power-coefficient = <854>;
151 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
152 operating-points-v2 = <&cluster0_opp>;
153 capacity-dmips-mhz = <1024>;
154 #cooling-cells = <2>;
155 };
156
157 a57_1: cpu@1 {
158 compatible = "arm,cortex-a57";
159 reg = <0x1>;
160 device_type = "cpu";
161 power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
162 next-level-cache = <&L2_CA57>;
163 enable-method = "psci";
164 cpu-idle-states = <&CPU_SLEEP_0>;
165 clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
166 operating-points-v2 = <&cluster0_opp>;
167 capacity-dmips-mhz = <1024>;
168 #cooling-cells = <2>;
169 };
170
171 a53_0: cpu@100 {
172 compatible = "arm,cortex-a53";
173 reg = <0x100>;
174 device_type = "cpu";
175 power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
176 next-level-cache = <&L2_CA53>;
177 enable-method = "psci";
178 cpu-idle-states = <&CPU_SLEEP_1>;
179 #cooling-cells = <2>;
180 dynamic-power-coefficient = <277>;
181 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
182 operating-points-v2 = <&cluster1_opp>;
183 capacity-dmips-mhz = <535>;
184 };
185
186 a53_1: cpu@101 {
187 compatible = "arm,cortex-a53";
188 reg = <0x101>;
189 device_type = "cpu";
190 power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
191 next-level-cache = <&L2_CA53>;
192 enable-method = "psci";
193 cpu-idle-states = <&CPU_SLEEP_1>;
194 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
195 operating-points-v2 = <&cluster1_opp>;
196 capacity-dmips-mhz = <535>;
197 };
198
199 a53_2: cpu@102 {
200 compatible = "arm,cortex-a53";
201 reg = <0x102>;
202 device_type = "cpu";
203 power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
204 next-level-cache = <&L2_CA53>;
205 enable-method = "psci";
206 cpu-idle-states = <&CPU_SLEEP_1>;
207 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
208 operating-points-v2 = <&cluster1_opp>;
209 capacity-dmips-mhz = <535>;
210 };
211
212 a53_3: cpu@103 {
213 compatible = "arm,cortex-a53";
214 reg = <0x103>;
215 device_type = "cpu";
216 power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
217 next-level-cache = <&L2_CA53>;
218 enable-method = "psci";
219 cpu-idle-states = <&CPU_SLEEP_1>;
220 clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
221 operating-points-v2 = <&cluster1_opp>;
222 capacity-dmips-mhz = <535>;
223 };
224
225 L2_CA57: cache-controller-0 {
226 compatible = "cache";
227 power-domains = <&sysc R8A7796_PD_CA57_SCU>;
228 cache-unified;
229 cache-level = <2>;
230 };
231
232 L2_CA53: cache-controller-1 {
233 compatible = "cache";
234 power-domains = <&sysc R8A7796_PD_CA53_SCU>;
235 cache-unified;
236 cache-level = <2>;
237 };
238
239 idle-states {
240 entry-method = "psci";
241
242 CPU_SLEEP_0: cpu-sleep-0 {
243 compatible = "arm,idle-state";
244 arm,psci-suspend-param = <0x0010000>;
245 local-timer-stop;
246 entry-latency-us = <400>;
247 exit-latency-us = <500>;
248 min-residency-us = <4000>;
249 };
250
251 CPU_SLEEP_1: cpu-sleep-1 {
252 compatible = "arm,idle-state";
253 arm,psci-suspend-param = <0x0010000>;
254 local-timer-stop;
255 entry-latency-us = <700>;
256 exit-latency-us = <700>;
257 min-residency-us = <5000>;
258 };
259 };
260 };
261
262 extal_clk: extal {
263 compatible = "fixed-clock";
264 #clock-cells = <0>;
265 /* This value must be overridden by the board */
266 clock-frequency = <0>;
267 };
268
269 extalr_clk: extalr {
270 compatible = "fixed-clock";
271 #clock-cells = <0>;
272 /* This value must be overridden by the board */
273 clock-frequency = <0>;
274 };
275
276 /* External PCIe clock - can be overridden by the board */
277 pcie_bus_clk: pcie_bus {
278 compatible = "fixed-clock";
279 #clock-cells = <0>;
280 clock-frequency = <0>;
281 };
282
283 pmu_a53 {
284 compatible = "arm,cortex-a53-pmu";
285 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
286 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
287 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
288 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
289 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
290 };
291
292 pmu_a57 {
293 compatible = "arm,cortex-a57-pmu";
294 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
295 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
296 interrupt-affinity = <&a57_0>, <&a57_1>;
297 };
298
299 psci {
300 compatible = "arm,psci-1.0", "arm,psci-0.2";
301 method = "smc";
302 };
303
304 /* External SCIF clock - to be overridden by boards that provide it */
305 scif_clk: scif {
306 compatible = "fixed-clock";
307 #clock-cells = <0>;
308 clock-frequency = <0>;
309 };
310
311 soc {
312 compatible = "simple-bus";
313 interrupt-parent = <&gic>;
314 #address-cells = <2>;
315 #size-cells = <2>;
316 ranges;
317
318 rwdt: watchdog@e6020000 {
319 compatible = "renesas,r8a7796-wdt",
320 "renesas,rcar-gen3-wdt";
321 reg = <0 0xe6020000 0 0x0c>;
322 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&cpg CPG_MOD 402>;
324 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
325 resets = <&cpg 402>;
326 status = "disabled";
327 };
328
329 gpio0: gpio@e6050000 {
330 compatible = "renesas,gpio-r8a7796",
331 "renesas,rcar-gen3-gpio";
332 reg = <0 0xe6050000 0 0x50>;
333 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
334 #gpio-cells = <2>;
335 gpio-controller;
336 gpio-ranges = <&pfc 0 0 16>;
337 #interrupt-cells = <2>;
338 interrupt-controller;
339 clocks = <&cpg CPG_MOD 912>;
340 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
341 resets = <&cpg 912>;
342 };
343
344 gpio1: gpio@e6051000 {
345 compatible = "renesas,gpio-r8a7796",
346 "renesas,rcar-gen3-gpio";
347 reg = <0 0xe6051000 0 0x50>;
348 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
349 #gpio-cells = <2>;
350 gpio-controller;
351 gpio-ranges = <&pfc 0 32 29>;
352 #interrupt-cells = <2>;
353 interrupt-controller;
354 clocks = <&cpg CPG_MOD 911>;
355 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
356 resets = <&cpg 911>;
357 };
358
359 gpio2: gpio@e6052000 {
360 compatible = "renesas,gpio-r8a7796",
361 "renesas,rcar-gen3-gpio";
362 reg = <0 0xe6052000 0 0x50>;
363 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
364 #gpio-cells = <2>;
365 gpio-controller;
366 gpio-ranges = <&pfc 0 64 15>;
367 #interrupt-cells = <2>;
368 interrupt-controller;
369 clocks = <&cpg CPG_MOD 910>;
370 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
371 resets = <&cpg 910>;
372 };
373
374 gpio3: gpio@e6053000 {
375 compatible = "renesas,gpio-r8a7796",
376 "renesas,rcar-gen3-gpio";
377 reg = <0 0xe6053000 0 0x50>;
378 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
379 #gpio-cells = <2>;
380 gpio-controller;
381 gpio-ranges = <&pfc 0 96 16>;
382 #interrupt-cells = <2>;
383 interrupt-controller;
384 clocks = <&cpg CPG_MOD 909>;
385 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
386 resets = <&cpg 909>;
387 };
388
389 gpio4: gpio@e6054000 {
390 compatible = "renesas,gpio-r8a7796",
391 "renesas,rcar-gen3-gpio";
392 reg = <0 0xe6054000 0 0x50>;
393 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
394 #gpio-cells = <2>;
395 gpio-controller;
396 gpio-ranges = <&pfc 0 128 18>;
397 #interrupt-cells = <2>;
398 interrupt-controller;
399 clocks = <&cpg CPG_MOD 908>;
400 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
401 resets = <&cpg 908>;
402 };
403
404 gpio5: gpio@e6055000 {
405 compatible = "renesas,gpio-r8a7796",
406 "renesas,rcar-gen3-gpio";
407 reg = <0 0xe6055000 0 0x50>;
408 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
409 #gpio-cells = <2>;
410 gpio-controller;
411 gpio-ranges = <&pfc 0 160 26>;
412 #interrupt-cells = <2>;
413 interrupt-controller;
414 clocks = <&cpg CPG_MOD 907>;
415 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
416 resets = <&cpg 907>;
417 };
418
419 gpio6: gpio@e6055400 {
420 compatible = "renesas,gpio-r8a7796",
421 "renesas,rcar-gen3-gpio";
422 reg = <0 0xe6055400 0 0x50>;
423 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
424 #gpio-cells = <2>;
425 gpio-controller;
426 gpio-ranges = <&pfc 0 192 32>;
427 #interrupt-cells = <2>;
428 interrupt-controller;
429 clocks = <&cpg CPG_MOD 906>;
430 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
431 resets = <&cpg 906>;
432 };
433
434 gpio7: gpio@e6055800 {
435 compatible = "renesas,gpio-r8a7796",
436 "renesas,rcar-gen3-gpio";
437 reg = <0 0xe6055800 0 0x50>;
438 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
439 #gpio-cells = <2>;
440 gpio-controller;
441 gpio-ranges = <&pfc 0 224 4>;
442 #interrupt-cells = <2>;
443 interrupt-controller;
444 clocks = <&cpg CPG_MOD 905>;
445 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
446 resets = <&cpg 905>;
447 };
448
449 pfc: pinctrl@e6060000 {
450 compatible = "renesas,pfc-r8a7796";
451 reg = <0 0xe6060000 0 0x50c>;
452 };
453
454 cmt0: timer@e60f0000 {
455 compatible = "renesas,r8a7796-cmt0",
456 "renesas,rcar-gen3-cmt0";
457 reg = <0 0xe60f0000 0 0x1004>;
458 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&cpg CPG_MOD 303>;
461 clock-names = "fck";
462 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
463 resets = <&cpg 303>;
464 status = "disabled";
465 };
466
467 cmt1: timer@e6130000 {
468 compatible = "renesas,r8a7796-cmt1",
469 "renesas,rcar-gen3-cmt1";
470 reg = <0 0xe6130000 0 0x1004>;
471 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&cpg CPG_MOD 302>;
480 clock-names = "fck";
481 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
482 resets = <&cpg 302>;
483 status = "disabled";
484 };
485
486 cmt2: timer@e6140000 {
487 compatible = "renesas,r8a7796-cmt1",
488 "renesas,rcar-gen3-cmt1";
489 reg = <0 0xe6140000 0 0x1004>;
490 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&cpg CPG_MOD 301>;
499 clock-names = "fck";
500 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
501 resets = <&cpg 301>;
502 status = "disabled";
503 };
504
505 cmt3: timer@e6148000 {
506 compatible = "renesas,r8a7796-cmt1",
507 "renesas,rcar-gen3-cmt1";
508 reg = <0 0xe6148000 0 0x1004>;
509 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&cpg CPG_MOD 300>;
518 clock-names = "fck";
519 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
520 resets = <&cpg 300>;
521 status = "disabled";
522 };
523
524 cpg: clock-controller@e6150000 {
525 compatible = "renesas,r8a7796-cpg-mssr";
526 reg = <0 0xe6150000 0 0x1000>;
527 clocks = <&extal_clk>, <&extalr_clk>;
528 clock-names = "extal", "extalr";
529 #clock-cells = <2>;
530 #power-domain-cells = <0>;
531 #reset-cells = <1>;
532 };
533
534 rst: reset-controller@e6160000 {
535 compatible = "renesas,r8a7796-rst";
536 reg = <0 0xe6160000 0 0x0200>;
537 };
538
539 sysc: system-controller@e6180000 {
540 compatible = "renesas,r8a7796-sysc";
541 reg = <0 0xe6180000 0 0x0400>;
542 #power-domain-cells = <1>;
543 };
544
545 tsc: thermal@e6198000 {
546 compatible = "renesas,r8a7796-thermal";
547 reg = <0 0xe6198000 0 0x100>,
548 <0 0xe61a0000 0 0x100>,
549 <0 0xe61a8000 0 0x100>;
550 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&cpg CPG_MOD 522>;
554 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
555 resets = <&cpg 522>;
556 #thermal-sensor-cells = <1>;
557 };
558
559 intc_ex: interrupt-controller@e61c0000 {
560 compatible = "renesas,intc-ex-r8a7796", "renesas,irqc";
561 #interrupt-cells = <2>;
562 interrupt-controller;
563 reg = <0 0xe61c0000 0 0x200>;
564 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&cpg CPG_MOD 407>;
571 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
572 resets = <&cpg 407>;
573 };
574
575 tmu0: timer@e61e0000 {
576 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
577 reg = <0 0xe61e0000 0 0x30>;
578 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&cpg CPG_MOD 125>;
582 clock-names = "fck";
583 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
584 resets = <&cpg 125>;
585 status = "disabled";
586 };
587
588 tmu1: timer@e6fc0000 {
589 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
590 reg = <0 0xe6fc0000 0 0x30>;
591 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&cpg CPG_MOD 124>;
595 clock-names = "fck";
596 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
597 resets = <&cpg 124>;
598 status = "disabled";
599 };
600
601 tmu2: timer@e6fd0000 {
602 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
603 reg = <0 0xe6fd0000 0 0x30>;
604 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&cpg CPG_MOD 123>;
608 clock-names = "fck";
609 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
610 resets = <&cpg 123>;
611 status = "disabled";
612 };
613
614 tmu3: timer@e6fe0000 {
615 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
616 reg = <0 0xe6fe0000 0 0x30>;
617 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&cpg CPG_MOD 122>;
621 clock-names = "fck";
622 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
623 resets = <&cpg 122>;
624 status = "disabled";
625 };
626
627 tmu4: timer@ffc00000 {
628 compatible = "renesas,tmu-r8a7796", "renesas,tmu";
629 reg = <0 0xffc00000 0 0x30>;
630 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&cpg CPG_MOD 121>;
634 clock-names = "fck";
635 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
636 resets = <&cpg 121>;
637 status = "disabled";
638 };
639
640 i2c0: i2c@e6500000 {
641 #address-cells = <1>;
642 #size-cells = <0>;
643 compatible = "renesas,i2c-r8a7796",
644 "renesas,rcar-gen3-i2c";
645 reg = <0 0xe6500000 0 0x40>;
646 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&cpg CPG_MOD 931>;
648 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
649 resets = <&cpg 931>;
650 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
651 <&dmac2 0x91>, <&dmac2 0x90>;
652 dma-names = "tx", "rx", "tx", "rx";
653 i2c-scl-internal-delay-ns = <110>;
654 status = "disabled";
655 };
656
657 i2c1: i2c@e6508000 {
658 #address-cells = <1>;
659 #size-cells = <0>;
660 compatible = "renesas,i2c-r8a7796",
661 "renesas,rcar-gen3-i2c";
662 reg = <0 0xe6508000 0 0x40>;
663 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&cpg CPG_MOD 930>;
665 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
666 resets = <&cpg 930>;
667 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
668 <&dmac2 0x93>, <&dmac2 0x92>;
669 dma-names = "tx", "rx", "tx", "rx";
670 i2c-scl-internal-delay-ns = <6>;
671 status = "disabled";
672 };
673
674 i2c2: i2c@e6510000 {
675 #address-cells = <1>;
676 #size-cells = <0>;
677 compatible = "renesas,i2c-r8a7796",
678 "renesas,rcar-gen3-i2c";
679 reg = <0 0xe6510000 0 0x40>;
680 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&cpg CPG_MOD 929>;
682 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
683 resets = <&cpg 929>;
684 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
685 <&dmac2 0x95>, <&dmac2 0x94>;
686 dma-names = "tx", "rx", "tx", "rx";
687 i2c-scl-internal-delay-ns = <6>;
688 status = "disabled";
689 };
690
691 i2c3: i2c@e66d0000 {
692 #address-cells = <1>;
693 #size-cells = <0>;
694 compatible = "renesas,i2c-r8a7796",
695 "renesas,rcar-gen3-i2c";
696 reg = <0 0xe66d0000 0 0x40>;
697 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&cpg CPG_MOD 928>;
699 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
700 resets = <&cpg 928>;
701 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
702 dma-names = "tx", "rx";
703 i2c-scl-internal-delay-ns = <110>;
704 status = "disabled";
705 };
706
707 i2c4: i2c@e66d8000 {
708 #address-cells = <1>;
709 #size-cells = <0>;
710 compatible = "renesas,i2c-r8a7796",
711 "renesas,rcar-gen3-i2c";
712 reg = <0 0xe66d8000 0 0x40>;
713 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&cpg CPG_MOD 927>;
715 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
716 resets = <&cpg 927>;
717 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
718 dma-names = "tx", "rx";
719 i2c-scl-internal-delay-ns = <110>;
720 status = "disabled";
721 };
722
723 i2c5: i2c@e66e0000 {
724 #address-cells = <1>;
725 #size-cells = <0>;
726 compatible = "renesas,i2c-r8a7796",
727 "renesas,rcar-gen3-i2c";
728 reg = <0 0xe66e0000 0 0x40>;
729 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&cpg CPG_MOD 919>;
731 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
732 resets = <&cpg 919>;
733 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
734 dma-names = "tx", "rx";
735 i2c-scl-internal-delay-ns = <110>;
736 status = "disabled";
737 };
738
739 i2c6: i2c@e66e8000 {
740 #address-cells = <1>;
741 #size-cells = <0>;
742 compatible = "renesas,i2c-r8a7796",
743 "renesas,rcar-gen3-i2c";
744 reg = <0 0xe66e8000 0 0x40>;
745 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
746 clocks = <&cpg CPG_MOD 918>;
747 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
748 resets = <&cpg 918>;
749 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
750 dma-names = "tx", "rx";
751 i2c-scl-internal-delay-ns = <6>;
752 status = "disabled";
753 };
754
755 i2c_dvfs: i2c@e60b0000 {
756 #address-cells = <1>;
757 #size-cells = <0>;
758 compatible = "renesas,iic-r8a7796",
759 "renesas,rcar-gen3-iic",
760 "renesas,rmobile-iic";
761 reg = <0 0xe60b0000 0 0x425>;
762 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&cpg CPG_MOD 926>;
764 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
765 resets = <&cpg 926>;
766 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
767 dma-names = "tx", "rx";
768 status = "disabled";
769 };
770
771 hscif0: serial@e6540000 {
772 compatible = "renesas,hscif-r8a7796",
773 "renesas,rcar-gen3-hscif",
774 "renesas,hscif";
775 reg = <0 0xe6540000 0 0x60>;
776 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
777 clocks = <&cpg CPG_MOD 520>,
778 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
779 <&scif_clk>;
780 clock-names = "fck", "brg_int", "scif_clk";
781 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
782 <&dmac2 0x31>, <&dmac2 0x30>;
783 dma-names = "tx", "rx", "tx", "rx";
784 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
785 resets = <&cpg 520>;
786 status = "disabled";
787 };
788
789 hscif1: serial@e6550000 {
790 compatible = "renesas,hscif-r8a7796",
791 "renesas,rcar-gen3-hscif",
792 "renesas,hscif";
793 reg = <0 0xe6550000 0 0x60>;
794 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
795 clocks = <&cpg CPG_MOD 519>,
796 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
797 <&scif_clk>;
798 clock-names = "fck", "brg_int", "scif_clk";
799 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
800 <&dmac2 0x33>, <&dmac2 0x32>;
801 dma-names = "tx", "rx", "tx", "rx";
802 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
803 resets = <&cpg 519>;
804 status = "disabled";
805 };
806
807 hscif2: serial@e6560000 {
808 compatible = "renesas,hscif-r8a7796",
809 "renesas,rcar-gen3-hscif",
810 "renesas,hscif";
811 reg = <0 0xe6560000 0 0x60>;
812 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&cpg CPG_MOD 518>,
814 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
815 <&scif_clk>;
816 clock-names = "fck", "brg_int", "scif_clk";
817 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
818 <&dmac2 0x35>, <&dmac2 0x34>;
819 dma-names = "tx", "rx", "tx", "rx";
820 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
821 resets = <&cpg 518>;
822 status = "disabled";
823 };
824
825 hscif3: serial@e66a0000 {
826 compatible = "renesas,hscif-r8a7796",
827 "renesas,rcar-gen3-hscif",
828 "renesas,hscif";
829 reg = <0 0xe66a0000 0 0x60>;
830 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
831 clocks = <&cpg CPG_MOD 517>,
832 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
833 <&scif_clk>;
834 clock-names = "fck", "brg_int", "scif_clk";
835 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
836 dma-names = "tx", "rx";
837 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
838 resets = <&cpg 517>;
839 status = "disabled";
840 };
841
842 hscif4: serial@e66b0000 {
843 compatible = "renesas,hscif-r8a7796",
844 "renesas,rcar-gen3-hscif",
845 "renesas,hscif";
846 reg = <0 0xe66b0000 0 0x60>;
847 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&cpg CPG_MOD 516>,
849 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
850 <&scif_clk>;
851 clock-names = "fck", "brg_int", "scif_clk";
852 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
853 dma-names = "tx", "rx";
854 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
855 resets = <&cpg 516>;
856 status = "disabled";
857 };
858
859 hsusb: usb@e6590000 {
860 compatible = "renesas,usbhs-r8a7796",
861 "renesas,rcar-gen3-usbhs";
862 reg = <0 0xe6590000 0 0x200>;
863 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
864 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
865 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
866 <&usb_dmac1 0>, <&usb_dmac1 1>;
867 dma-names = "ch0", "ch1", "ch2", "ch3";
868 renesas,buswait = <11>;
869 phys = <&usb2_phy0 3>;
870 phy-names = "usb";
871 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
872 resets = <&cpg 704>, <&cpg 703>;
873 status = "disabled";
874 };
875
876 usb_dmac0: dma-controller@e65a0000 {
877 compatible = "renesas,r8a7796-usb-dmac",
878 "renesas,usb-dmac";
879 reg = <0 0xe65a0000 0 0x100>;
880 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
881 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
882 interrupt-names = "ch0", "ch1";
883 clocks = <&cpg CPG_MOD 330>;
884 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
885 resets = <&cpg 330>;
886 #dma-cells = <1>;
887 dma-channels = <2>;
888 };
889
890 usb_dmac1: dma-controller@e65b0000 {
891 compatible = "renesas,r8a7796-usb-dmac",
892 "renesas,usb-dmac";
893 reg = <0 0xe65b0000 0 0x100>;
894 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
895 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
896 interrupt-names = "ch0", "ch1";
897 clocks = <&cpg CPG_MOD 331>;
898 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
899 resets = <&cpg 331>;
900 #dma-cells = <1>;
901 dma-channels = <2>;
902 };
903
904 usb3_phy0: usb-phy@e65ee000 {
905 compatible = "renesas,r8a7796-usb3-phy",
906 "renesas,rcar-gen3-usb3-phy";
907 reg = <0 0xe65ee000 0 0x90>;
908 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
909 <&usb_extal_clk>;
910 clock-names = "usb3-if", "usb3s_clk", "usb_extal";
911 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
912 resets = <&cpg 328>;
913 #phy-cells = <0>;
914 status = "disabled";
915 };
916
917 arm_cc630p: crypto@e6601000 {
918 compatible = "arm,cryptocell-630p-ree";
919 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
920 reg = <0x0 0xe6601000 0 0x1000>;
921 clocks = <&cpg CPG_MOD 229>;
922 resets = <&cpg 229>;
923 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
924 };
925
926 dmac0: dma-controller@e6700000 {
927 compatible = "renesas,dmac-r8a7796",
928 "renesas,rcar-dmac";
929 reg = <0 0xe6700000 0 0x10000>;
930 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
933 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
934 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
947 interrupt-names = "error",
948 "ch0", "ch1", "ch2", "ch3",
949 "ch4", "ch5", "ch6", "ch7",
950 "ch8", "ch9", "ch10", "ch11",
951 "ch12", "ch13", "ch14", "ch15";
952 clocks = <&cpg CPG_MOD 219>;
953 clock-names = "fck";
954 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
955 resets = <&cpg 219>;
956 #dma-cells = <1>;
957 dma-channels = <16>;
958 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
959 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
960 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
961 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
962 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
963 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
964 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
965 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
966 };
967
968 dmac1: dma-controller@e7300000 {
969 compatible = "renesas,dmac-r8a7796",
970 "renesas,rcar-dmac";
971 reg = <0 0xe7300000 0 0x10000>;
972 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
975 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
976 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
977 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
978 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
979 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
989 interrupt-names = "error",
990 "ch0", "ch1", "ch2", "ch3",
991 "ch4", "ch5", "ch6", "ch7",
992 "ch8", "ch9", "ch10", "ch11",
993 "ch12", "ch13", "ch14", "ch15";
994 clocks = <&cpg CPG_MOD 218>;
995 clock-names = "fck";
996 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
997 resets = <&cpg 218>;
998 #dma-cells = <1>;
999 dma-channels = <16>;
1000 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1001 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
1002 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
1003 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
1004 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
1005 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
1006 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
1007 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
1008 };
1009
1010 dmac2: dma-controller@e7310000 {
1011 compatible = "renesas,dmac-r8a7796",
1012 "renesas,rcar-dmac";
1013 reg = <0 0xe7310000 0 0x10000>;
1014 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1015 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1016 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1017 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1018 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
1019 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1020 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
1021 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1022 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1023 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
1024 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
1025 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
1026 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
1027 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
1028 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
1029 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
1030 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
1031 interrupt-names = "error",
1032 "ch0", "ch1", "ch2", "ch3",
1033 "ch4", "ch5", "ch6", "ch7",
1034 "ch8", "ch9", "ch10", "ch11",
1035 "ch12", "ch13", "ch14", "ch15";
1036 clocks = <&cpg CPG_MOD 217>;
1037 clock-names = "fck";
1038 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1039 resets = <&cpg 217>;
1040 #dma-cells = <1>;
1041 dma-channels = <16>;
1042 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
1043 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
1044 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
1045 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
1046 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
1047 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
1048 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
1049 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
1050 };
1051
1052 ipmmu_ds0: iommu@e6740000 {
1053 compatible = "renesas,ipmmu-r8a7796";
1054 reg = <0 0xe6740000 0 0x1000>;
1055 renesas,ipmmu-main = <&ipmmu_mm 0>;
1056 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1057 #iommu-cells = <1>;
1058 };
1059
1060 ipmmu_ds1: iommu@e7740000 {
1061 compatible = "renesas,ipmmu-r8a7796";
1062 reg = <0 0xe7740000 0 0x1000>;
1063 renesas,ipmmu-main = <&ipmmu_mm 1>;
1064 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1065 #iommu-cells = <1>;
1066 };
1067
1068 ipmmu_hc: iommu@e6570000 {
1069 compatible = "renesas,ipmmu-r8a7796";
1070 reg = <0 0xe6570000 0 0x1000>;
1071 renesas,ipmmu-main = <&ipmmu_mm 2>;
1072 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1073 #iommu-cells = <1>;
1074 };
1075
1076 ipmmu_ir: iommu@ff8b0000 {
1077 compatible = "renesas,ipmmu-r8a7796";
1078 reg = <0 0xff8b0000 0 0x1000>;
1079 renesas,ipmmu-main = <&ipmmu_mm 3>;
1080 power-domains = <&sysc R8A7796_PD_A3IR>;
1081 #iommu-cells = <1>;
1082 };
1083
1084 ipmmu_mm: iommu@e67b0000 {
1085 compatible = "renesas,ipmmu-r8a7796";
1086 reg = <0 0xe67b0000 0 0x1000>;
1087 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1088 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1089 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1090 #iommu-cells = <1>;
1091 };
1092
1093 ipmmu_mp: iommu@ec670000 {
1094 compatible = "renesas,ipmmu-r8a7796";
1095 reg = <0 0xec670000 0 0x1000>;
1096 renesas,ipmmu-main = <&ipmmu_mm 4>;
1097 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1098 #iommu-cells = <1>;
1099 };
1100
1101 ipmmu_pv0: iommu@fd800000 {
1102 compatible = "renesas,ipmmu-r8a7796";
1103 reg = <0 0xfd800000 0 0x1000>;
1104 renesas,ipmmu-main = <&ipmmu_mm 5>;
1105 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1106 #iommu-cells = <1>;
1107 };
1108
1109 ipmmu_pv1: iommu@fd950000 {
1110 compatible = "renesas,ipmmu-r8a7796";
1111 reg = <0 0xfd950000 0 0x1000>;
1112 renesas,ipmmu-main = <&ipmmu_mm 6>;
1113 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1114 #iommu-cells = <1>;
1115 };
1116
1117 ipmmu_rt: iommu@ffc80000 {
1118 compatible = "renesas,ipmmu-r8a7796";
1119 reg = <0 0xffc80000 0 0x1000>;
1120 renesas,ipmmu-main = <&ipmmu_mm 7>;
1121 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1122 #iommu-cells = <1>;
1123 };
1124
1125 ipmmu_vc0: iommu@fe6b0000 {
1126 compatible = "renesas,ipmmu-r8a7796";
1127 reg = <0 0xfe6b0000 0 0x1000>;
1128 renesas,ipmmu-main = <&ipmmu_mm 8>;
1129 power-domains = <&sysc R8A7796_PD_A3VC>;
1130 #iommu-cells = <1>;
1131 };
1132
1133 ipmmu_vi0: iommu@febd0000 {
1134 compatible = "renesas,ipmmu-r8a7796";
1135 reg = <0 0xfebd0000 0 0x1000>;
1136 renesas,ipmmu-main = <&ipmmu_mm 9>;
1137 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1138 #iommu-cells = <1>;
1139 };
1140
1141 avb: ethernet@e6800000 {
1142 compatible = "renesas,etheravb-r8a7796",
1143 "renesas,etheravb-rcar-gen3";
1144 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1145 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1146 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1147 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1148 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1149 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1150 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1151 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1152 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1153 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1154 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1155 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1156 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1157 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1158 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
1159 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1160 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
1161 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
1162 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1163 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1164 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1165 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1166 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1167 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1168 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
1169 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1170 interrupt-names = "ch0", "ch1", "ch2", "ch3",
1171 "ch4", "ch5", "ch6", "ch7",
1172 "ch8", "ch9", "ch10", "ch11",
1173 "ch12", "ch13", "ch14", "ch15",
1174 "ch16", "ch17", "ch18", "ch19",
1175 "ch20", "ch21", "ch22", "ch23",
1176 "ch24";
1177 clocks = <&cpg CPG_MOD 812>;
1178 clock-names = "fck";
1179 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1180 resets = <&cpg 812>;
1181 phy-mode = "rgmii";
1182 rx-internal-delay-ps = <0>;
1183 tx-internal-delay-ps = <0>;
1184 iommus = <&ipmmu_ds0 16>;
1185 #address-cells = <1>;
1186 #size-cells = <0>;
1187 status = "disabled";
1188 };
1189
1190 can0: can@e6c30000 {
1191 compatible = "renesas,can-r8a7796",
1192 "renesas,rcar-gen3-can";
1193 reg = <0 0xe6c30000 0 0x1000>;
1194 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1195 clocks = <&cpg CPG_MOD 916>,
1196 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1197 <&can_clk>;
1198 clock-names = "clkp1", "clkp2", "can_clk";
1199 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1200 assigned-clock-rates = <40000000>;
1201 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1202 resets = <&cpg 916>;
1203 status = "disabled";
1204 };
1205
1206 can1: can@e6c38000 {
1207 compatible = "renesas,can-r8a7796",
1208 "renesas,rcar-gen3-can";
1209 reg = <0 0xe6c38000 0 0x1000>;
1210 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1211 clocks = <&cpg CPG_MOD 915>,
1212 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1213 <&can_clk>;
1214 clock-names = "clkp1", "clkp2", "can_clk";
1215 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1216 assigned-clock-rates = <40000000>;
1217 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1218 resets = <&cpg 915>;
1219 status = "disabled";
1220 };
1221
1222 canfd: can@e66c0000 {
1223 compatible = "renesas,r8a7796-canfd",
1224 "renesas,rcar-gen3-canfd";
1225 reg = <0 0xe66c0000 0 0x8000>;
1226 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1227 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1228 interrupt-names = "ch_int", "g_int";
1229 clocks = <&cpg CPG_MOD 914>,
1230 <&cpg CPG_CORE R8A7796_CLK_CANFD>,
1231 <&can_clk>;
1232 clock-names = "fck", "canfd", "can_clk";
1233 assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
1234 assigned-clock-rates = <40000000>;
1235 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1236 resets = <&cpg 914>;
1237 status = "disabled";
1238
1239 channel0 {
1240 status = "disabled";
1241 };
1242
1243 channel1 {
1244 status = "disabled";
1245 };
1246 };
1247
1248 pwm0: pwm@e6e30000 {
1249 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1250 reg = <0 0xe6e30000 0 8>;
1251 #pwm-cells = <2>;
1252 clocks = <&cpg CPG_MOD 523>;
1253 resets = <&cpg 523>;
1254 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1255 status = "disabled";
1256 };
1257
1258 pwm1: pwm@e6e31000 {
1259 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1260 reg = <0 0xe6e31000 0 8>;
1261 #pwm-cells = <2>;
1262 clocks = <&cpg CPG_MOD 523>;
1263 resets = <&cpg 523>;
1264 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1265 status = "disabled";
1266 };
1267
1268 pwm2: pwm@e6e32000 {
1269 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1270 reg = <0 0xe6e32000 0 8>;
1271 #pwm-cells = <2>;
1272 clocks = <&cpg CPG_MOD 523>;
1273 resets = <&cpg 523>;
1274 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1275 status = "disabled";
1276 };
1277
1278 pwm3: pwm@e6e33000 {
1279 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1280 reg = <0 0xe6e33000 0 8>;
1281 #pwm-cells = <2>;
1282 clocks = <&cpg CPG_MOD 523>;
1283 resets = <&cpg 523>;
1284 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1285 status = "disabled";
1286 };
1287
1288 pwm4: pwm@e6e34000 {
1289 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1290 reg = <0 0xe6e34000 0 8>;
1291 #pwm-cells = <2>;
1292 clocks = <&cpg CPG_MOD 523>;
1293 resets = <&cpg 523>;
1294 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1295 status = "disabled";
1296 };
1297
1298 pwm5: pwm@e6e35000 {
1299 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1300 reg = <0 0xe6e35000 0 8>;
1301 #pwm-cells = <2>;
1302 clocks = <&cpg CPG_MOD 523>;
1303 resets = <&cpg 523>;
1304 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1305 status = "disabled";
1306 };
1307
1308 pwm6: pwm@e6e36000 {
1309 compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
1310 reg = <0 0xe6e36000 0 8>;
1311 #pwm-cells = <2>;
1312 clocks = <&cpg CPG_MOD 523>;
1313 resets = <&cpg 523>;
1314 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1315 status = "disabled";
1316 };
1317
1318 scif0: serial@e6e60000 {
1319 compatible = "renesas,scif-r8a7796",
1320 "renesas,rcar-gen3-scif", "renesas,scif";
1321 reg = <0 0xe6e60000 0 64>;
1322 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1323 clocks = <&cpg CPG_MOD 207>,
1324 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1325 <&scif_clk>;
1326 clock-names = "fck", "brg_int", "scif_clk";
1327 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1328 <&dmac2 0x51>, <&dmac2 0x50>;
1329 dma-names = "tx", "rx", "tx", "rx";
1330 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1331 resets = <&cpg 207>;
1332 status = "disabled";
1333 };
1334
1335 scif1: serial@e6e68000 {
1336 compatible = "renesas,scif-r8a7796",
1337 "renesas,rcar-gen3-scif", "renesas,scif";
1338 reg = <0 0xe6e68000 0 64>;
1339 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1340 clocks = <&cpg CPG_MOD 206>,
1341 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1342 <&scif_clk>;
1343 clock-names = "fck", "brg_int", "scif_clk";
1344 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1345 <&dmac2 0x53>, <&dmac2 0x52>;
1346 dma-names = "tx", "rx", "tx", "rx";
1347 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1348 resets = <&cpg 206>;
1349 status = "disabled";
1350 };
1351
1352 scif2: serial@e6e88000 {
1353 compatible = "renesas,scif-r8a7796",
1354 "renesas,rcar-gen3-scif", "renesas,scif";
1355 reg = <0 0xe6e88000 0 64>;
1356 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1357 clocks = <&cpg CPG_MOD 310>,
1358 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1359 <&scif_clk>;
1360 clock-names = "fck", "brg_int", "scif_clk";
1361 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1362 <&dmac2 0x13>, <&dmac2 0x12>;
1363 dma-names = "tx", "rx", "tx", "rx";
1364 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1365 resets = <&cpg 310>;
1366 status = "disabled";
1367 };
1368
1369 scif3: serial@e6c50000 {
1370 compatible = "renesas,scif-r8a7796",
1371 "renesas,rcar-gen3-scif", "renesas,scif";
1372 reg = <0 0xe6c50000 0 64>;
1373 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1374 clocks = <&cpg CPG_MOD 204>,
1375 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1376 <&scif_clk>;
1377 clock-names = "fck", "brg_int", "scif_clk";
1378 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1379 dma-names = "tx", "rx";
1380 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1381 resets = <&cpg 204>;
1382 status = "disabled";
1383 };
1384
1385 scif4: serial@e6c40000 {
1386 compatible = "renesas,scif-r8a7796",
1387 "renesas,rcar-gen3-scif", "renesas,scif";
1388 reg = <0 0xe6c40000 0 64>;
1389 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1390 clocks = <&cpg CPG_MOD 203>,
1391 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1392 <&scif_clk>;
1393 clock-names = "fck", "brg_int", "scif_clk";
1394 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1395 dma-names = "tx", "rx";
1396 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1397 resets = <&cpg 203>;
1398 status = "disabled";
1399 };
1400
1401 scif5: serial@e6f30000 {
1402 compatible = "renesas,scif-r8a7796",
1403 "renesas,rcar-gen3-scif", "renesas,scif";
1404 reg = <0 0xe6f30000 0 64>;
1405 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1406 clocks = <&cpg CPG_MOD 202>,
1407 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
1408 <&scif_clk>;
1409 clock-names = "fck", "brg_int", "scif_clk";
1410 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1411 <&dmac2 0x5b>, <&dmac2 0x5a>;
1412 dma-names = "tx", "rx", "tx", "rx";
1413 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1414 resets = <&cpg 202>;
1415 status = "disabled";
1416 };
1417
1418 tpu: pwm@e6e80000 {
1419 compatible = "renesas,tpu-r8a7796", "renesas,tpu";
1420 reg = <0 0xe6e80000 0 0x148>;
1421 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
1422 clocks = <&cpg CPG_MOD 304>;
1423 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1424 resets = <&cpg 304>;
1425 #pwm-cells = <3>;
1426 status = "disabled";
1427 };
1428
1429 msiof0: spi@e6e90000 {
1430 compatible = "renesas,msiof-r8a7796",
1431 "renesas,rcar-gen3-msiof";
1432 reg = <0 0xe6e90000 0 0x0064>;
1433 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1434 clocks = <&cpg CPG_MOD 211>;
1435 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1436 <&dmac2 0x41>, <&dmac2 0x40>;
1437 dma-names = "tx", "rx", "tx", "rx";
1438 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1439 resets = <&cpg 211>;
1440 #address-cells = <1>;
1441 #size-cells = <0>;
1442 status = "disabled";
1443 };
1444
1445 msiof1: spi@e6ea0000 {
1446 compatible = "renesas,msiof-r8a7796",
1447 "renesas,rcar-gen3-msiof";
1448 reg = <0 0xe6ea0000 0 0x0064>;
1449 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1450 clocks = <&cpg CPG_MOD 210>;
1451 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1452 <&dmac2 0x43>, <&dmac2 0x42>;
1453 dma-names = "tx", "rx", "tx", "rx";
1454 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1455 resets = <&cpg 210>;
1456 #address-cells = <1>;
1457 #size-cells = <0>;
1458 status = "disabled";
1459 };
1460
1461 msiof2: spi@e6c00000 {
1462 compatible = "renesas,msiof-r8a7796",
1463 "renesas,rcar-gen3-msiof";
1464 reg = <0 0xe6c00000 0 0x0064>;
1465 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1466 clocks = <&cpg CPG_MOD 209>;
1467 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1468 dma-names = "tx", "rx";
1469 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1470 resets = <&cpg 209>;
1471 #address-cells = <1>;
1472 #size-cells = <0>;
1473 status = "disabled";
1474 };
1475
1476 msiof3: spi@e6c10000 {
1477 compatible = "renesas,msiof-r8a7796",
1478 "renesas,rcar-gen3-msiof";
1479 reg = <0 0xe6c10000 0 0x0064>;
1480 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1481 clocks = <&cpg CPG_MOD 208>;
1482 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1483 dma-names = "tx", "rx";
1484 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1485 resets = <&cpg 208>;
1486 #address-cells = <1>;
1487 #size-cells = <0>;
1488 status = "disabled";
1489 };
1490
1491 vin0: video@e6ef0000 {
1492 compatible = "renesas,vin-r8a7796";
1493 reg = <0 0xe6ef0000 0 0x1000>;
1494 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1495 clocks = <&cpg CPG_MOD 811>;
1496 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1497 resets = <&cpg 811>;
1498 renesas,id = <0>;
1499 status = "disabled";
1500
1501 ports {
1502 #address-cells = <1>;
1503 #size-cells = <0>;
1504
1505 port@1 {
1506 #address-cells = <1>;
1507 #size-cells = <0>;
1508
1509 reg = <1>;
1510
1511 vin0csi20: endpoint@0 {
1512 reg = <0>;
1513 remote-endpoint = <&csi20vin0>;
1514 };
1515 vin0csi40: endpoint@2 {
1516 reg = <2>;
1517 remote-endpoint = <&csi40vin0>;
1518 };
1519 };
1520 };
1521 };
1522
1523 vin1: video@e6ef1000 {
1524 compatible = "renesas,vin-r8a7796";
1525 reg = <0 0xe6ef1000 0 0x1000>;
1526 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1527 clocks = <&cpg CPG_MOD 810>;
1528 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1529 resets = <&cpg 810>;
1530 renesas,id = <1>;
1531 status = "disabled";
1532
1533 ports {
1534 #address-cells = <1>;
1535 #size-cells = <0>;
1536
1537 port@1 {
1538 #address-cells = <1>;
1539 #size-cells = <0>;
1540
1541 reg = <1>;
1542
1543 vin1csi20: endpoint@0 {
1544 reg = <0>;
1545 remote-endpoint = <&csi20vin1>;
1546 };
1547 vin1csi40: endpoint@2 {
1548 reg = <2>;
1549 remote-endpoint = <&csi40vin1>;
1550 };
1551 };
1552 };
1553 };
1554
1555 vin2: video@e6ef2000 {
1556 compatible = "renesas,vin-r8a7796";
1557 reg = <0 0xe6ef2000 0 0x1000>;
1558 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1559 clocks = <&cpg CPG_MOD 809>;
1560 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1561 resets = <&cpg 809>;
1562 renesas,id = <2>;
1563 status = "disabled";
1564
1565 ports {
1566 #address-cells = <1>;
1567 #size-cells = <0>;
1568
1569 port@1 {
1570 #address-cells = <1>;
1571 #size-cells = <0>;
1572
1573 reg = <1>;
1574
1575 vin2csi20: endpoint@0 {
1576 reg = <0>;
1577 remote-endpoint = <&csi20vin2>;
1578 };
1579 vin2csi40: endpoint@2 {
1580 reg = <2>;
1581 remote-endpoint = <&csi40vin2>;
1582 };
1583 };
1584 };
1585 };
1586
1587 vin3: video@e6ef3000 {
1588 compatible = "renesas,vin-r8a7796";
1589 reg = <0 0xe6ef3000 0 0x1000>;
1590 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1591 clocks = <&cpg CPG_MOD 808>;
1592 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1593 resets = <&cpg 808>;
1594 renesas,id = <3>;
1595 status = "disabled";
1596
1597 ports {
1598 #address-cells = <1>;
1599 #size-cells = <0>;
1600
1601 port@1 {
1602 #address-cells = <1>;
1603 #size-cells = <0>;
1604
1605 reg = <1>;
1606
1607 vin3csi20: endpoint@0 {
1608 reg = <0>;
1609 remote-endpoint = <&csi20vin3>;
1610 };
1611 vin3csi40: endpoint@2 {
1612 reg = <2>;
1613 remote-endpoint = <&csi40vin3>;
1614 };
1615 };
1616 };
1617 };
1618
1619 vin4: video@e6ef4000 {
1620 compatible = "renesas,vin-r8a7796";
1621 reg = <0 0xe6ef4000 0 0x1000>;
1622 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1623 clocks = <&cpg CPG_MOD 807>;
1624 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1625 resets = <&cpg 807>;
1626 renesas,id = <4>;
1627 status = "disabled";
1628
1629 ports {
1630 #address-cells = <1>;
1631 #size-cells = <0>;
1632
1633 port@1 {
1634 #address-cells = <1>;
1635 #size-cells = <0>;
1636
1637 reg = <1>;
1638
1639 vin4csi20: endpoint@0 {
1640 reg = <0>;
1641 remote-endpoint = <&csi20vin4>;
1642 };
1643 vin4csi40: endpoint@2 {
1644 reg = <2>;
1645 remote-endpoint = <&csi40vin4>;
1646 };
1647 };
1648 };
1649 };
1650
1651 vin5: video@e6ef5000 {
1652 compatible = "renesas,vin-r8a7796";
1653 reg = <0 0xe6ef5000 0 0x1000>;
1654 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1655 clocks = <&cpg CPG_MOD 806>;
1656 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1657 resets = <&cpg 806>;
1658 renesas,id = <5>;
1659 status = "disabled";
1660
1661 ports {
1662 #address-cells = <1>;
1663 #size-cells = <0>;
1664
1665 port@1 {
1666 #address-cells = <1>;
1667 #size-cells = <0>;
1668
1669 reg = <1>;
1670
1671 vin5csi20: endpoint@0 {
1672 reg = <0>;
1673 remote-endpoint = <&csi20vin5>;
1674 };
1675 vin5csi40: endpoint@2 {
1676 reg = <2>;
1677 remote-endpoint = <&csi40vin5>;
1678 };
1679 };
1680 };
1681 };
1682
1683 vin6: video@e6ef6000 {
1684 compatible = "renesas,vin-r8a7796";
1685 reg = <0 0xe6ef6000 0 0x1000>;
1686 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1687 clocks = <&cpg CPG_MOD 805>;
1688 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1689 resets = <&cpg 805>;
1690 renesas,id = <6>;
1691 status = "disabled";
1692
1693 ports {
1694 #address-cells = <1>;
1695 #size-cells = <0>;
1696
1697 port@1 {
1698 #address-cells = <1>;
1699 #size-cells = <0>;
1700
1701 reg = <1>;
1702
1703 vin6csi20: endpoint@0 {
1704 reg = <0>;
1705 remote-endpoint = <&csi20vin6>;
1706 };
1707 vin6csi40: endpoint@2 {
1708 reg = <2>;
1709 remote-endpoint = <&csi40vin6>;
1710 };
1711 };
1712 };
1713 };
1714
1715 vin7: video@e6ef7000 {
1716 compatible = "renesas,vin-r8a7796";
1717 reg = <0 0xe6ef7000 0 0x1000>;
1718 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
1719 clocks = <&cpg CPG_MOD 804>;
1720 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1721 resets = <&cpg 804>;
1722 renesas,id = <7>;
1723 status = "disabled";
1724
1725 ports {
1726 #address-cells = <1>;
1727 #size-cells = <0>;
1728
1729 port@1 {
1730 #address-cells = <1>;
1731 #size-cells = <0>;
1732
1733 reg = <1>;
1734
1735 vin7csi20: endpoint@0 {
1736 reg = <0>;
1737 remote-endpoint = <&csi20vin7>;
1738 };
1739 vin7csi40: endpoint@2 {
1740 reg = <2>;
1741 remote-endpoint = <&csi40vin7>;
1742 };
1743 };
1744 };
1745 };
1746
1747 drif00: rif@e6f40000 {
1748 compatible = "renesas,r8a7796-drif",
1749 "renesas,rcar-gen3-drif";
1750 reg = <0 0xe6f40000 0 0x64>;
1751 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1752 clocks = <&cpg CPG_MOD 515>;
1753 clock-names = "fck";
1754 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1755 dma-names = "rx", "rx";
1756 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1757 resets = <&cpg 515>;
1758 renesas,bonding = <&drif01>;
1759 status = "disabled";
1760 };
1761
1762 drif01: rif@e6f50000 {
1763 compatible = "renesas,r8a7796-drif",
1764 "renesas,rcar-gen3-drif";
1765 reg = <0 0xe6f50000 0 0x64>;
1766 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1767 clocks = <&cpg CPG_MOD 514>;
1768 clock-names = "fck";
1769 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1770 dma-names = "rx", "rx";
1771 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1772 resets = <&cpg 514>;
1773 renesas,bonding = <&drif00>;
1774 status = "disabled";
1775 };
1776
1777 drif10: rif@e6f60000 {
1778 compatible = "renesas,r8a7796-drif",
1779 "renesas,rcar-gen3-drif";
1780 reg = <0 0xe6f60000 0 0x64>;
1781 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1782 clocks = <&cpg CPG_MOD 513>;
1783 clock-names = "fck";
1784 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1785 dma-names = "rx", "rx";
1786 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1787 resets = <&cpg 513>;
1788 renesas,bonding = <&drif11>;
1789 status = "disabled";
1790 };
1791
1792 drif11: rif@e6f70000 {
1793 compatible = "renesas,r8a7796-drif",
1794 "renesas,rcar-gen3-drif";
1795 reg = <0 0xe6f70000 0 0x64>;
1796 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1797 clocks = <&cpg CPG_MOD 512>;
1798 clock-names = "fck";
1799 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1800 dma-names = "rx", "rx";
1801 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1802 resets = <&cpg 512>;
1803 renesas,bonding = <&drif10>;
1804 status = "disabled";
1805 };
1806
1807 drif20: rif@e6f80000 {
1808 compatible = "renesas,r8a7796-drif",
1809 "renesas,rcar-gen3-drif";
1810 reg = <0 0xe6f80000 0 0x64>;
1811 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1812 clocks = <&cpg CPG_MOD 511>;
1813 clock-names = "fck";
1814 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1815 dma-names = "rx", "rx";
1816 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1817 resets = <&cpg 511>;
1818 renesas,bonding = <&drif21>;
1819 status = "disabled";
1820 };
1821
1822 drif21: rif@e6f90000 {
1823 compatible = "renesas,r8a7796-drif",
1824 "renesas,rcar-gen3-drif";
1825 reg = <0 0xe6f90000 0 0x64>;
1826 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1827 clocks = <&cpg CPG_MOD 510>;
1828 clock-names = "fck";
1829 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1830 dma-names = "rx", "rx";
1831 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1832 resets = <&cpg 510>;
1833 renesas,bonding = <&drif20>;
1834 status = "disabled";
1835 };
1836
1837 drif30: rif@e6fa0000 {
1838 compatible = "renesas,r8a7796-drif",
1839 "renesas,rcar-gen3-drif";
1840 reg = <0 0xe6fa0000 0 0x64>;
1841 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1842 clocks = <&cpg CPG_MOD 509>;
1843 clock-names = "fck";
1844 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1845 dma-names = "rx", "rx";
1846 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1847 resets = <&cpg 509>;
1848 renesas,bonding = <&drif31>;
1849 status = "disabled";
1850 };
1851
1852 drif31: rif@e6fb0000 {
1853 compatible = "renesas,r8a7796-drif",
1854 "renesas,rcar-gen3-drif";
1855 reg = <0 0xe6fb0000 0 0x64>;
1856 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1857 clocks = <&cpg CPG_MOD 508>;
1858 clock-names = "fck";
1859 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1860 dma-names = "rx", "rx";
1861 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1862 resets = <&cpg 508>;
1863 renesas,bonding = <&drif30>;
1864 status = "disabled";
1865 };
1866
1867 rcar_sound: sound@ec500000 {
1868 /*
1869 * #sound-dai-cells is required if simple-card
1870 *
1871 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1872 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1873 */
1874 /*
1875 * #clock-cells is required for audio_clkout0/1/2/3
1876 *
1877 * clkout : #clock-cells = <0>; <&rcar_sound>;
1878 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1879 */
1880 compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3";
1881 reg = <0 0xec500000 0 0x1000>, /* SCU */
1882 <0 0xec5a0000 0 0x100>, /* ADG */
1883 <0 0xec540000 0 0x1000>, /* SSIU */
1884 <0 0xec541000 0 0x280>, /* SSI */
1885 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1886 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1887
1888 clocks = <&cpg CPG_MOD 1005>,
1889 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1890 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1891 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1892 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1893 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1894 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1895 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1896 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1897 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1898 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1899 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1900 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1901 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1902 <&audio_clk_a>, <&audio_clk_b>,
1903 <&audio_clk_c>,
1904 <&cpg CPG_MOD 922>;
1905 clock-names = "ssi-all",
1906 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1907 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1908 "ssi.1", "ssi.0",
1909 "src.9", "src.8", "src.7", "src.6",
1910 "src.5", "src.4", "src.3", "src.2",
1911 "src.1", "src.0",
1912 "mix.1", "mix.0",
1913 "ctu.1", "ctu.0",
1914 "dvc.0", "dvc.1",
1915 "clk_a", "clk_b", "clk_c", "clk_i";
1916 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
1917 resets = <&cpg 1005>,
1918 <&cpg 1006>, <&cpg 1007>,
1919 <&cpg 1008>, <&cpg 1009>,
1920 <&cpg 1010>, <&cpg 1011>,
1921 <&cpg 1012>, <&cpg 1013>,
1922 <&cpg 1014>, <&cpg 1015>;
1923 reset-names = "ssi-all",
1924 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1925 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1926 "ssi.1", "ssi.0";
1927 status = "disabled";
1928
1929 rcar_sound,ctu {
1930 ctu00: ctu-0 { };
1931 ctu01: ctu-1 { };
1932 ctu02: ctu-2 { };
1933 ctu03: ctu-3 { };
1934 ctu10: ctu-4 { };
1935 ctu11: ctu-5 { };
1936 ctu12: ctu-6 { };
1937 ctu13: ctu-7 { };
1938 };
1939
1940 rcar_sound,dvc {
1941 dvc0: dvc-0 {
1942 dmas = <&audma1 0xbc>;
1943 dma-names = "tx";
1944 };
1945 dvc1: dvc-1 {
1946 dmas = <&audma1 0xbe>;
1947 dma-names = "tx";
1948 };
1949 };
1950
1951 rcar_sound,mix {
1952 mix0: mix-0 { };
1953 mix1: mix-1 { };
1954 };
1955
1956 rcar_sound,src {
1957 src0: src-0 {
1958 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1959 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1960 dma-names = "rx", "tx";
1961 };
1962 src1: src-1 {
1963 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1964 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1965 dma-names = "rx", "tx";
1966 };
1967 src2: src-2 {
1968 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1969 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1970 dma-names = "rx", "tx";
1971 };
1972 src3: src-3 {
1973 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1974 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1975 dma-names = "rx", "tx";
1976 };
1977 src4: src-4 {
1978 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1979 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1980 dma-names = "rx", "tx";
1981 };
1982 src5: src-5 {
1983 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1984 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1985 dma-names = "rx", "tx";
1986 };
1987 src6: src-6 {
1988 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1989 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1990 dma-names = "rx", "tx";
1991 };
1992 src7: src-7 {
1993 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1994 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1995 dma-names = "rx", "tx";
1996 };
1997 src8: src-8 {
1998 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1999 dmas = <&audma0 0x95>, <&audma1 0xb8>;
2000 dma-names = "rx", "tx";
2001 };
2002 src9: src-9 {
2003 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
2004 dmas = <&audma0 0x97>, <&audma1 0xba>;
2005 dma-names = "rx", "tx";
2006 };
2007 };
2008
2009 rcar_sound,ssi {
2010 ssi0: ssi-0 {
2011 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
2012 dmas = <&audma0 0x01>, <&audma1 0x02>;
2013 dma-names = "rx", "tx";
2014 };
2015 ssi1: ssi-1 {
2016 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
2017 dmas = <&audma0 0x03>, <&audma1 0x04>;
2018 dma-names = "rx", "tx";
2019 };
2020 ssi2: ssi-2 {
2021 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
2022 dmas = <&audma0 0x05>, <&audma1 0x06>;
2023 dma-names = "rx", "tx";
2024 };
2025 ssi3: ssi-3 {
2026 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
2027 dmas = <&audma0 0x07>, <&audma1 0x08>;
2028 dma-names = "rx", "tx";
2029 };
2030 ssi4: ssi-4 {
2031 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
2032 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2033 dma-names = "rx", "tx";
2034 };
2035 ssi5: ssi-5 {
2036 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
2037 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2038 dma-names = "rx", "tx";
2039 };
2040 ssi6: ssi-6 {
2041 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
2042 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2043 dma-names = "rx", "tx";
2044 };
2045 ssi7: ssi-7 {
2046 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
2047 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2048 dma-names = "rx", "tx";
2049 };
2050 ssi8: ssi-8 {
2051 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
2052 dmas = <&audma0 0x11>, <&audma1 0x12>;
2053 dma-names = "rx", "tx";
2054 };
2055 ssi9: ssi-9 {
2056 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
2057 dmas = <&audma0 0x13>, <&audma1 0x14>;
2058 dma-names = "rx", "tx";
2059 };
2060 };
2061
2062 rcar_sound,ssiu {
2063 ssiu00: ssiu-0 {
2064 dmas = <&audma0 0x15>, <&audma1 0x16>;
2065 dma-names = "rx", "tx";
2066 };
2067 ssiu01: ssiu-1 {
2068 dmas = <&audma0 0x35>, <&audma1 0x36>;
2069 dma-names = "rx", "tx";
2070 };
2071 ssiu02: ssiu-2 {
2072 dmas = <&audma0 0x37>, <&audma1 0x38>;
2073 dma-names = "rx", "tx";
2074 };
2075 ssiu03: ssiu-3 {
2076 dmas = <&audma0 0x47>, <&audma1 0x48>;
2077 dma-names = "rx", "tx";
2078 };
2079 ssiu04: ssiu-4 {
2080 dmas = <&audma0 0x3F>, <&audma1 0x40>;
2081 dma-names = "rx", "tx";
2082 };
2083 ssiu05: ssiu-5 {
2084 dmas = <&audma0 0x43>, <&audma1 0x44>;
2085 dma-names = "rx", "tx";
2086 };
2087 ssiu06: ssiu-6 {
2088 dmas = <&audma0 0x4F>, <&audma1 0x50>;
2089 dma-names = "rx", "tx";
2090 };
2091 ssiu07: ssiu-7 {
2092 dmas = <&audma0 0x53>, <&audma1 0x54>;
2093 dma-names = "rx", "tx";
2094 };
2095 ssiu10: ssiu-8 {
2096 dmas = <&audma0 0x49>, <&audma1 0x4a>;
2097 dma-names = "rx", "tx";
2098 };
2099 ssiu11: ssiu-9 {
2100 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
2101 dma-names = "rx", "tx";
2102 };
2103 ssiu12: ssiu-10 {
2104 dmas = <&audma0 0x57>, <&audma1 0x58>;
2105 dma-names = "rx", "tx";
2106 };
2107 ssiu13: ssiu-11 {
2108 dmas = <&audma0 0x59>, <&audma1 0x5A>;
2109 dma-names = "rx", "tx";
2110 };
2111 ssiu14: ssiu-12 {
2112 dmas = <&audma0 0x5F>, <&audma1 0x60>;
2113 dma-names = "rx", "tx";
2114 };
2115 ssiu15: ssiu-13 {
2116 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
2117 dma-names = "rx", "tx";
2118 };
2119 ssiu16: ssiu-14 {
2120 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
2121 dma-names = "rx", "tx";
2122 };
2123 ssiu17: ssiu-15 {
2124 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
2125 dma-names = "rx", "tx";
2126 };
2127 ssiu20: ssiu-16 {
2128 dmas = <&audma0 0x63>, <&audma1 0x64>;
2129 dma-names = "rx", "tx";
2130 };
2131 ssiu21: ssiu-17 {
2132 dmas = <&audma0 0x67>, <&audma1 0x68>;
2133 dma-names = "rx", "tx";
2134 };
2135 ssiu22: ssiu-18 {
2136 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
2137 dma-names = "rx", "tx";
2138 };
2139 ssiu23: ssiu-19 {
2140 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
2141 dma-names = "rx", "tx";
2142 };
2143 ssiu24: ssiu-20 {
2144 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2145 dma-names = "rx", "tx";
2146 };
2147 ssiu25: ssiu-21 {
2148 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2149 dma-names = "rx", "tx";
2150 };
2151 ssiu26: ssiu-22 {
2152 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2153 dma-names = "rx", "tx";
2154 };
2155 ssiu27: ssiu-23 {
2156 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2157 dma-names = "rx", "tx";
2158 };
2159 ssiu30: ssiu-24 {
2160 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2161 dma-names = "rx", "tx";
2162 };
2163 ssiu31: ssiu-25 {
2164 dmas = <&audma0 0x21>, <&audma1 0x22>;
2165 dma-names = "rx", "tx";
2166 };
2167 ssiu32: ssiu-26 {
2168 dmas = <&audma0 0x23>, <&audma1 0x24>;
2169 dma-names = "rx", "tx";
2170 };
2171 ssiu33: ssiu-27 {
2172 dmas = <&audma0 0x25>, <&audma1 0x26>;
2173 dma-names = "rx", "tx";
2174 };
2175 ssiu34: ssiu-28 {
2176 dmas = <&audma0 0x27>, <&audma1 0x28>;
2177 dma-names = "rx", "tx";
2178 };
2179 ssiu35: ssiu-29 {
2180 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2181 dma-names = "rx", "tx";
2182 };
2183 ssiu36: ssiu-30 {
2184 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2185 dma-names = "rx", "tx";
2186 };
2187 ssiu37: ssiu-31 {
2188 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2189 dma-names = "rx", "tx";
2190 };
2191 ssiu40: ssiu-32 {
2192 dmas = <&audma0 0x71>, <&audma1 0x72>;
2193 dma-names = "rx", "tx";
2194 };
2195 ssiu41: ssiu-33 {
2196 dmas = <&audma0 0x17>, <&audma1 0x18>;
2197 dma-names = "rx", "tx";
2198 };
2199 ssiu42: ssiu-34 {
2200 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2201 dma-names = "rx", "tx";
2202 };
2203 ssiu43: ssiu-35 {
2204 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2205 dma-names = "rx", "tx";
2206 };
2207 ssiu44: ssiu-36 {
2208 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2209 dma-names = "rx", "tx";
2210 };
2211 ssiu45: ssiu-37 {
2212 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2213 dma-names = "rx", "tx";
2214 };
2215 ssiu46: ssiu-38 {
2216 dmas = <&audma0 0x31>, <&audma1 0x32>;
2217 dma-names = "rx", "tx";
2218 };
2219 ssiu47: ssiu-39 {
2220 dmas = <&audma0 0x33>, <&audma1 0x34>;
2221 dma-names = "rx", "tx";
2222 };
2223 ssiu50: ssiu-40 {
2224 dmas = <&audma0 0x73>, <&audma1 0x74>;
2225 dma-names = "rx", "tx";
2226 };
2227 ssiu60: ssiu-41 {
2228 dmas = <&audma0 0x75>, <&audma1 0x76>;
2229 dma-names = "rx", "tx";
2230 };
2231 ssiu70: ssiu-42 {
2232 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2233 dma-names = "rx", "tx";
2234 };
2235 ssiu80: ssiu-43 {
2236 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2237 dma-names = "rx", "tx";
2238 };
2239 ssiu90: ssiu-44 {
2240 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2241 dma-names = "rx", "tx";
2242 };
2243 ssiu91: ssiu-45 {
2244 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2245 dma-names = "rx", "tx";
2246 };
2247 ssiu92: ssiu-46 {
2248 dmas = <&audma0 0x81>, <&audma1 0x82>;
2249 dma-names = "rx", "tx";
2250 };
2251 ssiu93: ssiu-47 {
2252 dmas = <&audma0 0x83>, <&audma1 0x84>;
2253 dma-names = "rx", "tx";
2254 };
2255 ssiu94: ssiu-48 {
2256 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2257 dma-names = "rx", "tx";
2258 };
2259 ssiu95: ssiu-49 {
2260 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2261 dma-names = "rx", "tx";
2262 };
2263 ssiu96: ssiu-50 {
2264 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2265 dma-names = "rx", "tx";
2266 };
2267 ssiu97: ssiu-51 {
2268 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2269 dma-names = "rx", "tx";
2270 };
2271 };
2272 };
2273
2274 mlp: mlp@ec520000 {
2275 compatible = "renesas,r8a7796-mlp",
2276 "renesas,rcar-gen3-mlp";
2277 reg = <0 0xec520000 0 0x800>;
2278 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
2279 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
2280 clocks = <&cpg CPG_MOD 802>;
2281 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2282 resets = <&cpg 802>;
2283 status = "disabled";
2284 };
2285
2286 audma0: dma-controller@ec700000 {
2287 compatible = "renesas,dmac-r8a7796",
2288 "renesas,rcar-dmac";
2289 reg = <0 0xec700000 0 0x10000>;
2290 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
2291 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2292 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2293 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2294 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2295 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2296 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2297 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2298 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2299 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2300 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2301 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2302 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2303 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2304 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2305 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2306 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
2307 interrupt-names = "error",
2308 "ch0", "ch1", "ch2", "ch3",
2309 "ch4", "ch5", "ch6", "ch7",
2310 "ch8", "ch9", "ch10", "ch11",
2311 "ch12", "ch13", "ch14", "ch15";
2312 clocks = <&cpg CPG_MOD 502>;
2313 clock-names = "fck";
2314 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2315 resets = <&cpg 502>;
2316 #dma-cells = <1>;
2317 dma-channels = <16>;
2318 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2319 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
2320 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
2321 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
2322 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
2323 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
2324 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
2325 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
2326 };
2327
2328 audma1: dma-controller@ec720000 {
2329 compatible = "renesas,dmac-r8a7796",
2330 "renesas,rcar-dmac";
2331 reg = <0 0xec720000 0 0x10000>;
2332 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
2333 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2334 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2335 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2336 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2337 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2338 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2339 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2340 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2341 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2342 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2343 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
2344 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2345 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
2346 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
2347 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
2348 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
2349 interrupt-names = "error",
2350 "ch0", "ch1", "ch2", "ch3",
2351 "ch4", "ch5", "ch6", "ch7",
2352 "ch8", "ch9", "ch10", "ch11",
2353 "ch12", "ch13", "ch14", "ch15";
2354 clocks = <&cpg CPG_MOD 501>;
2355 clock-names = "fck";
2356 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2357 resets = <&cpg 501>;
2358 #dma-cells = <1>;
2359 dma-channels = <16>;
2360 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
2361 <&ipmmu_mp 18>, <&ipmmu_mp 19>,
2362 <&ipmmu_mp 20>, <&ipmmu_mp 21>,
2363 <&ipmmu_mp 22>, <&ipmmu_mp 23>,
2364 <&ipmmu_mp 24>, <&ipmmu_mp 25>,
2365 <&ipmmu_mp 26>, <&ipmmu_mp 27>,
2366 <&ipmmu_mp 28>, <&ipmmu_mp 29>,
2367 <&ipmmu_mp 30>, <&ipmmu_mp 31>;
2368 };
2369
2370 xhci0: usb@ee000000 {
2371 compatible = "renesas,xhci-r8a7796",
2372 "renesas,rcar-gen3-xhci";
2373 reg = <0 0xee000000 0 0xc00>;
2374 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2375 clocks = <&cpg CPG_MOD 328>;
2376 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2377 resets = <&cpg 328>;
2378 status = "disabled";
2379 };
2380
2381 usb3_peri0: usb@ee020000 {
2382 compatible = "renesas,r8a7796-usb3-peri",
2383 "renesas,rcar-gen3-usb3-peri";
2384 reg = <0 0xee020000 0 0x400>;
2385 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2386 clocks = <&cpg CPG_MOD 328>;
2387 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2388 resets = <&cpg 328>;
2389 status = "disabled";
2390 };
2391
2392 ohci0: usb@ee080000 {
2393 compatible = "generic-ohci";
2394 reg = <0 0xee080000 0 0x100>;
2395 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2396 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2397 phys = <&usb2_phy0 1>;
2398 phy-names = "usb";
2399 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2400 resets = <&cpg 703>, <&cpg 704>;
2401 status = "disabled";
2402 };
2403
2404 ohci1: usb@ee0a0000 {
2405 compatible = "generic-ohci";
2406 reg = <0 0xee0a0000 0 0x100>;
2407 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2408 clocks = <&cpg CPG_MOD 702>;
2409 phys = <&usb2_phy1 1>;
2410 phy-names = "usb";
2411 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2412 resets = <&cpg 702>;
2413 status = "disabled";
2414 };
2415
2416 ehci0: usb@ee080100 {
2417 compatible = "generic-ehci";
2418 reg = <0 0xee080100 0 0x100>;
2419 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2420 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2421 phys = <&usb2_phy0 2>;
2422 phy-names = "usb";
2423 companion = <&ohci0>;
2424 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2425 resets = <&cpg 703>, <&cpg 704>;
2426 status = "disabled";
2427 };
2428
2429 ehci1: usb@ee0a0100 {
2430 compatible = "generic-ehci";
2431 reg = <0 0xee0a0100 0 0x100>;
2432 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
2433 clocks = <&cpg CPG_MOD 702>;
2434 phys = <&usb2_phy1 2>;
2435 phy-names = "usb";
2436 companion = <&ohci1>;
2437 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2438 resets = <&cpg 702>;
2439 status = "disabled";
2440 };
2441
2442 usb2_phy0: usb-phy@ee080200 {
2443 compatible = "renesas,usb2-phy-r8a7796",
2444 "renesas,rcar-gen3-usb2-phy";
2445 reg = <0 0xee080200 0 0x700>;
2446 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2447 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
2448 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2449 resets = <&cpg 703>, <&cpg 704>;
2450 #phy-cells = <1>;
2451 status = "disabled";
2452 };
2453
2454 usb2_phy1: usb-phy@ee0a0200 {
2455 compatible = "renesas,usb2-phy-r8a7796",
2456 "renesas,rcar-gen3-usb2-phy";
2457 reg = <0 0xee0a0200 0 0x700>;
2458 clocks = <&cpg CPG_MOD 702>;
2459 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2460 resets = <&cpg 702>;
2461 #phy-cells = <1>;
2462 status = "disabled";
2463 };
2464
2465 sdhi0: mmc@ee100000 {
2466 compatible = "renesas,sdhi-r8a7796",
2467 "renesas,rcar-gen3-sdhi";
2468 reg = <0 0xee100000 0 0x2000>;
2469 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
2470 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7796_CLK_SD0H>;
2471 clock-names = "core", "clkh";
2472 max-frequency = <200000000>;
2473 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2474 resets = <&cpg 314>;
2475 iommus = <&ipmmu_ds1 32>;
2476 status = "disabled";
2477 };
2478
2479 sdhi1: mmc@ee120000 {
2480 compatible = "renesas,sdhi-r8a7796",
2481 "renesas,rcar-gen3-sdhi";
2482 reg = <0 0xee120000 0 0x2000>;
2483 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
2484 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7796_CLK_SD1H>;
2485 clock-names = "core", "clkh";
2486 max-frequency = <200000000>;
2487 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2488 resets = <&cpg 313>;
2489 iommus = <&ipmmu_ds1 33>;
2490 status = "disabled";
2491 };
2492
2493 sdhi2: mmc@ee140000 {
2494 compatible = "renesas,sdhi-r8a7796",
2495 "renesas,rcar-gen3-sdhi";
2496 reg = <0 0xee140000 0 0x2000>;
2497 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
2498 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7796_CLK_SD2H>;
2499 clock-names = "core", "clkh";
2500 max-frequency = <200000000>;
2501 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2502 resets = <&cpg 312>;
2503 iommus = <&ipmmu_ds1 34>;
2504 status = "disabled";
2505 };
2506
2507 sdhi3: mmc@ee160000 {
2508 compatible = "renesas,sdhi-r8a7796",
2509 "renesas,rcar-gen3-sdhi";
2510 reg = <0 0xee160000 0 0x2000>;
2511 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
2512 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7796_CLK_SD3H>;
2513 clock-names = "core", "clkh";
2514 max-frequency = <200000000>;
2515 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2516 resets = <&cpg 311>;
2517 iommus = <&ipmmu_ds1 35>;
2518 status = "disabled";
2519 };
2520
2521 rpc: spi@ee200000 {
2522 compatible = "renesas,r8a7796-rpc-if",
2523 "renesas,rcar-gen3-rpc-if";
2524 reg = <0 0xee200000 0 0x200>,
2525 <0 0x08000000 0 0x04000000>,
2526 <0 0xee208000 0 0x100>;
2527 reg-names = "regs", "dirmap", "wbuf";
2528 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2529 clocks = <&cpg CPG_MOD 917>;
2530 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2531 resets = <&cpg 917>;
2532 #address-cells = <1>;
2533 #size-cells = <0>;
2534 status = "disabled";
2535 };
2536
2537 gic: interrupt-controller@f1010000 {
2538 compatible = "arm,gic-400";
2539 #interrupt-cells = <3>;
2540 #address-cells = <0>;
2541 interrupt-controller;
2542 reg = <0x0 0xf1010000 0 0x1000>,
2543 <0x0 0xf1020000 0 0x20000>,
2544 <0x0 0xf1040000 0 0x20000>,
2545 <0x0 0xf1060000 0 0x20000>;
2546 interrupts = <GIC_PPI 9
2547 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
2548 clocks = <&cpg CPG_MOD 408>;
2549 clock-names = "clk";
2550 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2551 resets = <&cpg 408>;
2552 };
2553
2554 pciec0: pcie@fe000000 {
2555 compatible = "renesas,pcie-r8a7796",
2556 "renesas,pcie-rcar-gen3";
2557 reg = <0 0xfe000000 0 0x80000>;
2558 #address-cells = <3>;
2559 #size-cells = <2>;
2560 bus-range = <0x00 0xff>;
2561 device_type = "pci";
2562 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2563 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2564 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2565 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2566 /* Map all possible DDR/IOMMU as inbound ranges */
2567 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2568 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2569 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2570 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
2571 #interrupt-cells = <1>;
2572 interrupt-map-mask = <0 0 0 0>;
2573 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2574 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
2575 clock-names = "pcie", "pcie_bus";
2576 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2577 resets = <&cpg 319>;
2578 iommu-map = <0 &ipmmu_hc 0 1>;
2579 iommu-map-mask = <0>;
2580 status = "disabled";
2581 };
2582
2583 pciec1: pcie@ee800000 {
2584 compatible = "renesas,pcie-r8a7796",
2585 "renesas,pcie-rcar-gen3";
2586 reg = <0 0xee800000 0 0x80000>;
2587 #address-cells = <3>;
2588 #size-cells = <2>;
2589 bus-range = <0x00 0xff>;
2590 device_type = "pci";
2591 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2592 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2593 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2594 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2595 /* Map all possible DDR/IOMMU as inbound ranges */
2596 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2597 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2598 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2599 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2600 #interrupt-cells = <1>;
2601 interrupt-map-mask = <0 0 0 0>;
2602 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2603 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
2604 clock-names = "pcie", "pcie_bus";
2605 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2606 resets = <&cpg 318>;
2607 iommu-map = <0 &ipmmu_hc 1 1>;
2608 iommu-map-mask = <0>;
2609 status = "disabled";
2610 };
2611
2612 imr-lx4@fe860000 {
2613 compatible = "renesas,r8a7796-imr-lx4",
2614 "renesas,imr-lx4";
2615 reg = <0 0xfe860000 0 0x2000>;
2616 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
2617 clocks = <&cpg CPG_MOD 823>;
2618 power-domains = <&sysc R8A7796_PD_A3VC>;
2619 resets = <&cpg 823>;
2620 };
2621
2622 imr-lx4@fe870000 {
2623 compatible = "renesas,r8a7796-imr-lx4",
2624 "renesas,imr-lx4";
2625 reg = <0 0xfe870000 0 0x2000>;
2626 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
2627 clocks = <&cpg CPG_MOD 822>;
2628 power-domains = <&sysc R8A7796_PD_A3VC>;
2629 resets = <&cpg 822>;
2630 };
2631
2632 fdp1@fe940000 {
2633 compatible = "renesas,fdp1";
2634 reg = <0 0xfe940000 0 0x2400>;
2635 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
2636 clocks = <&cpg CPG_MOD 119>;
2637 power-domains = <&sysc R8A7796_PD_A3VC>;
2638 resets = <&cpg 119>;
2639 renesas,fcp = <&fcpf0>;
2640 };
2641
2642 fcpf0: fcp@fe950000 {
2643 compatible = "renesas,fcpf";
2644 reg = <0 0xfe950000 0 0x200>;
2645 clocks = <&cpg CPG_MOD 615>;
2646 power-domains = <&sysc R8A7796_PD_A3VC>;
2647 resets = <&cpg 615>;
2648 };
2649
2650 fcpvb0: fcp@fe96f000 {
2651 compatible = "renesas,fcpv";
2652 reg = <0 0xfe96f000 0 0x200>;
2653 clocks = <&cpg CPG_MOD 607>;
2654 power-domains = <&sysc R8A7796_PD_A3VC>;
2655 resets = <&cpg 607>;
2656 };
2657
2658 fcpvi0: fcp@fe9af000 {
2659 compatible = "renesas,fcpv";
2660 reg = <0 0xfe9af000 0 0x200>;
2661 clocks = <&cpg CPG_MOD 611>;
2662 power-domains = <&sysc R8A7796_PD_A3VC>;
2663 resets = <&cpg 611>;
2664 iommus = <&ipmmu_vc0 19>;
2665 };
2666
2667 fcpvd0: fcp@fea27000 {
2668 compatible = "renesas,fcpv";
2669 reg = <0 0xfea27000 0 0x200>;
2670 clocks = <&cpg CPG_MOD 603>;
2671 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2672 resets = <&cpg 603>;
2673 iommus = <&ipmmu_vi0 8>;
2674 };
2675
2676 fcpvd1: fcp@fea2f000 {
2677 compatible = "renesas,fcpv";
2678 reg = <0 0xfea2f000 0 0x200>;
2679 clocks = <&cpg CPG_MOD 602>;
2680 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2681 resets = <&cpg 602>;
2682 iommus = <&ipmmu_vi0 9>;
2683 };
2684
2685 fcpvd2: fcp@fea37000 {
2686 compatible = "renesas,fcpv";
2687 reg = <0 0xfea37000 0 0x200>;
2688 clocks = <&cpg CPG_MOD 601>;
2689 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2690 resets = <&cpg 601>;
2691 iommus = <&ipmmu_vi0 10>;
2692 };
2693
2694 vspb: vsp@fe960000 {
2695 compatible = "renesas,vsp2";
2696 reg = <0 0xfe960000 0 0x8000>;
2697 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
2698 clocks = <&cpg CPG_MOD 626>;
2699 power-domains = <&sysc R8A7796_PD_A3VC>;
2700 resets = <&cpg 626>;
2701
2702 renesas,fcp = <&fcpvb0>;
2703 };
2704
2705 vspd0: vsp@fea20000 {
2706 compatible = "renesas,vsp2";
2707 reg = <0 0xfea20000 0 0x5000>;
2708 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
2709 clocks = <&cpg CPG_MOD 623>;
2710 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2711 resets = <&cpg 623>;
2712
2713 renesas,fcp = <&fcpvd0>;
2714 };
2715
2716 vspd1: vsp@fea28000 {
2717 compatible = "renesas,vsp2";
2718 reg = <0 0xfea28000 0 0x5000>;
2719 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
2720 clocks = <&cpg CPG_MOD 622>;
2721 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2722 resets = <&cpg 622>;
2723
2724 renesas,fcp = <&fcpvd1>;
2725 };
2726
2727 vspd2: vsp@fea30000 {
2728 compatible = "renesas,vsp2";
2729 reg = <0 0xfea30000 0 0x5000>;
2730 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
2731 clocks = <&cpg CPG_MOD 621>;
2732 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2733 resets = <&cpg 621>;
2734
2735 renesas,fcp = <&fcpvd2>;
2736 };
2737
2738 vspi0: vsp@fe9a0000 {
2739 compatible = "renesas,vsp2";
2740 reg = <0 0xfe9a0000 0 0x8000>;
2741 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
2742 clocks = <&cpg CPG_MOD 631>;
2743 power-domains = <&sysc R8A7796_PD_A3VC>;
2744 resets = <&cpg 631>;
2745
2746 renesas,fcp = <&fcpvi0>;
2747 };
2748
2749 cmm0: cmm@fea40000 {
2750 compatible = "renesas,r8a7796-cmm",
2751 "renesas,rcar-gen3-cmm";
2752 reg = <0 0xfea40000 0 0x1000>;
2753 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2754 clocks = <&cpg CPG_MOD 711>;
2755 resets = <&cpg 711>;
2756 };
2757
2758 cmm1: cmm@fea50000 {
2759 compatible = "renesas,r8a7796-cmm",
2760 "renesas,rcar-gen3-cmm";
2761 reg = <0 0xfea50000 0 0x1000>;
2762 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2763 clocks = <&cpg CPG_MOD 710>;
2764 resets = <&cpg 710>;
2765 };
2766
2767 cmm2: cmm@fea60000 {
2768 compatible = "renesas,r8a7796-cmm",
2769 "renesas,rcar-gen3-cmm";
2770 reg = <0 0xfea60000 0 0x1000>;
2771 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2772 clocks = <&cpg CPG_MOD 709>;
2773 resets = <&cpg 709>;
2774 };
2775
2776 csi20: csi2@fea80000 {
2777 compatible = "renesas,r8a7796-csi2";
2778 reg = <0 0xfea80000 0 0x10000>;
2779 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2780 clocks = <&cpg CPG_MOD 714>;
2781 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2782 resets = <&cpg 714>;
2783 status = "disabled";
2784
2785 ports {
2786 #address-cells = <1>;
2787 #size-cells = <0>;
2788
2789 port@0 {
2790 reg = <0>;
2791 };
2792
2793 port@1 {
2794 #address-cells = <1>;
2795 #size-cells = <0>;
2796
2797 reg = <1>;
2798
2799 csi20vin0: endpoint@0 {
2800 reg = <0>;
2801 remote-endpoint = <&vin0csi20>;
2802 };
2803 csi20vin1: endpoint@1 {
2804 reg = <1>;
2805 remote-endpoint = <&vin1csi20>;
2806 };
2807 csi20vin2: endpoint@2 {
2808 reg = <2>;
2809 remote-endpoint = <&vin2csi20>;
2810 };
2811 csi20vin3: endpoint@3 {
2812 reg = <3>;
2813 remote-endpoint = <&vin3csi20>;
2814 };
2815 csi20vin4: endpoint@4 {
2816 reg = <4>;
2817 remote-endpoint = <&vin4csi20>;
2818 };
2819 csi20vin5: endpoint@5 {
2820 reg = <5>;
2821 remote-endpoint = <&vin5csi20>;
2822 };
2823 csi20vin6: endpoint@6 {
2824 reg = <6>;
2825 remote-endpoint = <&vin6csi20>;
2826 };
2827 csi20vin7: endpoint@7 {
2828 reg = <7>;
2829 remote-endpoint = <&vin7csi20>;
2830 };
2831 };
2832 };
2833 };
2834
2835 csi40: csi2@feaa0000 {
2836 compatible = "renesas,r8a7796-csi2";
2837 reg = <0 0xfeaa0000 0 0x10000>;
2838 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2839 clocks = <&cpg CPG_MOD 716>;
2840 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2841 resets = <&cpg 716>;
2842 status = "disabled";
2843
2844 ports {
2845 #address-cells = <1>;
2846 #size-cells = <0>;
2847
2848 port@0 {
2849 reg = <0>;
2850 };
2851
2852 port@1 {
2853 #address-cells = <1>;
2854 #size-cells = <0>;
2855
2856 reg = <1>;
2857
2858 csi40vin0: endpoint@0 {
2859 reg = <0>;
2860 remote-endpoint = <&vin0csi40>;
2861 };
2862 csi40vin1: endpoint@1 {
2863 reg = <1>;
2864 remote-endpoint = <&vin1csi40>;
2865 };
2866 csi40vin2: endpoint@2 {
2867 reg = <2>;
2868 remote-endpoint = <&vin2csi40>;
2869 };
2870 csi40vin3: endpoint@3 {
2871 reg = <3>;
2872 remote-endpoint = <&vin3csi40>;
2873 };
2874 csi40vin4: endpoint@4 {
2875 reg = <4>;
2876 remote-endpoint = <&vin4csi40>;
2877 };
2878 csi40vin5: endpoint@5 {
2879 reg = <5>;
2880 remote-endpoint = <&vin5csi40>;
2881 };
2882 csi40vin6: endpoint@6 {
2883 reg = <6>;
2884 remote-endpoint = <&vin6csi40>;
2885 };
2886 csi40vin7: endpoint@7 {
2887 reg = <7>;
2888 remote-endpoint = <&vin7csi40>;
2889 };
2890 };
2891
2892 };
2893 };
2894
2895 hdmi0: hdmi@fead0000 {
2896 compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi";
2897 reg = <0 0xfead0000 0 0x10000>;
2898 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
2899 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>;
2900 clock-names = "iahb", "isfr";
2901 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2902 resets = <&cpg 729>;
2903 status = "disabled";
2904
2905 ports {
2906 #address-cells = <1>;
2907 #size-cells = <0>;
2908 port@0 {
2909 reg = <0>;
2910 dw_hdmi0_in: endpoint {
2911 remote-endpoint = <&du_out_hdmi0>;
2912 };
2913 };
2914 port@1 {
2915 reg = <1>;
2916 };
2917 port@2 {
2918 /* HDMI sound */
2919 reg = <2>;
2920 };
2921 };
2922 };
2923
2924 du: display@feb00000 {
2925 compatible = "renesas,du-r8a7796";
2926 reg = <0 0xfeb00000 0 0x70000>;
2927 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2928 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2929 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
2930 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
2931 <&cpg CPG_MOD 722>;
2932 clock-names = "du.0", "du.1", "du.2";
2933 resets = <&cpg 724>, <&cpg 722>;
2934 reset-names = "du.0", "du.2";
2935
2936 renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>;
2937 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2938
2939 status = "disabled";
2940
2941 ports {
2942 #address-cells = <1>;
2943 #size-cells = <0>;
2944
2945 port@0 {
2946 reg = <0>;
2947 };
2948 port@1 {
2949 reg = <1>;
2950 du_out_hdmi0: endpoint {
2951 remote-endpoint = <&dw_hdmi0_in>;
2952 };
2953 };
2954 port@2 {
2955 reg = <2>;
2956 du_out_lvds0: endpoint {
2957 remote-endpoint = <&lvds0_in>;
2958 };
2959 };
2960 };
2961 };
2962
2963 lvds0: lvds@feb90000 {
2964 compatible = "renesas,r8a7796-lvds";
2965 reg = <0 0xfeb90000 0 0x14>;
2966 clocks = <&cpg CPG_MOD 727>;
2967 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2968 resets = <&cpg 727>;
2969 status = "disabled";
2970
2971 ports {
2972 #address-cells = <1>;
2973 #size-cells = <0>;
2974
2975 port@0 {
2976 reg = <0>;
2977 lvds0_in: endpoint {
2978 remote-endpoint = <&du_out_lvds0>;
2979 };
2980 };
2981 port@1 {
2982 reg = <1>;
2983 };
2984 };
2985 };
2986
2987 prr: chipid@fff00044 {
2988 compatible = "renesas,prr";
2989 reg = <0 0xfff00044 0 4>;
2990 };
2991 };
2992
2993 thermal-zones {
2994 sensor1_thermal: sensor1-thermal {
2995 polling-delay-passive = <250>;
2996 polling-delay = <1000>;
2997 thermal-sensors = <&tsc 0>;
2998 sustainable-power = <3874>;
2999
3000 trips {
3001 sensor1_crit: sensor1-crit {
3002 temperature = <120000>;
3003 hysteresis = <1000>;
3004 type = "critical";
3005 };
3006 };
3007 };
3008
3009 sensor2_thermal: sensor2-thermal {
3010 polling-delay-passive = <250>;
3011 polling-delay = <1000>;
3012 thermal-sensors = <&tsc 1>;
3013 sustainable-power = <3874>;
3014
3015 trips {
3016 sensor2_crit: sensor2-crit {
3017 temperature = <120000>;
3018 hysteresis = <1000>;
3019 type = "critical";
3020 };
3021 };
3022 };
3023
3024 sensor3_thermal: sensor3-thermal {
3025 polling-delay-passive = <250>;
3026 polling-delay = <1000>;
3027 thermal-sensors = <&tsc 2>;
3028 sustainable-power = <3874>;
3029
3030 cooling-maps {
3031 map0 {
3032 trip = <&target>;
3033 cooling-device = <&a57_0 2 4>;
3034 contribution = <1024>;
3035 };
3036 map1 {
3037 trip = <&target>;
3038 cooling-device = <&a53_0 0 2>;
3039 contribution = <1024>;
3040 };
3041 };
3042 trips {
3043 target: trip-point1 {
3044 temperature = <100000>;
3045 hysteresis = <1000>;
3046 type = "passive";
3047 };
3048
3049 sensor3_crit: sensor3-crit {
3050 temperature = <120000>;
3051 hysteresis = <1000>;
3052 type = "critical";
3053 };
3054 };
3055 };
3056 };
3057
3058 timer {
3059 compatible = "arm,armv8-timer";
3060 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
3061 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
3062 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
3063 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
3064 };
3065
3066 /* External USB clocks - can be overridden by the board */
3067 usb3s0_clk: usb3s0 {
3068 compatible = "fixed-clock";
3069 #clock-cells = <0>;
3070 clock-frequency = <0>;
3071 };
3072
3073 usb_extal_clk: usb_extal {
3074 compatible = "fixed-clock";
3075 #clock-cells = <0>;
3076 clock-frequency = <0>;
3077 };
3078 };
"Das U-Boot" Source Tree