src/arm64/ti/k3-am62a-main.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for AM62A SoC Family Main Domain peripherals
   4  *
   5  * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 &cbass_main {
   9         oc_sram: sram@70000000 {
  10                 compatible = "mmio-sram";
  11                 reg = <0x00 0x70000000 0x00 0x10000>;
  12                 #address-cells = <1>;
  13                 #size-cells = <1>;
  14                 ranges = <0x0 0x00 0x70000000 0x10000>;
  15         };
  16
  17         gic500: interrupt-controller@1800000 {
  18                 compatible = "arm,gic-v3";
  19                 reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
  20                       <0x00 0x01880000 0x00 0xc0000>,   /* GICR */
  21                       <0x00 0x01880000 0x00 0xc0000>,   /* GICR */
  22                       <0x01 0x00000000 0x00 0x2000>,    /* GICC */
  23                       <0x01 0x00010000 0x00 0x1000>,    /* GICH */
  24                       <0x01 0x00020000 0x00 0x2000>;    /* GICV */
  25                 #address-cells = <2>;
  26                 #size-cells = <2>;
  27                 ranges;
  28                 #interrupt-cells = <3>;
  29                 interrupt-controller;
  30                 /*
  31                  * vcpumntirq:
  32                  * virtual CPU interface maintenance interrupt
  33                  */
  34                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  35
  36                 gic_its: msi-controller@1820000 {
  37                         compatible = "arm,gic-v3-its";
  38                         reg = <0x00 0x01820000 0x00 0x10000>;
  39                         socionext,synquacer-pre-its = <0x1000000 0x400000>;
  40                         msi-controller;
  41                         #msi-cells = <1>;
  42                 };
  43         };
  44
  45         main_conf: syscon@100000 {
  46                 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
  47                 reg = <0x00 0x00100000 0x00 0x20000>;
  48                 #address-cells = <1>;
  49                 #size-cells = <1>;
  50                 ranges = <0x00 0x00 0x00100000 0x20000>;
  51
  52                 phy_gmii_sel: phy@4044 {
  53                         compatible = "ti,am654-phy-gmii-sel";
  54                         reg = <0x4044 0x8>;
  55                         #phy-cells = <1>;
  56                 };
  57
  58                 epwm_tbclk: clock-controller@4130 {
  59                         compatible = "ti,am62-epwm-tbclk";
  60                         reg = <0x4130 0x4>;
  61                         #clock-cells = <1>;
  62                 };
  63         };
  64
  65         dmss: bus@48000000 {
  66                 compatible = "simple-bus";
  67                 #address-cells = <2>;
  68                 #size-cells = <2>;
  69                 dma-ranges;
  70                 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>;
  71
  72                 ti,sci-dev-id = <25>;
  73
  74                 secure_proxy_main: mailbox@4d000000 {
  75                         compatible = "ti,am654-secure-proxy";
  76                         reg = <0x00 0x4d000000 0x00 0x80000>,
  77                               <0x00 0x4a600000 0x00 0x80000>,
  78                               <0x00 0x4a400000 0x00 0x80000>;
  79                         reg-names = "target_data", "rt", "scfg";
  80                         #mbox-cells = <1>;
  81                         interrupt-names = "rx_012";
  82                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  83                 };
  84
  85                 inta_main_dmss: interrupt-controller@48000000 {
  86                         compatible = "ti,sci-inta";
  87                         reg = <0x00 0x48000000 0x00 0x100000>;
  88                         #interrupt-cells = <0>;
  89                         interrupt-controller;
  90                         interrupt-parent = <&gic500>;
  91                         msi-controller;
  92                         ti,sci = <&dmsc>;
  93                         ti,sci-dev-id = <28>;
  94                         ti,interrupt-ranges = <6 70 34>;
  95                         ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
  96                 };
  97
  98                 main_bcdma: dma-controller@485c0100 {
  99                         compatible = "ti,am64-dmss-bcdma";
 100                         reg = <0x00 0x485c0100 0x00 0x100>,
 101                               <0x00 0x4c000000 0x00 0x20000>,
 102                               <0x00 0x4a820000 0x00 0x20000>,
 103                               <0x00 0x4aa40000 0x00 0x20000>,
 104                               <0x00 0x4bc00000 0x00 0x100000>,
 105                               <0x00 0x48600000 0x00 0x8000>,
 106                               <0x00 0x484a4000 0x00 0x2000>,
 107                               <0x00 0x484c2000 0x00 0x2000>,
 108                               <0x00 0x48420000 0x00 0x2000>;
 109                         reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
 110                                     "ring", "tchan", "rchan", "bchan";
 111                         msi-parent = <&inta_main_dmss>;
 112                         #dma-cells = <3>;
 113                         ti,sci = <&dmsc>;
 114                         ti,sci-dev-id = <26>;
 115                         ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
 116                         ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
 117                         ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
 118                 };
 119
 120                 main_pktdma: dma-controller@485c0000 {
 121                         compatible = "ti,am64-dmss-pktdma";
 122                         reg = <0x00 0x485c0000 0x00 0x100>,
 123                               <0x00 0x4a800000 0x00 0x20000>,
 124                               <0x00 0x4aa00000 0x00 0x40000>,
 125                               <0x00 0x4b800000 0x00 0x400000>,
 126                               <0x00 0x485e0000 0x00 0x10000>,
 127                               <0x00 0x484a0000 0x00 0x2000>,
 128                               <0x00 0x484c0000 0x00 0x2000>,
 129                               <0x00 0x48430000 0x00 0x1000>;
 130                         reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
 131                                     "ring", "tchan", "rchan", "rflow";
 132                         msi-parent = <&inta_main_dmss>;
 133                         #dma-cells = <2>;
 134                         ti,sci = <&dmsc>;
 135                         ti,sci-dev-id = <30>;
 136                         ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
 137                                                 <0x24>, /* CPSW_TX_CHAN */
 138                                                 <0x25>, /* SAUL_TX_0_CHAN */
 139                                                 <0x26>; /* SAUL_TX_1_CHAN */
 140                         ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
 141                                                 <0x11>, /* RING_CPSW_TX_CHAN */
 142                                                 <0x12>, /* RING_SAUL_TX_0_CHAN */
 143                                                 <0x13>; /* RING_SAUL_TX_1_CHAN */
 144                         ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
 145                                                 <0x2b>, /* CPSW_RX_CHAN */
 146                                                 <0x2d>, /* SAUL_RX_0_CHAN */
 147                                                 <0x2f>, /* SAUL_RX_1_CHAN */
 148                                                 <0x31>, /* SAUL_RX_2_CHAN */
 149                                                 <0x33>; /* SAUL_RX_3_CHAN */
 150                         ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
 151                                                 <0x2c>, /* FLOW_CPSW_RX_CHAN */
 152                                                 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
 153                                                 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
 154                 };
 155         };
 156
 157         dmss_csi: bus@4e000000 {
 158                 compatible = "simple-bus";
 159                 #address-cells = <2>;
 160                 #size-cells = <2>;
 161                 dma-ranges;
 162                 ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x300000>;
 163
 164                 ti,sci-dev-id = <198>;
 165
 166                 inta_main_dmss_csi: interrupt-controller@4e0a0000 {
 167                         compatible = "ti,sci-inta";
 168                         reg = <0x00 0x4e0a0000 0x00 0x8000>;
 169                         #interrupt-cells = <0>;
 170                         interrupt-controller;
 171                         interrupt-parent = <&gic500>;
 172                         msi-controller;
 173                         ti,sci = <&dmsc>;
 174                         ti,sci-dev-id = <200>;
 175                         ti,interrupt-ranges = <0 237 8>;
 176                         ti,unmapped-event-sources = <&main_bcdma_csi>;
 177                         power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
 178                 };
 179
 180                 main_bcdma_csi: dma-controller@4e230000 {
 181                         compatible = "ti,am62a-dmss-bcdma-csirx";
 182                         reg = <0x00 0x4e230000 0x00 0x100>,
 183                               <0x00 0x4e180000 0x00 0x8000>,
 184                               <0x00 0x4e100000 0x00 0x10000>;
 185                         reg-names = "gcfg", "rchanrt", "ringrt";
 186                         msi-parent = <&inta_main_dmss_csi>;
 187                         #dma-cells = <3>;
 188                         ti,sci = <&dmsc>;
 189                         ti,sci-dev-id = <199>;
 190                         ti,sci-rm-range-rchan = <0x21>;
 191                         power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
 192                 };
 193         };
 194
 195         dmsc: system-controller@44043000 {
 196                 compatible = "ti,k2g-sci";
 197                 reg = <0x00 0x44043000 0x00 0xfe0>;
 198                 reg-names = "debug_messages";
 199                 ti,host-id = <12>;
 200                 mbox-names = "rx", "tx";
 201                 mboxes = <&secure_proxy_main 12>,
 202                          <&secure_proxy_main 13>;
 203
 204                 k3_pds: power-controller {
 205                         compatible = "ti,sci-pm-domain";
 206                         #power-domain-cells = <2>;
 207                 };
 208
 209                 k3_clks: clock-controller {
 210                         compatible = "ti,k2g-sci-clk";
 211                         #clock-cells = <2>;
 212                 };
 213
 214                 k3_reset: reset-controller {
 215                         compatible = "ti,sci-reset";
 216                         #reset-cells = <2>;
 217                 };
 218         };
 219
 220         secure_proxy_sa3: mailbox@43600000 {
 221                 compatible = "ti,am654-secure-proxy";
 222                 #mbox-cells = <1>;
 223                 reg-names = "target_data", "rt", "scfg";
 224                 reg = <0x00 0x43600000 0x00 0x10000>,
 225                       <0x00 0x44880000 0x00 0x20000>,
 226                       <0x00 0x44860000 0x00 0x20000>;
 227                 /*
 228                  * Marked Disabled:
 229                  * Node is incomplete as it is meant for bootloaders and
 230                  * firmware on non-MPU processors
 231                  */
 232                 status = "disabled";
 233         };
 234
 235         main_pmx0: pinctrl@f4000 {
 236                 compatible = "pinctrl-single";
 237                 reg = <0x00 0xf4000 0x00 0x2ac>;
 238                 #pinctrl-cells = <1>;
 239                 pinctrl-single,register-width = <32>;
 240                 pinctrl-single,function-mask = <0xffffffff>;
 241         };
 242
 243         main_timer0: timer@2400000 {
 244                 compatible = "ti,am654-timer";
 245                 reg = <0x00 0x2400000 0x00 0x400>;
 246                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 247                 clocks = <&k3_clks 36 2>;
 248                 clock-names = "fck";
 249                 assigned-clocks = <&k3_clks 36 2>;
 250                 assigned-clock-parents = <&k3_clks 36 3>;
 251                 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
 252                 ti,timer-pwm;
 253         };
 254
 255         main_timer1: timer@2410000 {
 256                 compatible = "ti,am654-timer";
 257                 reg = <0x00 0x2410000 0x00 0x400>;
 258                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 259                 clocks = <&k3_clks 37 2>;
 260                 clock-names = "fck";
 261                 assigned-clocks = <&k3_clks 37 2>;
 262                 assigned-clock-parents = <&k3_clks 37 3>;
 263                 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
 264                 ti,timer-pwm;
 265         };
 266
 267         main_timer2: timer@2420000 {
 268                 compatible = "ti,am654-timer";
 269                 reg = <0x00 0x2420000 0x00 0x400>;
 270                 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 271                 clocks = <&k3_clks 38 2>;
 272                 clock-names = "fck";
 273                 assigned-clocks = <&k3_clks 38 2>;
 274                 assigned-clock-parents = <&k3_clks 38 3>;
 275                 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
 276                 ti,timer-pwm;
 277         };
 278
 279         main_timer3: timer@2430000 {
 280                 compatible = "ti,am654-timer";
 281                 reg = <0x00 0x2430000 0x00 0x400>;
 282                 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 283                 clocks = <&k3_clks 39 2>;
 284                 clock-names = "fck";
 285                 assigned-clocks = <&k3_clks 39 2>;
 286                 assigned-clock-parents = <&k3_clks 39 3>;
 287                 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
 288                 ti,timer-pwm;
 289         };
 290
 291         main_timer4: timer@2440000 {
 292                 compatible = "ti,am654-timer";
 293                 reg = <0x00 0x2440000 0x00 0x400>;
 294                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 295                 clocks = <&k3_clks 40 2>;
 296                 clock-names = "fck";
 297                 assigned-clocks = <&k3_clks 40 2>;
 298                 assigned-clock-parents = <&k3_clks 40 3>;
 299                 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
 300                 ti,timer-pwm;
 301         };
 302
 303         main_timer5: timer@2450000 {
 304                 compatible = "ti,am654-timer";
 305                 reg = <0x00 0x2450000 0x00 0x400>;
 306                 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 307                 clocks = <&k3_clks 41 2>;
 308                 clock-names = "fck";
 309                 assigned-clocks = <&k3_clks 41 2>;
 310                 assigned-clock-parents = <&k3_clks 41 3>;
 311                 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
 312                 ti,timer-pwm;
 313         };
 314
 315         main_timer6: timer@2460000 {
 316                 compatible = "ti,am654-timer";
 317                 reg = <0x00 0x2460000 0x00 0x400>;
 318                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 319                 clocks = <&k3_clks 42 2>;
 320                 clock-names = "fck";
 321                 assigned-clocks = <&k3_clks 42 2>;
 322                 assigned-clock-parents = <&k3_clks 42 3>;
 323                 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
 324                 ti,timer-pwm;
 325         };
 326
 327         main_timer7: timer@2470000 {
 328                 compatible = "ti,am654-timer";
 329                 reg = <0x00 0x2470000 0x00 0x400>;
 330                 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 331                 clocks = <&k3_clks 43 2>;
 332                 clock-names = "fck";
 333                 assigned-clocks = <&k3_clks 43 2>;
 334                 assigned-clock-parents = <&k3_clks 43 3>;
 335                 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
 336                 ti,timer-pwm;
 337         };
 338
 339         main_uart0: serial@2800000 {
 340                 compatible = "ti,am64-uart", "ti,am654-uart";
 341                 reg = <0x00 0x02800000 0x00 0x100>;
 342                 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
 343                 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
 344                 clocks = <&k3_clks 146 0>;
 345                 clock-names = "fclk";
 346                 status = "disabled";
 347         };
 348
 349         main_uart1: serial@2810000 {
 350                 compatible = "ti,am64-uart", "ti,am654-uart";
 351                 reg = <0x00 0x02810000 0x00 0x100>;
 352                 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 353                 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
 354                 clocks = <&k3_clks 152 0>;
 355                 clock-names = "fclk";
 356                 status = "disabled";
 357         };
 358
 359         main_uart2: serial@2820000 {
 360                 compatible = "ti,am64-uart", "ti,am654-uart";
 361                 reg = <0x00 0x02820000 0x00 0x100>;
 362                 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 363                 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
 364                 clocks = <&k3_clks 153 0>;
 365                 clock-names = "fclk";
 366                 status = "disabled";
 367         };
 368
 369         main_uart3: serial@2830000 {
 370                 compatible = "ti,am64-uart", "ti,am654-uart";
 371                 reg = <0x00 0x02830000 0x00 0x100>;
 372                 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
 373                 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
 374                 clocks = <&k3_clks 154 0>;
 375                 clock-names = "fclk";
 376                 status = "disabled";
 377         };
 378
 379         main_uart4: serial@2840000 {
 380                 compatible = "ti,am64-uart", "ti,am654-uart";
 381                 reg = <0x00 0x02840000 0x00 0x100>;
 382                 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
 383                 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
 384                 clocks = <&k3_clks 155 0>;
 385                 clock-names = "fclk";
 386                 status = "disabled";
 387         };
 388
 389         main_uart5: serial@2850000 {
 390                 compatible = "ti,am64-uart", "ti,am654-uart";
 391                 reg = <0x00 0x02850000 0x00 0x100>;
 392                 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
 393                 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
 394                 clocks = <&k3_clks 156 0>;
 395                 clock-names = "fclk";
 396                 status = "disabled";
 397         };
 398
 399         main_uart6: serial@2860000 {
 400                 compatible = "ti,am64-uart", "ti,am654-uart";
 401                 reg = <0x00 0x02860000 0x00 0x100>;
 402                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 403                 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
 404                 clocks = <&k3_clks 158 0>;
 405                 clock-names = "fclk";
 406                 status = "disabled";
 407         };
 408
 409         main_i2c0: i2c@20000000 {
 410                 compatible = "ti,am64-i2c", "ti,omap4-i2c";
 411                 reg = <0x00 0x20000000 0x00 0x100>;
 412                 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 413                 #address-cells = <1>;
 414                 #size-cells = <0>;
 415                 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
 416                 clocks = <&k3_clks 102 2>;
 417                 clock-names = "fck";
 418                 status = "disabled";
 419         };
 420
 421         main_i2c1: i2c@20010000 {
 422                 compatible = "ti,am64-i2c", "ti,omap4-i2c";
 423                 reg = <0x00 0x20010000 0x00 0x100>;
 424                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 425                 #address-cells = <1>;
 426                 #size-cells = <0>;
 427                 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
 428                 clocks = <&k3_clks 103 2>;
 429                 clock-names = "fck";
 430                 status = "disabled";
 431         };
 432
 433         main_i2c2: i2c@20020000 {
 434                 compatible = "ti,am64-i2c", "ti,omap4-i2c";
 435                 reg = <0x00 0x20020000 0x00 0x100>;
 436                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 437                 #address-cells = <1>;
 438                 #size-cells = <0>;
 439                 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
 440                 clocks = <&k3_clks 104 2>;
 441                 clock-names = "fck";
 442                 status = "disabled";
 443         };
 444
 445         main_i2c3: i2c@20030000 {
 446                 compatible = "ti,am64-i2c", "ti,omap4-i2c";
 447                 reg = <0x00 0x20030000 0x00 0x100>;
 448                 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 449                 #address-cells = <1>;
 450                 #size-cells = <0>;
 451                 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
 452                 clocks = <&k3_clks 105 2>;
 453                 clock-names = "fck";
 454                 status = "disabled";
 455         };
 456
 457         main_spi0: spi@20100000 {
 458                 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
 459                 reg = <0x00 0x20100000 0x00 0x400>;
 460                 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 461                 #address-cells = <1>;
 462                 #size-cells = <0>;
 463                 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
 464                 clocks = <&k3_clks 141 0>;
 465                 status = "disabled";
 466         };
 467
 468         main_spi1: spi@20110000 {
 469                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 470                 reg = <0x00 0x20110000 0x00 0x400>;
 471                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 472                 #address-cells = <1>;
 473                 #size-cells = <0>;
 474                 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
 475                 clocks = <&k3_clks 142 0>;
 476                 status = "disabled";
 477         };
 478
 479         main_spi2: spi@20120000 {
 480                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 481                 reg = <0x00 0x20120000 0x00 0x400>;
 482                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 483                 #address-cells = <1>;
 484                 #size-cells = <0>;
 485                 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
 486                 clocks = <&k3_clks 143 0>;
 487                 status = "disabled";
 488         };
 489
 490         main_gpio_intr: interrupt-controller@a00000 {
 491                 compatible = "ti,sci-intr";
 492                 reg = <0x00 0x00a00000 0x00 0x800>;
 493                 ti,intr-trigger-type = <1>;
 494                 interrupt-controller;
 495                 interrupt-parent = <&gic500>;
 496                 #interrupt-cells = <1>;
 497                 ti,sci = <&dmsc>;
 498                 ti,sci-dev-id = <3>;
 499                 ti,interrupt-ranges = <0 32 16>;
 500                 status = "disabled";
 501         };
 502
 503         main_gpio0: gpio@600000 {
 504                 compatible = "ti,am64-gpio", "ti,keystone-gpio";
 505                 reg = <0x00 0x00600000 0x0 0x100>;
 506                 gpio-controller;
 507                 #gpio-cells = <2>;
 508                 interrupt-parent = <&main_gpio_intr>;
 509                 interrupts = <190>, <191>, <192>,
 510                              <193>, <194>, <195>;
 511                 interrupt-controller;
 512                 #interrupt-cells = <2>;
 513                 ti,ngpio = <92>;
 514                 ti,davinci-gpio-unbanked = <0>;
 515                 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
 516                 clocks = <&k3_clks 77 0>;
 517                 clock-names = "gpio";
 518                 status = "disabled";
 519         };
 520
 521         main_gpio1: gpio@601000 {
 522                 compatible = "ti,am64-gpio", "ti,keystone-gpio";
 523                 reg = <0x00 0x00601000 0x0 0x100>;
 524                 gpio-controller;
 525                 #gpio-cells = <2>;
 526                 interrupt-parent = <&main_gpio_intr>;
 527                 interrupts = <180>, <181>, <182>,
 528                              <183>, <184>, <185>;
 529                 interrupt-controller;
 530                 #interrupt-cells = <2>;
 531                 ti,ngpio = <52>;
 532                 ti,davinci-gpio-unbanked = <0>;
 533                 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
 534                 clocks = <&k3_clks 78 0>;
 535                 clock-names = "gpio";
 536                 status = "disabled";
 537         };
 538
 539         sdhci1: mmc@fa00000 {
 540                 compatible = "ti,am62-sdhci";
 541                 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
 542                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 543                 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
 544                 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
 545                 clock-names = "clk_ahb", "clk_xin";
 546                 ti,trm-icp = <0x2>;
 547                 ti,otap-del-sel-legacy = <0x0>;
 548                 ti,otap-del-sel-sd-hs = <0x0>;
 549                 ti,otap-del-sel-sdr12 = <0xf>;
 550                 ti,otap-del-sel-sdr25 = <0xf>;
 551                 ti,otap-del-sel-sdr50 = <0xc>;
 552                 ti,otap-del-sel-sdr104 = <0x6>;
 553                 ti,otap-del-sel-ddr50 = <0x9>;
 554                 ti,itap-del-sel-legacy = <0x0>;
 555                 ti,itap-del-sel-sd-hs = <0x0>;
 556                 ti,itap-del-sel-sdr12 = <0x0>;
 557                 ti,itap-del-sel-sdr25 = <0x0>;
 558                 ti,clkbuf-sel = <0x7>;
 559                 bus-width = <4>;
 560                 no-1-8-v;
 561                 status = "disabled";
 562         };
 563
 564         usbss0: dwc3-usb@f900000 {
 565                 compatible = "ti,am62-usb";
 566                 reg = <0x00 0x0f900000 0x00 0x800>;
 567                 clocks = <&k3_clks 161 3>;
 568                 clock-names = "ref";
 569                 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
 570                 #address-cells = <2>;
 571                 #size-cells = <2>;
 572                 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
 573                 ranges;
 574                 status = "disabled";
 575
 576                 usb0: usb@31000000 {
 577                         compatible = "snps,dwc3";
 578                         reg = <0x00 0x31000000 0x00 0x50000>;
 579                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
 580                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
 581                         interrupt-names = "host", "peripheral";
 582                         maximum-speed = "high-speed";
 583                         dr_mode = "otg";
 584                 };
 585         };
 586
 587         usbss1: dwc3-usb@f910000 {
 588                 compatible = "ti,am62-usb";
 589                 reg = <0x00 0x0f910000 0x00 0x800>;
 590                 clocks = <&k3_clks 162 3>;
 591                 clock-names = "ref";
 592                 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
 593                 #address-cells = <2>;
 594                 #size-cells = <2>;
 595                 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
 596                 ranges;
 597                 status = "disabled";
 598
 599                 usb1: usb@31100000 {
 600                         compatible = "snps,dwc3";
 601                         reg = <0x00 0x31100000 0x00 0x50000>;
 602                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
 603                                      <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
 604                         interrupt-names = "host", "peripheral";
 605                         maximum-speed = "high-speed";
 606                         dr_mode = "otg";
 607                 };
 608         };
 609
 610         fss: bus@fc00000 {
 611                 compatible = "simple-bus";
 612                 reg = <0x00 0x0fc00000 0x00 0x70000>;
 613                 #address-cells = <2>;
 614                 #size-cells = <2>;
 615                 ranges;
 616                 status = "disabled";
 617
 618                 ospi0: spi@fc40000 {
 619                         compatible = "ti,am654-ospi", "cdns,qspi-nor";
 620                         reg = <0x00 0x0fc40000 0x00 0x100>,
 621                               <0x05 0x00000000 0x01 0x00000000>;
 622                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 623                         cdns,fifo-depth = <256>;
 624                         cdns,fifo-width = <4>;
 625                         cdns,trigger-address = <0x0>;
 626                         clocks = <&k3_clks 75 7>;
 627                         assigned-clocks = <&k3_clks 75 7>;
 628                         assigned-clock-parents = <&k3_clks 75 8>;
 629                         assigned-clock-rates = <166666666>;
 630                         power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
 631                         #address-cells = <1>;
 632                         #size-cells = <0>;
 633                 };
 634         };
 635
 636         cpsw3g: ethernet@8000000 {
 637                 compatible = "ti,am642-cpsw-nuss";
 638                 #address-cells = <2>;
 639                 #size-cells = <2>;
 640                 reg = <0x0 0x8000000 0x0 0x200000>;
 641                 reg-names = "cpsw_nuss";
 642                 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
 643                 clocks = <&k3_clks 13 0>;
 644                 assigned-clocks = <&k3_clks 13 3>;
 645                 assigned-clock-parents = <&k3_clks 13 11>;
 646                 clock-names = "fck";
 647                 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
 648                 status = "disabled";
 649
 650                 dmas = <&main_pktdma 0xc600 15>,
 651                        <&main_pktdma 0xc601 15>,
 652                        <&main_pktdma 0xc602 15>,
 653                        <&main_pktdma 0xc603 15>,
 654                        <&main_pktdma 0xc604 15>,
 655                        <&main_pktdma 0xc605 15>,
 656                        <&main_pktdma 0xc606 15>,
 657                        <&main_pktdma 0xc607 15>,
 658                        <&main_pktdma 0x4600 15>;
 659                 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
 660                             "tx7", "rx";
 661
 662                 ethernet-ports {
 663                         #address-cells = <1>;
 664                         #size-cells = <0>;
 665
 666                         cpsw_port1: port@1 {
 667                                 reg = <1>;
 668                                 ti,mac-only;
 669                                 label = "port1";
 670                                 phys = <&phy_gmii_sel 1>;
 671                                 mac-address = [00 00 00 00 00 00];
 672                                 ti,syscon-efuse = <&wkup_conf 0x200>;
 673                         };
 674
 675                         cpsw_port2: port@2 {
 676                                 reg = <2>;
 677                                 ti,mac-only;
 678                                 label = "port2";
 679                                 phys = <&phy_gmii_sel 2>;
 680                                 mac-address = [00 00 00 00 00 00];
 681                         };
 682                 };
 683
 684                 cpsw3g_mdio: mdio@f00 {
 685                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 686                         reg = <0x0 0xf00 0x0 0x100>;
 687                         #address-cells = <1>;
 688                         #size-cells = <0>;
 689                         clocks = <&k3_clks 13 0>;
 690                         clock-names = "fck";
 691                         bus_freq = <1000000>;
 692                 };
 693
 694                 cpts@3d000 {
 695                         compatible = "ti,j721e-cpts";
 696                         reg = <0x0 0x3d000 0x0 0x400>;
 697                         clocks = <&k3_clks 13 3>;
 698                         clock-names = "cpts";
 699                         interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 700                         interrupt-names = "cpts";
 701                         ti,cpts-ext-ts-inputs = <4>;
 702                         ti,cpts-periodic-outputs = <2>;
 703                 };
 704         };
 705
 706         hwspinlock: spinlock@2a000000 {
 707                 compatible = "ti,am64-hwspinlock";
 708                 reg = <0x00 0x2a000000 0x00 0x1000>;
 709                 #hwlock-cells = <1>;
 710         };
 711
 712         mailbox0_cluster0: mailbox@29000000 {
 713                 compatible = "ti,am64-mailbox";
 714                 reg = <0x00 0x29000000 0x00 0x200>;
 715                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 716                 #mbox-cells = <1>;
 717                 ti,mbox-num-users = <4>;
 718                 ti,mbox-num-fifos = <16>;
 719         };
 720
 721         mailbox0_cluster1: mailbox@29010000 {
 722                 compatible = "ti,am64-mailbox";
 723                 reg = <0x00 0x29010000 0x00 0x200>;
 724                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 725                 #mbox-cells = <1>;
 726                 ti,mbox-num-users = <4>;
 727                 ti,mbox-num-fifos = <16>;
 728         };
 729
 730         mailbox0_cluster2: mailbox@29020000 {
 731                 compatible = "ti,am64-mailbox";
 732                 reg = <0x00 0x29020000 0x00 0x200>;
 733                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 734                 #mbox-cells = <1>;
 735                 ti,mbox-num-users = <4>;
 736                 ti,mbox-num-fifos = <16>;
 737         };
 738
 739         mailbox0_cluster3: mailbox@29030000 {
 740                 compatible = "ti,am64-mailbox";
 741                 reg = <0x00 0x29030000 0x00 0x200>;
 742                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 743                 #mbox-cells = <1>;
 744                 ti,mbox-num-users = <4>;
 745                 ti,mbox-num-fifos = <16>;
 746         };
 747
 748         main_mcan0: can@20701000 {
 749                 compatible = "bosch,m_can";
 750                 reg = <0x00 0x20701000 0x00 0x200>,
 751                       <0x00 0x20708000 0x00 0x8000>;
 752                 reg-names = "m_can", "message_ram";
 753                 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
 754                 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
 755                 clock-names = "hclk", "cclk";
 756                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 757                              <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 758                 interrupt-names = "int0", "int1";
 759                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 760                 status = "disabled";
 761         };
 762
 763         main_rti0: watchdog@e000000 {
 764                 compatible = "ti,j7-rti-wdt";
 765                 reg = <0x00 0x0e000000 0x00 0x100>;
 766                 clocks = <&k3_clks 125 0>;
 767                 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
 768                 assigned-clocks = <&k3_clks 125 0>;
 769                 assigned-clock-parents = <&k3_clks 125 2>;
 770         };
 771
 772         main_rti1: watchdog@e010000 {
 773                 compatible = "ti,j7-rti-wdt";
 774                 reg = <0x00 0x0e010000 0x00 0x100>;
 775                 clocks = <&k3_clks 126 0>;
 776                 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
 777                 assigned-clocks = <&k3_clks 126 0>;
 778                 assigned-clock-parents = <&k3_clks 126 2>;
 779         };
 780
 781         main_rti2: watchdog@e020000 {
 782                 compatible = "ti,j7-rti-wdt";
 783                 reg = <0x00 0x0e020000 0x00 0x100>;
 784                 clocks = <&k3_clks 127 0>;
 785                 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
 786                 assigned-clocks = <&k3_clks 127 0>;
 787                 assigned-clock-parents = <&k3_clks 127 2>;
 788         };
 789
 790         main_rti3: watchdog@e030000 {
 791                 compatible = "ti,j7-rti-wdt";
 792                 reg = <0x00 0x0e030000 0x00 0x100>;
 793                 clocks = <&k3_clks 128 0>;
 794                 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
 795                 assigned-clocks = <&k3_clks 128 0>;
 796                 assigned-clock-parents = <&k3_clks 128 2>;
 797         };
 798
 799         main_rti4: watchdog@e040000 {
 800                 compatible = "ti,j7-rti-wdt";
 801                 reg = <0x00 0x0e040000 0x00 0x100>;
 802                 clocks = <&k3_clks 205 0>;
 803                 power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>;
 804                 assigned-clocks = <&k3_clks 205 0>;
 805                 assigned-clock-parents = <&k3_clks 205 2>;
 806         };
 807
 808         epwm0: pwm@23000000 {
 809                 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
 810                 #pwm-cells = <3>;
 811                 reg = <0x00 0x23000000 0x00 0x100>;
 812                 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
 813                 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
 814                 clock-names = "tbclk", "fck";
 815                 status = "disabled";
 816         };
 817
 818         epwm1: pwm@23010000 {
 819                 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
 820                 #pwm-cells = <3>;
 821                 reg = <0x00 0x23010000 0x00 0x100>;
 822                 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
 823                 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
 824                 clock-names = "tbclk", "fck";
 825                 status = "disabled";
 826         };
 827
 828         epwm2: pwm@23020000 {
 829                 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
 830                 #pwm-cells = <3>;
 831                 reg = <0x00 0x23020000 0x00 0x100>;
 832                 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
 833                 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
 834                 clock-names = "tbclk", "fck";
 835                 status = "disabled";
 836         };
 837
 838         ecap0: pwm@23100000 {
 839                 compatible = "ti,am3352-ecap";
 840                 #pwm-cells = <3>;
 841                 reg = <0x00 0x23100000 0x00 0x100>;
 842                 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
 843                 clocks = <&k3_clks 51 0>;
 844                 clock-names = "fck";
 845                 status = "disabled";
 846         };
 847
 848         ecap1: pwm@23110000 {
 849                 compatible = "ti,am3352-ecap";
 850                 #pwm-cells = <3>;
 851                 reg = <0x00 0x23110000 0x00 0x100>;
 852                 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
 853                 clocks = <&k3_clks 52 0>;
 854                 clock-names = "fck";
 855                 status = "disabled";
 856         };
 857
 858         ecap2: pwm@23120000 {
 859                 compatible = "ti,am3352-ecap";
 860                 #pwm-cells = <3>;
 861                 reg = <0x00 0x23120000 0x00 0x100>;
 862                 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
 863                 clocks = <&k3_clks 53 0>;
 864                 clock-names = "fck";
 865                 status = "disabled";
 866         };
 867
 868         mcasp0: audio-controller@2b00000 {
 869                 compatible = "ti,am33xx-mcasp-audio";
 870                 reg = <0x00 0x02b00000 0x00 0x2000>,
 871                       <0x00 0x02b08000 0x00 0x400>;
 872                 reg-names = "mpu", "dat";
 873                 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
 874                              <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
 875                 interrupt-names = "tx", "rx";
 876
 877                 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>;
 878                 dma-names = "tx", "rx";
 879
 880                 clocks = <&k3_clks 190 0>;
 881                 clock-names = "fck";
 882                 assigned-clocks = <&k3_clks 190 0>;
 883                 assigned-clock-parents = <&k3_clks 190 2>;
 884                 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
 885                 status = "disabled";
 886         };
 887
 888         mcasp1: audio-controller@2b10000 {
 889                 compatible = "ti,am33xx-mcasp-audio";
 890                 reg = <0x00 0x02b10000 0x00 0x2000>,
 891                       <0x00 0x02b18000 0x00 0x400>;
 892                 reg-names = "mpu", "dat";
 893                 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 894                              <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
 895                 interrupt-names = "tx", "rx";
 896
 897                 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>;
 898                 dma-names = "tx", "rx";
 899
 900                 clocks = <&k3_clks 191 0>;
 901                 clock-names = "fck";
 902                 assigned-clocks = <&k3_clks 191 0>;
 903                 assigned-clock-parents = <&k3_clks 191 2>;
 904                 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
 905                 status = "disabled";
 906         };
 907
 908         mcasp2: audio-controller@2b20000 {
 909                 compatible = "ti,am33xx-mcasp-audio";
 910                 reg = <0x00 0x02b20000 0x00 0x2000>,
 911                       <0x00 0x02b28000 0x00 0x400>;
 912                 reg-names = "mpu", "dat";
 913                 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
 914                              <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 915                 interrupt-names = "tx", "rx";
 916
 917                 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>;
 918                 dma-names = "tx", "rx";
 919
 920                 clocks = <&k3_clks 192 0>;
 921                 clock-names = "fck";
 922                 assigned-clocks = <&k3_clks 192 0>;
 923                 assigned-clock-parents = <&k3_clks 192 2>;
 924                 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
 925                 status = "disabled";
 926         };
 927
 928         ti_csi2rx0: ticsi2rx@30102000 {
 929                 compatible = "ti,j721e-csi2rx-shim";
 930                 dmas = <&main_bcdma_csi 0 0x5000 0>;
 931                 dma-names = "rx0";
 932                 reg = <0x00 0x30102000 0x00 0x1000>;
 933                 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
 934                 #address-cells = <2>;
 935                 #size-cells = <2>;
 936                 ranges;
 937                 status = "disabled";
 938
 939                 cdns_csi2rx0: csi-bridge@30101000 {
 940                         compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
 941                         reg = <0x00 0x30101000 0x00 0x1000>;
 942                         clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
 943                                 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
 944                         clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
 945                                 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
 946                         phys = <&dphy0>;
 947                         phy-names = "dphy";
 948
 949                         ports {
 950                                 #address-cells = <1>;
 951                                 #size-cells = <0>;
 952
 953                                 csi0_port0: port@0 {
 954                                         reg = <0>;
 955                                         status = "disabled";
 956                                 };
 957
 958                                 csi0_port1: port@1 {
 959                                         reg = <1>;
 960                                         status = "disabled";
 961                                 };
 962
 963                                 csi0_port2: port@2 {
 964                                         reg = <2>;
 965                                         status = "disabled";
 966                                 };
 967
 968                                 csi0_port3: port@3 {
 969                                         reg = <3>;
 970                                         status = "disabled";
 971                                 };
 972
 973                                 csi0_port4: port@4 {
 974                                         reg = <4>;
 975                                         status = "disabled";
 976                                 };
 977                         };
 978                 };
 979         };
 980
 981         dphy0: phy@30110000 {
 982                 compatible = "cdns,dphy-rx";
 983                 reg = <0x00 0x30110000 0x00 0x1100>;
 984                 #phy-cells = <0>;
 985                 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
 986                 status = "disabled";
 987         };
 988 };