src/arm64/ti/k3-am62a-mcu.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for AM625 SoC Family MCU Domain peripherals
   4  *
   5  * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 &cbass_mcu {
   9         mcu_pmx0: pinctrl@4084000 {
  10                 compatible = "pinctrl-single";
  11                 reg = <0x00 0x04084000 0x00 0x88>;
  12                 #pinctrl-cells = <1>;
  13                 pinctrl-single,register-width = <32>;
  14                 pinctrl-single,function-mask = <0xffffffff>;
  15                 status = "disabled";
  16         };
  17
  18         /*
  19          * The MCU domain timer interrupts are routed only to the ESM module,
  20          * and not currently available for Linux. The MCU domain timers are
  21          * of limited use without interrupts, and likely reserved by the ESM.
  22          */
  23         mcu_timer0: timer@4800000 {
  24                 compatible = "ti,am654-timer";
  25                 reg = <0x00 0x4800000 0x00 0x400>;
  26                 clocks = <&k3_clks 35 2>;
  27                 clock-names = "fck";
  28                 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
  29                 ti,timer-pwm;
  30                 status = "reserved";
  31         };
  32
  33         mcu_timer1: timer@4810000 {
  34                 compatible = "ti,am654-timer";
  35                 reg = <0x00 0x4810000 0x00 0x400>;
  36                 clocks = <&k3_clks 48 2>;
  37                 clock-names = "fck";
  38                 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
  39                 ti,timer-pwm;
  40                 status = "reserved";
  41         };
  42
  43         mcu_timer2: timer@4820000 {
  44                 compatible = "ti,am654-timer";
  45                 reg = <0x00 0x4820000 0x00 0x400>;
  46                 clocks = <&k3_clks 49 2>;
  47                 clock-names = "fck";
  48                 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
  49                 ti,timer-pwm;
  50                 status = "reserved";
  51         };
  52
  53         mcu_timer3: timer@4830000 {
  54                 compatible = "ti,am654-timer";
  55                 reg = <0x00 0x4830000 0x00 0x400>;
  56                 clocks = <&k3_clks 50 2>;
  57                 clock-names = "fck";
  58                 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
  59                 ti,timer-pwm;
  60                 status = "reserved";
  61         };
  62
  63         mcu_uart0: serial@4a00000 {
  64                 compatible = "ti,am64-uart", "ti,am654-uart";
  65                 reg = <0x00 0x04a00000 0x00 0x100>;
  66                 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
  67                 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
  68                 clocks = <&k3_clks 149 0>;
  69                 clock-names = "fclk";
  70                 status = "disabled";
  71         };
  72
  73         mcu_i2c0: i2c@4900000 {
  74                 compatible = "ti,am64-i2c", "ti,omap4-i2c";
  75                 reg = <0x00 0x04900000 0x00 0x100>;
  76                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
  77                 #address-cells = <1>;
  78                 #size-cells = <0>;
  79                 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
  80                 clocks = <&k3_clks 106 2>;
  81                 clock-names = "fck";
  82                 status = "disabled";
  83         };
  84
  85         mcu_spi0: spi@4b00000 {
  86                 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
  87                 reg = <0x00 0x04b00000 0x00 0x400>;
  88                 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
  89                 #address-cells = <1>;
  90                 #size-cells = <0>;
  91                 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
  92                 clocks = <&k3_clks 147 0>;
  93                 status = "disabled";
  94         };
  95
  96         mcu_spi1: spi@4b10000 {
  97                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
  98                 reg = <0x00 0x04b10000 0x00 0x400>;
  99                 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 100                 #address-cells = <1>;
 101                 #size-cells = <0>;
 102                 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
 103                 clocks = <&k3_clks 148 0>;
 104                 status = "disabled";
 105         };
 106
 107         mcu_gpio_intr: interrupt-controller@4210000 {
 108                 compatible = "ti,sci-intr";
 109                 reg = <0x00 0x04210000 0x00 0x200>;
 110                 ti,intr-trigger-type = <1>;
 111                 interrupt-controller;
 112                 interrupt-parent = <&gic500>;
 113                 #interrupt-cells = <1>;
 114                 ti,sci = <&dmsc>;
 115                 ti,sci-dev-id = <5>;
 116                 ti,interrupt-ranges = <0 104 4>;
 117         };
 118
 119         mcu_gpio0: gpio@4201000 {
 120                 compatible = "ti,am64-gpio", "ti,keystone-gpio";
 121                 reg = <0x00 0x04201000 0x00 0x100>;
 122                 gpio-controller;
 123                 #gpio-cells = <2>;
 124                 interrupt-parent = <&mcu_gpio_intr>;
 125                 interrupts = <30>, <31>;
 126                 interrupt-controller;
 127                 #interrupt-cells = <2>;
 128                 ti,ngpio = <24>;
 129                 ti,davinci-gpio-unbanked = <0>;
 130                 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
 131                 clocks = <&k3_clks 79 0>;
 132                 clock-names = "gpio";
 133                 status = "disabled";
 134         };
 135
 136         mcu_rti0: watchdog@4880000 {
 137                 compatible = "ti,j7-rti-wdt";
 138                 reg = <0x00 0x04880000 0x00 0x100>;
 139                 clocks = <&k3_clks 131 0>;
 140                 power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>;
 141                 assigned-clocks = <&k3_clks 131 0>;
 142                 assigned-clock-parents = <&k3_clks 131 2>;
 143                 /* Tightly coupled to M4F */
 144                 status = "reserved";
 145         };
 146
 147         mcu_mcan0: can@4e08000 {
 148                 compatible = "bosch,m_can";
 149                 reg = <0x00 0x4e08000 0x00 0x200>,
 150                       <0x00 0x4e00000 0x00 0x8000>;
 151                 reg-names = "m_can", "message_ram";
 152                 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
 153                 clocks = <&k3_clks 188 6>, <&k3_clks 188 1>;
 154                 clock-names = "hclk", "cclk";
 155                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 156                 status = "disabled";
 157         };
 158
 159         mcu_mcan1: can@4e18000 {
 160                 compatible = "bosch,m_can";
 161                 reg = <0x00 0x4e18000 0x00 0x200>,
 162                       <0x00 0x4e10000 0x00 0x8000>;
 163                 reg-names = "m_can", "message_ram";
 164                 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
 165                 clocks = <&k3_clks 189 6>, <&k3_clks 189 1>;
 166                 clock-names = "hclk", "cclk";
 167                 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
 168                 status = "disabled";
 169         };
 170 };