1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for J721E SoC Family Main Domain peripherals
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
20 cmn_refclk1: clock-cmnrefclk1 {
22 compatible = "fixed-clock";
23 clock-frequency = <0>;
28 msmc_ram: sram@70000000 {
29 compatible = "mmio-sram";
30 reg = <0x0 0x70000000 0x0 0x800000>;
33 ranges = <0x0 0x0 0x70000000 0x800000>;
40 scm_conf: scm-conf@100000 {
41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
45 ranges = <0x0 0x0 0x00100000 0x1c000>;
47 serdes_ln_ctrl: mux-controller@4080 {
48 compatible = "mmio-mux";
49 reg = <0x00004080 0x50>;
50 #mux-control-cells = <1>;
51 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
52 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
53 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
54 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
55 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
56 /* SERDES4 lane0/1/2/3 select */
57 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
58 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
59 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
60 <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>,
61 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
62 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
65 cpsw0_phy_gmii_sel: phy@4044 {
66 compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
67 ti,qsgmii-main-ports = <2>, <2>;
72 usb_serdes_mux: mux-controller@4000 {
73 compatible = "mmio-mux";
74 #mux-control-cells = <1>;
75 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
76 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
79 ehrpwm_tbclk: clock-controller@4140 {
80 compatible = "ti,am654-ehrpwm-tbclk";
86 main_ehrpwm0: pwm@3000000 {
87 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
89 reg = <0x00 0x3000000 0x00 0x100>;
90 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
91 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>;
92 clock-names = "tbclk", "fck";
96 main_ehrpwm1: pwm@3010000 {
97 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
99 reg = <0x00 0x3010000 0x00 0x100>;
100 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
101 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>;
102 clock-names = "tbclk", "fck";
106 main_ehrpwm2: pwm@3020000 {
107 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
109 reg = <0x00 0x3020000 0x00 0x100>;
110 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
111 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>;
112 clock-names = "tbclk", "fck";
116 main_ehrpwm3: pwm@3030000 {
117 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
119 reg = <0x00 0x3030000 0x00 0x100>;
120 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
121 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>;
122 clock-names = "tbclk", "fck";
126 main_ehrpwm4: pwm@3040000 {
127 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
129 reg = <0x00 0x3040000 0x00 0x100>;
130 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
131 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>;
132 clock-names = "tbclk", "fck";
136 main_ehrpwm5: pwm@3050000 {
137 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
139 reg = <0x00 0x3050000 0x00 0x100>;
140 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
141 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>;
142 clock-names = "tbclk", "fck";
146 gic500: interrupt-controller@1800000 {
147 compatible = "arm,gic-v3";
148 #address-cells = <2>;
151 #interrupt-cells = <3>;
152 interrupt-controller;
153 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
154 <0x00 0x01900000 0x00 0x100000>, /* GICR */
155 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
156 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
157 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
159 /* vcpumntirq: virtual CPU interface maintenance interrupt */
160 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
162 gic_its: msi-controller@1820000 {
163 compatible = "arm,gic-v3-its";
164 reg = <0x00 0x01820000 0x00 0x10000>;
165 socionext,synquacer-pre-its = <0x1000000 0x400000>;
171 main_gpio_intr: interrupt-controller@a00000 {
172 compatible = "ti,sci-intr";
173 reg = <0x00 0x00a00000 0x00 0x800>;
174 ti,intr-trigger-type = <1>;
175 interrupt-controller;
176 interrupt-parent = <&gic500>;
177 #interrupt-cells = <1>;
179 ti,sci-dev-id = <131>;
180 ti,interrupt-ranges = <8 392 56>;
183 main_navss: bus@30000000 {
184 compatible = "simple-bus";
185 #address-cells = <2>;
187 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
191 ti,sci-dev-id = <199>;
193 main_navss_intr: interrupt-controller@310e0000 {
194 compatible = "ti,sci-intr";
195 reg = <0x0 0x310e0000 0x0 0x4000>;
196 ti,intr-trigger-type = <4>;
197 interrupt-controller;
198 interrupt-parent = <&gic500>;
199 #interrupt-cells = <1>;
201 ti,sci-dev-id = <213>;
202 ti,interrupt-ranges = <0 64 64>,
207 main_udmass_inta: interrupt-controller@33d00000 {
208 compatible = "ti,sci-inta";
209 reg = <0x0 0x33d00000 0x0 0x100000>;
210 interrupt-controller;
211 interrupt-parent = <&main_navss_intr>;
213 #interrupt-cells = <0>;
215 ti,sci-dev-id = <209>;
216 ti,interrupt-ranges = <0 0 256>;
219 secure_proxy_main: mailbox@32c00000 {
220 compatible = "ti,am654-secure-proxy";
222 reg-names = "target_data", "rt", "scfg";
223 reg = <0x00 0x32c00000 0x00 0x100000>,
224 <0x00 0x32400000 0x00 0x100000>,
225 <0x00 0x32800000 0x00 0x100000>;
226 interrupt-names = "rx_011";
227 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
230 smmu0: iommu@36600000 {
231 compatible = "arm,smmu-v3";
232 reg = <0x0 0x36600000 0x0 0x100000>;
233 interrupt-parent = <&gic500>;
234 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
235 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
236 interrupt-names = "eventq", "gerror";
240 hwspinlock: spinlock@30e00000 {
241 compatible = "ti,am654-hwspinlock";
242 reg = <0x00 0x30e00000 0x00 0x1000>;
246 mailbox0_cluster0: mailbox@31f80000 {
247 compatible = "ti,am654-mailbox";
248 reg = <0x00 0x31f80000 0x00 0x200>;
250 ti,mbox-num-users = <4>;
251 ti,mbox-num-fifos = <16>;
252 interrupt-parent = <&main_navss_intr>;
256 mailbox0_cluster1: mailbox@31f81000 {
257 compatible = "ti,am654-mailbox";
258 reg = <0x00 0x31f81000 0x00 0x200>;
260 ti,mbox-num-users = <4>;
261 ti,mbox-num-fifos = <16>;
262 interrupt-parent = <&main_navss_intr>;
266 mailbox0_cluster2: mailbox@31f82000 {
267 compatible = "ti,am654-mailbox";
268 reg = <0x00 0x31f82000 0x00 0x200>;
270 ti,mbox-num-users = <4>;
271 ti,mbox-num-fifos = <16>;
272 interrupt-parent = <&main_navss_intr>;
276 mailbox0_cluster3: mailbox@31f83000 {
277 compatible = "ti,am654-mailbox";
278 reg = <0x00 0x31f83000 0x00 0x200>;
280 ti,mbox-num-users = <4>;
281 ti,mbox-num-fifos = <16>;
282 interrupt-parent = <&main_navss_intr>;
286 mailbox0_cluster4: mailbox@31f84000 {
287 compatible = "ti,am654-mailbox";
288 reg = <0x00 0x31f84000 0x00 0x200>;
290 ti,mbox-num-users = <4>;
291 ti,mbox-num-fifos = <16>;
292 interrupt-parent = <&main_navss_intr>;
296 mailbox0_cluster5: mailbox@31f85000 {
297 compatible = "ti,am654-mailbox";
298 reg = <0x00 0x31f85000 0x00 0x200>;
300 ti,mbox-num-users = <4>;
301 ti,mbox-num-fifos = <16>;
302 interrupt-parent = <&main_navss_intr>;
306 mailbox0_cluster6: mailbox@31f86000 {
307 compatible = "ti,am654-mailbox";
308 reg = <0x00 0x31f86000 0x00 0x200>;
310 ti,mbox-num-users = <4>;
311 ti,mbox-num-fifos = <16>;
312 interrupt-parent = <&main_navss_intr>;
316 mailbox0_cluster7: mailbox@31f87000 {
317 compatible = "ti,am654-mailbox";
318 reg = <0x00 0x31f87000 0x00 0x200>;
320 ti,mbox-num-users = <4>;
321 ti,mbox-num-fifos = <16>;
322 interrupt-parent = <&main_navss_intr>;
326 mailbox0_cluster8: mailbox@31f88000 {
327 compatible = "ti,am654-mailbox";
328 reg = <0x00 0x31f88000 0x00 0x200>;
330 ti,mbox-num-users = <4>;
331 ti,mbox-num-fifos = <16>;
332 interrupt-parent = <&main_navss_intr>;
336 mailbox0_cluster9: mailbox@31f89000 {
337 compatible = "ti,am654-mailbox";
338 reg = <0x00 0x31f89000 0x00 0x200>;
340 ti,mbox-num-users = <4>;
341 ti,mbox-num-fifos = <16>;
342 interrupt-parent = <&main_navss_intr>;
346 mailbox0_cluster10: mailbox@31f8a000 {
347 compatible = "ti,am654-mailbox";
348 reg = <0x00 0x31f8a000 0x00 0x200>;
350 ti,mbox-num-users = <4>;
351 ti,mbox-num-fifos = <16>;
352 interrupt-parent = <&main_navss_intr>;
356 mailbox0_cluster11: mailbox@31f8b000 {
357 compatible = "ti,am654-mailbox";
358 reg = <0x00 0x31f8b000 0x00 0x200>;
360 ti,mbox-num-users = <4>;
361 ti,mbox-num-fifos = <16>;
362 interrupt-parent = <&main_navss_intr>;
366 main_ringacc: ringacc@3c000000 {
367 compatible = "ti,am654-navss-ringacc";
368 reg = <0x0 0x3c000000 0x0 0x400000>,
369 <0x0 0x38000000 0x0 0x400000>,
370 <0x0 0x31120000 0x0 0x100>,
371 <0x0 0x33000000 0x0 0x40000>,
372 <0x0 0x31080000 0x0 0x40000>;
373 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
374 ti,num-rings = <1024>;
375 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
377 ti,sci-dev-id = <211>;
378 msi-parent = <&main_udmass_inta>;
381 main_udmap: dma-controller@31150000 {
382 compatible = "ti,j721e-navss-main-udmap";
383 reg = <0x0 0x31150000 0x0 0x100>,
384 <0x0 0x34000000 0x0 0x100000>,
385 <0x0 0x35000000 0x0 0x100000>,
386 <0x0 0x30b00000 0x0 0x20000>,
387 <0x0 0x30c00000 0x0 0x10000>,
388 <0x0 0x30d00000 0x0 0x8000>;
389 reg-names = "gcfg", "rchanrt", "tchanrt",
390 "tchan", "rchan", "rflow";
391 msi-parent = <&main_udmass_inta>;
395 ti,sci-dev-id = <212>;
396 ti,ringacc = <&main_ringacc>;
398 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
399 <0x0f>, /* TX_HCHAN */
400 <0x10>; /* TX_UHCHAN */
401 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
402 <0x0b>, /* RX_HCHAN */
403 <0x0c>; /* RX_UHCHAN */
404 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
408 compatible = "ti,j721e-cpts";
409 reg = <0x0 0x310d0000 0x0 0x400>;
411 clocks = <&k3_clks 201 1>;
412 clock-names = "cpts";
413 interrupts-extended = <&main_navss_intr 391>;
414 interrupt-names = "cpts";
415 ti,cpts-periodic-outputs = <6>;
416 ti,cpts-ext-ts-inputs = <8>;
420 cpsw0: ethernet@c000000 {
421 compatible = "ti,j721e-cpswxg-nuss";
422 #address-cells = <2>;
424 reg = <0x0 0xc000000 0x0 0x200000>;
425 reg-names = "cpsw_nuss";
426 ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>;
427 clocks = <&k3_clks 19 89>;
429 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
431 dmas = <&main_udmap 0xca00>,
432 <&main_udmap 0xca01>,
433 <&main_udmap 0xca02>,
434 <&main_udmap 0xca03>,
435 <&main_udmap 0xca04>,
436 <&main_udmap 0xca05>,
437 <&main_udmap 0xca06>,
438 <&main_udmap 0xca07>,
439 <&main_udmap 0x4a00>;
440 dma-names = "tx0", "tx1", "tx2", "tx3",
441 "tx4", "tx5", "tx6", "tx7",
447 #address-cells = <1>;
449 cpsw0_port1: port@1 {
456 cpsw0_port2: port@2 {
463 cpsw0_port3: port@3 {
470 cpsw0_port4: port@4 {
477 cpsw0_port5: port@5 {
484 cpsw0_port6: port@6 {
491 cpsw0_port7: port@7 {
498 cpsw0_port8: port@8 {
506 cpsw9g_mdio: mdio@f00 {
507 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
508 reg = <0x0 0xf00 0x0 0x100>;
509 #address-cells = <1>;
511 clocks = <&k3_clks 19 89>;
513 bus_freq = <1000000>;
518 compatible = "ti,j721e-cpts";
519 reg = <0x0 0x3d000 0x0 0x400>;
520 clocks = <&k3_clks 19 16>;
521 clock-names = "cpts";
522 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
523 interrupt-names = "cpts";
524 ti,cpts-ext-ts-inputs = <4>;
525 ti,cpts-periodic-outputs = <2>;
529 main_crypto: crypto@4e00000 {
530 compatible = "ti,j721e-sa2ul";
531 reg = <0x0 0x4e00000 0x0 0x1200>;
532 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
533 #address-cells = <2>;
535 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
537 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
538 <&main_udmap 0x4001>;
539 dma-names = "tx", "rx1", "rx2";
542 compatible = "inside-secure,safexcel-eip76";
543 reg = <0x0 0x4e10000 0x0 0x7d>;
544 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
548 main_pmx0: pinctrl@11c000 {
549 compatible = "pinctrl-single";
550 /* Proxy 0 addressing */
551 reg = <0x0 0x11c000 0x0 0x2b4>;
552 #pinctrl-cells = <1>;
553 pinctrl-single,register-width = <32>;
554 pinctrl-single,function-mask = <0xffffffff>;
557 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
558 main_timerio_input: pinctrl@104200 {
559 compatible = "pinctrl-single";
560 reg = <0x00 0x104200 0x00 0x50>;
561 #pinctrl-cells = <1>;
562 pinctrl-single,register-width = <32>;
563 pinctrl-single,function-mask = <0x00000007>;
566 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
567 main_timerio_output: pinctrl@104280 {
568 compatible = "pinctrl-single";
569 reg = <0x00 0x104280 0x00 0x20>;
570 #pinctrl-cells = <1>;
571 pinctrl-single,register-width = <32>;
572 pinctrl-single,function-mask = <0x0000001f>;
575 serdes_wiz0: wiz@5000000 {
576 compatible = "ti,j721e-wiz-16g";
577 #address-cells = <1>;
579 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
580 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>;
581 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
582 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
583 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
586 ranges = <0x5000000 0x0 0x5000000 0x10000>;
588 wiz0_pll0_refclk: pll0-refclk {
589 clocks = <&k3_clks 292 11>, <&cmn_refclk>;
591 assigned-clocks = <&wiz0_pll0_refclk>;
592 assigned-clock-parents = <&k3_clks 292 11>;
595 wiz0_pll1_refclk: pll1-refclk {
596 clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
598 assigned-clocks = <&wiz0_pll1_refclk>;
599 assigned-clock-parents = <&k3_clks 292 0>;
602 wiz0_refclk_dig: refclk-dig {
603 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
605 assigned-clocks = <&wiz0_refclk_dig>;
606 assigned-clock-parents = <&k3_clks 292 11>;
609 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
610 clocks = <&wiz0_refclk_dig>;
614 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
615 clocks = <&wiz0_pll1_refclk>;
619 serdes0: serdes@5000000 {
620 compatible = "ti,sierra-phy-t0";
621 reg-names = "serdes";
622 reg = <0x5000000 0x10000>;
623 #address-cells = <1>;
626 resets = <&serdes_wiz0 0>;
627 reset-names = "sierra_reset";
628 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>,
629 <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>;
630 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
631 "pll0_refclk", "pll1_refclk";
635 serdes_wiz1: wiz@5010000 {
636 compatible = "ti,j721e-wiz-16g";
637 #address-cells = <1>;
639 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
640 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>;
641 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
642 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
643 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
646 ranges = <0x5010000 0x0 0x5010000 0x10000>;
648 wiz1_pll0_refclk: pll0-refclk {
649 clocks = <&k3_clks 293 13>, <&cmn_refclk>;
651 assigned-clocks = <&wiz1_pll0_refclk>;
652 assigned-clock-parents = <&k3_clks 293 13>;
655 wiz1_pll1_refclk: pll1-refclk {
656 clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
658 assigned-clocks = <&wiz1_pll1_refclk>;
659 assigned-clock-parents = <&k3_clks 293 0>;
662 wiz1_refclk_dig: refclk-dig {
663 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
665 assigned-clocks = <&wiz1_refclk_dig>;
666 assigned-clock-parents = <&k3_clks 293 13>;
669 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div {
670 clocks = <&wiz1_refclk_dig>;
674 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
675 clocks = <&wiz1_pll1_refclk>;
679 serdes1: serdes@5010000 {
680 compatible = "ti,sierra-phy-t0";
681 reg-names = "serdes";
682 reg = <0x5010000 0x10000>;
683 #address-cells = <1>;
686 resets = <&serdes_wiz1 0>;
687 reset-names = "sierra_reset";
688 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>,
689 <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>;
690 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
691 "pll0_refclk", "pll1_refclk";
695 serdes_wiz2: wiz@5020000 {
696 compatible = "ti,j721e-wiz-16g";
697 #address-cells = <1>;
699 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
700 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>;
701 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
702 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
703 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
706 ranges = <0x5020000 0x0 0x5020000 0x10000>;
708 wiz2_pll0_refclk: pll0-refclk {
709 clocks = <&k3_clks 294 11>, <&cmn_refclk>;
711 assigned-clocks = <&wiz2_pll0_refclk>;
712 assigned-clock-parents = <&k3_clks 294 11>;
715 wiz2_pll1_refclk: pll1-refclk {
716 clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
718 assigned-clocks = <&wiz2_pll1_refclk>;
719 assigned-clock-parents = <&k3_clks 294 0>;
722 wiz2_refclk_dig: refclk-dig {
723 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
725 assigned-clocks = <&wiz2_refclk_dig>;
726 assigned-clock-parents = <&k3_clks 294 11>;
729 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
730 clocks = <&wiz2_refclk_dig>;
734 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
735 clocks = <&wiz2_pll1_refclk>;
739 serdes2: serdes@5020000 {
740 compatible = "ti,sierra-phy-t0";
741 reg-names = "serdes";
742 reg = <0x5020000 0x10000>;
743 #address-cells = <1>;
746 resets = <&serdes_wiz2 0>;
747 reset-names = "sierra_reset";
748 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>,
749 <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>;
750 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
751 "pll0_refclk", "pll1_refclk";
755 serdes_wiz3: wiz@5030000 {
756 compatible = "ti,j721e-wiz-16g";
757 #address-cells = <1>;
759 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
760 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>;
761 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
762 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
763 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
766 ranges = <0x5030000 0x0 0x5030000 0x10000>;
768 wiz3_pll0_refclk: pll0-refclk {
769 clocks = <&k3_clks 295 9>, <&cmn_refclk>;
771 assigned-clocks = <&wiz3_pll0_refclk>;
772 assigned-clock-parents = <&k3_clks 295 9>;
775 wiz3_pll1_refclk: pll1-refclk {
776 clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
778 assigned-clocks = <&wiz3_pll1_refclk>;
779 assigned-clock-parents = <&k3_clks 295 0>;
782 wiz3_refclk_dig: refclk-dig {
783 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
785 assigned-clocks = <&wiz3_refclk_dig>;
786 assigned-clock-parents = <&k3_clks 295 9>;
789 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
790 clocks = <&wiz3_refclk_dig>;
794 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
795 clocks = <&wiz3_pll1_refclk>;
799 serdes3: serdes@5030000 {
800 compatible = "ti,sierra-phy-t0";
801 reg-names = "serdes";
802 reg = <0x5030000 0x10000>;
803 #address-cells = <1>;
806 resets = <&serdes_wiz3 0>;
807 reset-names = "sierra_reset";
808 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>,
809 <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>;
810 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
811 "pll0_refclk", "pll1_refclk";
815 pcie0_rc: pcie@2900000 {
816 compatible = "ti,j721e-pcie-host";
817 reg = <0x00 0x02900000 0x00 0x1000>,
818 <0x00 0x02907000 0x00 0x400>,
819 <0x00 0x0d000000 0x00 0x00800000>,
820 <0x00 0x10000000 0x00 0x00001000>;
821 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
822 interrupt-names = "link_state";
823 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
825 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
826 max-link-speed = <3>;
828 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
829 clocks = <&k3_clks 239 1>;
831 #address-cells = <3>;
833 bus-range = <0x0 0xff>;
834 vendor-id = <0x104c>;
835 device-id = <0xb00d>;
836 msi-map = <0x0 &gic_its 0x0 0x10000>;
838 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
839 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
840 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
844 pcie1_rc: pcie@2910000 {
845 compatible = "ti,j721e-pcie-host";
846 reg = <0x00 0x02910000 0x00 0x1000>,
847 <0x00 0x02917000 0x00 0x400>,
848 <0x00 0x0d800000 0x00 0x00800000>,
849 <0x00 0x18000000 0x00 0x00001000>;
850 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
851 interrupt-names = "link_state";
852 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
854 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
855 max-link-speed = <3>;
857 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
858 clocks = <&k3_clks 240 1>;
860 #address-cells = <3>;
862 bus-range = <0x0 0xff>;
863 vendor-id = <0x104c>;
864 device-id = <0xb00d>;
865 msi-map = <0x0 &gic_its 0x10000 0x10000>;
867 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
868 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
869 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
873 pcie2_rc: pcie@2920000 {
874 compatible = "ti,j721e-pcie-host";
875 reg = <0x00 0x02920000 0x00 0x1000>,
876 <0x00 0x02927000 0x00 0x400>,
877 <0x00 0x0e000000 0x00 0x00800000>,
878 <0x44 0x00000000 0x00 0x00001000>;
879 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
880 interrupt-names = "link_state";
881 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
883 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
884 max-link-speed = <3>;
886 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
887 clocks = <&k3_clks 241 1>;
889 #address-cells = <3>;
891 bus-range = <0x0 0xff>;
892 vendor-id = <0x104c>;
893 device-id = <0xb00d>;
894 msi-map = <0x0 &gic_its 0x20000 0x10000>;
896 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
897 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
898 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
902 pcie3_rc: pcie@2930000 {
903 compatible = "ti,j721e-pcie-host";
904 reg = <0x00 0x02930000 0x00 0x1000>,
905 <0x00 0x02937000 0x00 0x400>,
906 <0x00 0x0e800000 0x00 0x00800000>,
907 <0x44 0x10000000 0x00 0x00001000>;
908 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
909 interrupt-names = "link_state";
910 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
912 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
913 max-link-speed = <3>;
915 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
916 clocks = <&k3_clks 242 1>;
918 #address-cells = <3>;
920 bus-range = <0x0 0xff>;
921 vendor-id = <0x104c>;
922 device-id = <0xb00d>;
923 msi-map = <0x0 &gic_its 0x30000 0x10000>;
925 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
926 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
927 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
931 serdes_wiz4: wiz@5050000 {
932 compatible = "ti,am64-wiz-10g";
933 #address-cells = <1>;
935 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
936 clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>;
937 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
938 assigned-clocks = <&k3_clks 297 9>;
939 assigned-clock-parents = <&k3_clks 297 10>;
940 assigned-clock-rates = <19200000>;
944 ranges = <0x05050000 0x00 0x05050000 0x010000>,
945 <0x0a030a00 0x00 0x0a030a00 0x40>;
947 serdes4: serdes@5050000 {
949 * Note: we also map DPTX PHY registers as the Torrent
950 * needs to manage those.
952 compatible = "ti,j721e-serdes-10g";
953 reg = <0x05050000 0x010000>,
954 <0x0a030a00 0x40>; /* DPTX PHY */
955 reg-names = "torrent_phy", "dptx_phy";
957 resets = <&serdes_wiz4 0>;
958 reset-names = "torrent_reset";
959 clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>;
960 clock-names = "refclk";
961 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
962 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
963 <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
964 assigned-clock-parents = <&k3_clks 297 9>,
967 #address-cells = <1>;
972 main_timer0: timer@2400000 {
973 compatible = "ti,am654-timer";
974 reg = <0x00 0x2400000 0x00 0x400>;
975 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
976 clocks = <&k3_clks 49 1>;
978 assigned-clocks = <&k3_clks 49 1>;
979 assigned-clock-parents = <&k3_clks 49 2>;
980 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
984 main_timer1: timer@2410000 {
985 compatible = "ti,am654-timer";
986 reg = <0x00 0x2410000 0x00 0x400>;
987 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
988 clocks = <&k3_clks 50 1>;
990 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>;
991 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>;
992 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
996 main_timer2: timer@2420000 {
997 compatible = "ti,am654-timer";
998 reg = <0x00 0x2420000 0x00 0x400>;
999 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1000 clocks = <&k3_clks 51 1>;
1001 clock-names = "fck";
1002 assigned-clocks = <&k3_clks 51 1>;
1003 assigned-clock-parents = <&k3_clks 51 2>;
1004 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
1008 main_timer3: timer@2430000 {
1009 compatible = "ti,am654-timer";
1010 reg = <0x00 0x2430000 0x00 0x400>;
1011 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1012 clocks = <&k3_clks 52 1>;
1013 clock-names = "fck";
1014 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>;
1015 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>;
1016 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
1020 main_timer4: timer@2440000 {
1021 compatible = "ti,am654-timer";
1022 reg = <0x00 0x2440000 0x00 0x400>;
1023 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1024 clocks = <&k3_clks 53 1>;
1025 clock-names = "fck";
1026 assigned-clocks = <&k3_clks 53 1>;
1027 assigned-clock-parents = <&k3_clks 53 2>;
1028 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
1032 main_timer5: timer@2450000 {
1033 compatible = "ti,am654-timer";
1034 reg = <0x00 0x2450000 0x00 0x400>;
1035 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1036 clocks = <&k3_clks 54 1>;
1037 clock-names = "fck";
1038 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>;
1039 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>;
1040 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1044 main_timer6: timer@2460000 {
1045 compatible = "ti,am654-timer";
1046 reg = <0x00 0x2460000 0x00 0x400>;
1047 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
1048 clocks = <&k3_clks 55 1>;
1049 clock-names = "fck";
1050 assigned-clocks = <&k3_clks 55 1>;
1051 assigned-clock-parents = <&k3_clks 55 2>;
1052 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
1056 main_timer7: timer@2470000 {
1057 compatible = "ti,am654-timer";
1058 reg = <0x00 0x2470000 0x00 0x400>;
1059 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1060 clocks = <&k3_clks 57 1>;
1061 clock-names = "fck";
1062 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>;
1063 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>;
1064 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
1068 main_timer8: timer@2480000 {
1069 compatible = "ti,am654-timer";
1070 reg = <0x00 0x2480000 0x00 0x400>;
1071 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
1072 clocks = <&k3_clks 58 1>;
1073 clock-names = "fck";
1074 assigned-clocks = <&k3_clks 58 1>;
1075 assigned-clock-parents = <&k3_clks 58 2>;
1076 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
1080 main_timer9: timer@2490000 {
1081 compatible = "ti,am654-timer";
1082 reg = <0x00 0x2490000 0x00 0x400>;
1083 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
1084 clocks = <&k3_clks 59 1>;
1085 clock-names = "fck";
1086 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>;
1087 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>;
1088 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
1092 main_timer10: timer@24a0000 {
1093 compatible = "ti,am654-timer";
1094 reg = <0x00 0x24a0000 0x00 0x400>;
1095 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
1096 clocks = <&k3_clks 60 1>;
1097 clock-names = "fck";
1098 assigned-clocks = <&k3_clks 60 1>;
1099 assigned-clock-parents = <&k3_clks 60 2>;
1100 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
1104 main_timer11: timer@24b0000 {
1105 compatible = "ti,am654-timer";
1106 reg = <0x00 0x24b0000 0x00 0x400>;
1107 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
1108 clocks = <&k3_clks 62 1>;
1109 clock-names = "fck";
1110 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>;
1111 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>;
1112 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1116 main_timer12: timer@24c0000 {
1117 compatible = "ti,am654-timer";
1118 reg = <0x00 0x24c0000 0x00 0x400>;
1119 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
1120 clocks = <&k3_clks 63 1>;
1121 clock-names = "fck";
1122 assigned-clocks = <&k3_clks 63 1>;
1123 assigned-clock-parents = <&k3_clks 63 2>;
1124 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1128 main_timer13: timer@24d0000 {
1129 compatible = "ti,am654-timer";
1130 reg = <0x00 0x24d0000 0x00 0x400>;
1131 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
1132 clocks = <&k3_clks 64 1>;
1133 clock-names = "fck";
1134 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>;
1135 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>;
1136 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1140 main_timer14: timer@24e0000 {
1141 compatible = "ti,am654-timer";
1142 reg = <0x00 0x24e0000 0x00 0x400>;
1143 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1144 clocks = <&k3_clks 65 1>;
1145 clock-names = "fck";
1146 assigned-clocks = <&k3_clks 65 1>;
1147 assigned-clock-parents = <&k3_clks 65 2>;
1148 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
1152 main_timer15: timer@24f0000 {
1153 compatible = "ti,am654-timer";
1154 reg = <0x00 0x24f0000 0x00 0x400>;
1155 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1156 clocks = <&k3_clks 66 1>;
1157 clock-names = "fck";
1158 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>;
1159 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>;
1160 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
1164 main_timer16: timer@2500000 {
1165 compatible = "ti,am654-timer";
1166 reg = <0x00 0x2500000 0x00 0x400>;
1167 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
1168 clocks = <&k3_clks 67 1>;
1169 clock-names = "fck";
1170 assigned-clocks = <&k3_clks 67 1>;
1171 assigned-clock-parents = <&k3_clks 67 2>;
1172 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1176 main_timer17: timer@2510000 {
1177 compatible = "ti,am654-timer";
1178 reg = <0x00 0x2510000 0x00 0x400>;
1179 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1180 clocks = <&k3_clks 68 1>;
1181 clock-names = "fck";
1182 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>;
1183 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>;
1184 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
1188 main_timer18: timer@2520000 {
1189 compatible = "ti,am654-timer";
1190 reg = <0x00 0x2520000 0x00 0x400>;
1191 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1192 clocks = <&k3_clks 69 1>;
1193 clock-names = "fck";
1194 assigned-clocks = <&k3_clks 69 1>;
1195 assigned-clock-parents = <&k3_clks 69 2>;
1196 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
1200 main_timer19: timer@2530000 {
1201 compatible = "ti,am654-timer";
1202 reg = <0x00 0x2530000 0x00 0x400>;
1203 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1204 clocks = <&k3_clks 70 1>;
1205 clock-names = "fck";
1206 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>;
1207 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>;
1208 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
1212 main_uart0: serial@2800000 {
1213 compatible = "ti,j721e-uart", "ti,am654-uart";
1214 reg = <0x00 0x02800000 0x00 0x100>;
1215 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
1216 clock-frequency = <48000000>;
1217 current-speed = <115200>;
1218 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
1219 clocks = <&k3_clks 146 0>;
1220 clock-names = "fclk";
1221 status = "disabled";
1224 main_uart1: serial@2810000 {
1225 compatible = "ti,j721e-uart", "ti,am654-uart";
1226 reg = <0x00 0x02810000 0x00 0x100>;
1227 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
1228 clock-frequency = <48000000>;
1229 current-speed = <115200>;
1230 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
1231 clocks = <&k3_clks 278 0>;
1232 clock-names = "fclk";
1233 status = "disabled";
1236 main_uart2: serial@2820000 {
1237 compatible = "ti,j721e-uart", "ti,am654-uart";
1238 reg = <0x00 0x02820000 0x00 0x100>;
1239 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
1240 clock-frequency = <48000000>;
1241 current-speed = <115200>;
1242 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
1243 clocks = <&k3_clks 279 0>;
1244 clock-names = "fclk";
1245 status = "disabled";
1248 main_uart3: serial@2830000 {
1249 compatible = "ti,j721e-uart", "ti,am654-uart";
1250 reg = <0x00 0x02830000 0x00 0x100>;
1251 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
1252 clock-frequency = <48000000>;
1253 current-speed = <115200>;
1254 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
1255 clocks = <&k3_clks 280 0>;
1256 clock-names = "fclk";
1257 status = "disabled";
1260 main_uart4: serial@2840000 {
1261 compatible = "ti,j721e-uart", "ti,am654-uart";
1262 reg = <0x00 0x02840000 0x00 0x100>;
1263 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
1264 clock-frequency = <48000000>;
1265 current-speed = <115200>;
1266 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
1267 clocks = <&k3_clks 281 0>;
1268 clock-names = "fclk";
1269 status = "disabled";
1272 main_uart5: serial@2850000 {
1273 compatible = "ti,j721e-uart", "ti,am654-uart";
1274 reg = <0x00 0x02850000 0x00 0x100>;
1275 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
1276 clock-frequency = <48000000>;
1277 current-speed = <115200>;
1278 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
1279 clocks = <&k3_clks 282 0>;
1280 clock-names = "fclk";
1281 status = "disabled";
1284 main_uart6: serial@2860000 {
1285 compatible = "ti,j721e-uart", "ti,am654-uart";
1286 reg = <0x00 0x02860000 0x00 0x100>;
1287 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
1288 clock-frequency = <48000000>;
1289 current-speed = <115200>;
1290 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
1291 clocks = <&k3_clks 283 0>;
1292 clock-names = "fclk";
1293 status = "disabled";
1296 main_uart7: serial@2870000 {
1297 compatible = "ti,j721e-uart", "ti,am654-uart";
1298 reg = <0x00 0x02870000 0x00 0x100>;
1299 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1300 clock-frequency = <48000000>;
1301 current-speed = <115200>;
1302 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
1303 clocks = <&k3_clks 284 0>;
1304 clock-names = "fclk";
1305 status = "disabled";
1308 main_uart8: serial@2880000 {
1309 compatible = "ti,j721e-uart", "ti,am654-uart";
1310 reg = <0x00 0x02880000 0x00 0x100>;
1311 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
1312 clock-frequency = <48000000>;
1313 current-speed = <115200>;
1314 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
1315 clocks = <&k3_clks 285 0>;
1316 clock-names = "fclk";
1317 status = "disabled";
1320 main_uart9: serial@2890000 {
1321 compatible = "ti,j721e-uart", "ti,am654-uart";
1322 reg = <0x00 0x02890000 0x00 0x100>;
1323 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
1324 clock-frequency = <48000000>;
1325 current-speed = <115200>;
1326 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
1327 clocks = <&k3_clks 286 0>;
1328 clock-names = "fclk";
1329 status = "disabled";
1332 main_gpio0: gpio@600000 {
1333 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1334 reg = <0x0 0x00600000 0x0 0x100>;
1337 interrupt-parent = <&main_gpio_intr>;
1338 interrupts = <256>, <257>, <258>, <259>,
1339 <260>, <261>, <262>, <263>;
1340 interrupt-controller;
1341 #interrupt-cells = <2>;
1343 ti,davinci-gpio-unbanked = <0>;
1344 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
1345 clocks = <&k3_clks 105 0>;
1346 clock-names = "gpio";
1347 status = "disabled";
1350 main_gpio1: gpio@601000 {
1351 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1352 reg = <0x0 0x00601000 0x0 0x100>;
1355 interrupt-parent = <&main_gpio_intr>;
1356 interrupts = <288>, <289>, <290>;
1357 interrupt-controller;
1358 #interrupt-cells = <2>;
1360 ti,davinci-gpio-unbanked = <0>;
1361 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
1362 clocks = <&k3_clks 106 0>;
1363 clock-names = "gpio";
1364 status = "disabled";
1367 main_gpio2: gpio@610000 {
1368 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1369 reg = <0x0 0x00610000 0x0 0x100>;
1372 interrupt-parent = <&main_gpio_intr>;
1373 interrupts = <264>, <265>, <266>, <267>,
1374 <268>, <269>, <270>, <271>;
1375 interrupt-controller;
1376 #interrupt-cells = <2>;
1378 ti,davinci-gpio-unbanked = <0>;
1379 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
1380 clocks = <&k3_clks 107 0>;
1381 clock-names = "gpio";
1382 status = "disabled";
1385 main_gpio3: gpio@611000 {
1386 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1387 reg = <0x0 0x00611000 0x0 0x100>;
1390 interrupt-parent = <&main_gpio_intr>;
1391 interrupts = <292>, <293>, <294>;
1392 interrupt-controller;
1393 #interrupt-cells = <2>;
1395 ti,davinci-gpio-unbanked = <0>;
1396 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
1397 clocks = <&k3_clks 108 0>;
1398 clock-names = "gpio";
1399 status = "disabled";
1402 main_gpio4: gpio@620000 {
1403 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1404 reg = <0x0 0x00620000 0x0 0x100>;
1407 interrupt-parent = <&main_gpio_intr>;
1408 interrupts = <272>, <273>, <274>, <275>,
1409 <276>, <277>, <278>, <279>;
1410 interrupt-controller;
1411 #interrupt-cells = <2>;
1413 ti,davinci-gpio-unbanked = <0>;
1414 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
1415 clocks = <&k3_clks 109 0>;
1416 clock-names = "gpio";
1417 status = "disabled";
1420 main_gpio5: gpio@621000 {
1421 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1422 reg = <0x0 0x00621000 0x0 0x100>;
1425 interrupt-parent = <&main_gpio_intr>;
1426 interrupts = <296>, <297>, <298>;
1427 interrupt-controller;
1428 #interrupt-cells = <2>;
1430 ti,davinci-gpio-unbanked = <0>;
1431 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
1432 clocks = <&k3_clks 110 0>;
1433 clock-names = "gpio";
1434 status = "disabled";
1437 main_gpio6: gpio@630000 {
1438 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1439 reg = <0x0 0x00630000 0x0 0x100>;
1442 interrupt-parent = <&main_gpio_intr>;
1443 interrupts = <280>, <281>, <282>, <283>,
1444 <284>, <285>, <286>, <287>;
1445 interrupt-controller;
1446 #interrupt-cells = <2>;
1448 ti,davinci-gpio-unbanked = <0>;
1449 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
1450 clocks = <&k3_clks 111 0>;
1451 clock-names = "gpio";
1452 status = "disabled";
1455 main_gpio7: gpio@631000 {
1456 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1457 reg = <0x0 0x00631000 0x0 0x100>;
1460 interrupt-parent = <&main_gpio_intr>;
1461 interrupts = <300>, <301>, <302>;
1462 interrupt-controller;
1463 #interrupt-cells = <2>;
1465 ti,davinci-gpio-unbanked = <0>;
1466 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
1467 clocks = <&k3_clks 112 0>;
1468 clock-names = "gpio";
1469 status = "disabled";
1472 main_sdhci0: mmc@4f80000 {
1473 compatible = "ti,j721e-sdhci-8bit";
1474 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
1475 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1476 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
1477 clock-names = "clk_ahb", "clk_xin";
1478 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
1479 assigned-clocks = <&k3_clks 91 1>;
1480 assigned-clock-parents = <&k3_clks 91 2>;
1484 ti,otap-del-sel-legacy = <0x0>;
1485 ti,otap-del-sel-mmc-hs = <0x0>;
1486 ti,otap-del-sel-ddr52 = <0x5>;
1487 ti,otap-del-sel-hs200 = <0x6>;
1488 ti,otap-del-sel-hs400 = <0x0>;
1489 ti,itap-del-sel-legacy = <0x10>;
1490 ti,itap-del-sel-mmc-hs = <0xa>;
1491 ti,itap-del-sel-ddr52 = <0x3>;
1494 status = "disabled";
1497 main_sdhci1: mmc@4fb0000 {
1498 compatible = "ti,j721e-sdhci-4bit";
1499 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
1500 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1501 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
1502 clock-names = "clk_ahb", "clk_xin";
1503 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
1504 assigned-clocks = <&k3_clks 92 0>;
1505 assigned-clock-parents = <&k3_clks 92 1>;
1506 ti,otap-del-sel-legacy = <0x0>;
1507 ti,otap-del-sel-sd-hs = <0x0>;
1508 ti,otap-del-sel-sdr12 = <0xf>;
1509 ti,otap-del-sel-sdr25 = <0xf>;
1510 ti,otap-del-sel-sdr50 = <0xc>;
1511 ti,otap-del-sel-ddr50 = <0xc>;
1512 ti,otap-del-sel-sdr104 = <0x5>;
1513 ti,itap-del-sel-legacy = <0x0>;
1514 ti,itap-del-sel-sd-hs = <0x0>;
1515 ti,itap-del-sel-sdr12 = <0x0>;
1516 ti,itap-del-sel-sdr25 = <0x0>;
1517 ti,itap-del-sel-ddr50 = <0x2>;
1519 ti,clkbuf-sel = <0x7>;
1521 sdhci-caps-mask = <0x2 0x0>;
1522 status = "disabled";
1525 main_sdhci2: mmc@4f98000 {
1526 compatible = "ti,j721e-sdhci-4bit";
1527 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
1528 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1529 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
1530 clock-names = "clk_ahb", "clk_xin";
1531 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
1532 assigned-clocks = <&k3_clks 93 0>;
1533 assigned-clock-parents = <&k3_clks 93 1>;
1534 ti,otap-del-sel-legacy = <0x0>;
1535 ti,otap-del-sel-sd-hs = <0x0>;
1536 ti,otap-del-sel-sdr12 = <0xf>;
1537 ti,otap-del-sel-sdr25 = <0xf>;
1538 ti,otap-del-sel-sdr50 = <0xc>;
1539 ti,otap-del-sel-ddr50 = <0xc>;
1540 ti,otap-del-sel-sdr104 = <0x5>;
1541 ti,itap-del-sel-legacy = <0x0>;
1542 ti,itap-del-sel-sd-hs = <0x0>;
1543 ti,itap-del-sel-sdr12 = <0x0>;
1544 ti,itap-del-sel-sdr25 = <0x0>;
1545 ti,itap-del-sel-ddr50 = <0x2>;
1547 ti,clkbuf-sel = <0x7>;
1549 sdhci-caps-mask = <0x2 0x0>;
1550 status = "disabled";
1553 usbss0: cdns-usb@4104000 {
1554 compatible = "ti,j721e-usb";
1555 reg = <0x00 0x4104000 0x00 0x100>;
1557 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1558 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
1559 clock-names = "ref", "lpm";
1560 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
1561 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
1562 #address-cells = <2>;
1567 compatible = "cdns,usb3";
1568 reg = <0x00 0x6000000 0x00 0x10000>,
1569 <0x00 0x6010000 0x00 0x10000>,
1570 <0x00 0x6020000 0x00 0x10000>;
1571 reg-names = "otg", "xhci", "dev";
1572 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1573 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
1574 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1575 interrupt-names = "host",
1578 maximum-speed = "super-speed";
1583 usbss1: cdns-usb@4114000 {
1584 compatible = "ti,j721e-usb";
1585 reg = <0x00 0x4114000 0x00 0x100>;
1587 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
1588 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
1589 clock-names = "ref", "lpm";
1590 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
1591 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
1592 #address-cells = <2>;
1597 compatible = "cdns,usb3";
1598 reg = <0x00 0x6400000 0x00 0x10000>,
1599 <0x00 0x6410000 0x00 0x10000>,
1600 <0x00 0x6420000 0x00 0x10000>;
1601 reg-names = "otg", "xhci", "dev";
1602 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1603 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
1604 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1605 interrupt-names = "host",
1608 maximum-speed = "super-speed";
1613 main_i2c0: i2c@2000000 {
1614 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1615 reg = <0x0 0x2000000 0x0 0x100>;
1616 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
1617 #address-cells = <1>;
1619 clock-names = "fck";
1620 clocks = <&k3_clks 187 0>;
1621 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
1622 status = "disabled";
1625 main_i2c1: i2c@2010000 {
1626 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1627 reg = <0x0 0x2010000 0x0 0x100>;
1628 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
1629 #address-cells = <1>;
1631 clock-names = "fck";
1632 clocks = <&k3_clks 188 0>;
1633 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1634 status = "disabled";
1637 main_i2c2: i2c@2020000 {
1638 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1639 reg = <0x0 0x2020000 0x0 0x100>;
1640 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1641 #address-cells = <1>;
1643 clock-names = "fck";
1644 clocks = <&k3_clks 189 0>;
1645 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1646 status = "disabled";
1649 main_i2c3: i2c@2030000 {
1650 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1651 reg = <0x0 0x2030000 0x0 0x100>;
1652 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
1653 #address-cells = <1>;
1655 clock-names = "fck";
1656 clocks = <&k3_clks 190 0>;
1657 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1658 status = "disabled";
1661 main_i2c4: i2c@2040000 {
1662 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1663 reg = <0x0 0x2040000 0x0 0x100>;
1664 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
1665 #address-cells = <1>;
1667 clock-names = "fck";
1668 clocks = <&k3_clks 191 0>;
1669 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1670 status = "disabled";
1673 main_i2c5: i2c@2050000 {
1674 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1675 reg = <0x0 0x2050000 0x0 0x100>;
1676 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1677 #address-cells = <1>;
1679 clock-names = "fck";
1680 clocks = <&k3_clks 192 0>;
1681 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1682 status = "disabled";
1685 main_i2c6: i2c@2060000 {
1686 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1687 reg = <0x0 0x2060000 0x0 0x100>;
1688 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1689 #address-cells = <1>;
1691 clock-names = "fck";
1692 clocks = <&k3_clks 193 0>;
1693 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1694 status = "disabled";
1697 ufs_wrapper: ufs-wrapper@4e80000 {
1698 compatible = "ti,j721e-ufs";
1699 reg = <0x0 0x4e80000 0x0 0x100>;
1700 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1701 clocks = <&k3_clks 277 1>;
1702 assigned-clocks = <&k3_clks 277 1>;
1703 assigned-clock-parents = <&k3_clks 277 4>;
1705 #address-cells = <2>;
1709 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
1710 reg = <0x0 0x4e84000 0x0 0x10000>;
1711 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1712 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
1713 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
1714 clock-names = "core_clk", "phy_clk", "ref_clk";
1719 mhdp: dp-bridge@a000000 {
1720 compatible = "ti,j721e-mhdp8546";
1722 * Note: we do not map DPTX PHY area, as that is handled by
1725 reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
1726 <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */
1727 reg-names = "mhdptx", "j721e-intg";
1729 clocks = <&k3_clks 151 36>;
1731 interrupt-parent = <&gic500>;
1732 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
1734 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
1737 #address-cells = <1>;
1751 compatible = "ti,j721e-dss";
1753 <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1754 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1755 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1756 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1758 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1759 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1760 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1761 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1763 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1764 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1765 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1766 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1768 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1769 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1770 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1771 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1772 <0x00 0x04af0000 0x00 0x10000>; /* wb */
1774 reg-names = "common_m", "common_s0",
1775 "common_s1", "common_s2",
1776 "vidl1", "vidl2","vid1","vid2",
1777 "ovr1", "ovr2", "ovr3", "ovr4",
1778 "vp1", "vp2", "vp3", "vp4",
1781 clocks = <&k3_clks 152 0>,
1786 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1788 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1790 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
1791 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
1792 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
1793 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1794 interrupt-names = "common_m",
1803 mcasp0: mcasp@2b00000 {
1804 compatible = "ti,am33xx-mcasp-audio";
1805 reg = <0x0 0x02b00000 0x0 0x2000>,
1806 <0x0 0x02b08000 0x0 0x1000>;
1807 reg-names = "mpu","dat";
1808 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
1809 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
1810 interrupt-names = "tx", "rx";
1812 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
1813 dma-names = "tx", "rx";
1815 clocks = <&k3_clks 174 1>;
1816 clock-names = "fck";
1817 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
1818 status = "disabled";
1821 mcasp1: mcasp@2b10000 {
1822 compatible = "ti,am33xx-mcasp-audio";
1823 reg = <0x0 0x02b10000 0x0 0x2000>,
1824 <0x0 0x02b18000 0x0 0x1000>;
1825 reg-names = "mpu","dat";
1826 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
1827 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
1828 interrupt-names = "tx", "rx";
1830 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
1831 dma-names = "tx", "rx";
1833 clocks = <&k3_clks 175 1>;
1834 clock-names = "fck";
1835 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
1836 status = "disabled";
1839 mcasp2: mcasp@2b20000 {
1840 compatible = "ti,am33xx-mcasp-audio";
1841 reg = <0x0 0x02b20000 0x0 0x2000>,
1842 <0x0 0x02b28000 0x0 0x1000>;
1843 reg-names = "mpu","dat";
1844 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
1845 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
1846 interrupt-names = "tx", "rx";
1848 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
1849 dma-names = "tx", "rx";
1851 clocks = <&k3_clks 176 1>;
1852 clock-names = "fck";
1853 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
1854 status = "disabled";
1857 mcasp3: mcasp@2b30000 {
1858 compatible = "ti,am33xx-mcasp-audio";
1859 reg = <0x0 0x02b30000 0x0 0x2000>,
1860 <0x0 0x02b38000 0x0 0x1000>;
1861 reg-names = "mpu","dat";
1862 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>,
1863 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
1864 interrupt-names = "tx", "rx";
1866 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
1867 dma-names = "tx", "rx";
1869 clocks = <&k3_clks 177 1>;
1870 clock-names = "fck";
1871 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
1872 status = "disabled";
1875 mcasp4: mcasp@2b40000 {
1876 compatible = "ti,am33xx-mcasp-audio";
1877 reg = <0x0 0x02b40000 0x0 0x2000>,
1878 <0x0 0x02b48000 0x0 0x1000>;
1879 reg-names = "mpu","dat";
1880 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>,
1881 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
1882 interrupt-names = "tx", "rx";
1884 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
1885 dma-names = "tx", "rx";
1887 clocks = <&k3_clks 178 1>;
1888 clock-names = "fck";
1889 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
1890 status = "disabled";
1893 mcasp5: mcasp@2b50000 {
1894 compatible = "ti,am33xx-mcasp-audio";
1895 reg = <0x0 0x02b50000 0x0 0x2000>,
1896 <0x0 0x02b58000 0x0 0x1000>;
1897 reg-names = "mpu","dat";
1898 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>,
1899 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
1900 interrupt-names = "tx", "rx";
1902 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
1903 dma-names = "tx", "rx";
1905 clocks = <&k3_clks 179 1>;
1906 clock-names = "fck";
1907 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
1908 status = "disabled";
1911 mcasp6: mcasp@2b60000 {
1912 compatible = "ti,am33xx-mcasp-audio";
1913 reg = <0x0 0x02b60000 0x0 0x2000>,
1914 <0x0 0x02b68000 0x0 0x1000>;
1915 reg-names = "mpu","dat";
1916 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>,
1917 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>;
1918 interrupt-names = "tx", "rx";
1920 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
1921 dma-names = "tx", "rx";
1923 clocks = <&k3_clks 180 1>;
1924 clock-names = "fck";
1925 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
1926 status = "disabled";
1929 mcasp7: mcasp@2b70000 {
1930 compatible = "ti,am33xx-mcasp-audio";
1931 reg = <0x0 0x02b70000 0x0 0x2000>,
1932 <0x0 0x02b78000 0x0 0x1000>;
1933 reg-names = "mpu","dat";
1934 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>,
1935 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
1936 interrupt-names = "tx", "rx";
1938 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
1939 dma-names = "tx", "rx";
1941 clocks = <&k3_clks 181 1>;
1942 clock-names = "fck";
1943 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
1944 status = "disabled";
1947 mcasp8: mcasp@2b80000 {
1948 compatible = "ti,am33xx-mcasp-audio";
1949 reg = <0x0 0x02b80000 0x0 0x2000>,
1950 <0x0 0x02b88000 0x0 0x1000>;
1951 reg-names = "mpu","dat";
1952 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>,
1953 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
1954 interrupt-names = "tx", "rx";
1956 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
1957 dma-names = "tx", "rx";
1959 clocks = <&k3_clks 182 1>;
1960 clock-names = "fck";
1961 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1962 status = "disabled";
1965 mcasp9: mcasp@2b90000 {
1966 compatible = "ti,am33xx-mcasp-audio";
1967 reg = <0x0 0x02b90000 0x0 0x2000>,
1968 <0x0 0x02b98000 0x0 0x1000>;
1969 reg-names = "mpu","dat";
1970 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>,
1971 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>;
1972 interrupt-names = "tx", "rx";
1974 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
1975 dma-names = "tx", "rx";
1977 clocks = <&k3_clks 183 1>;
1978 clock-names = "fck";
1979 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1980 status = "disabled";
1983 mcasp10: mcasp@2ba0000 {
1984 compatible = "ti,am33xx-mcasp-audio";
1985 reg = <0x0 0x02ba0000 0x0 0x2000>,
1986 <0x0 0x02ba8000 0x0 0x1000>;
1987 reg-names = "mpu","dat";
1988 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>,
1989 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
1990 interrupt-names = "tx", "rx";
1992 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
1993 dma-names = "tx", "rx";
1995 clocks = <&k3_clks 184 1>;
1996 clock-names = "fck";
1997 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
1998 status = "disabled";
2001 mcasp11: mcasp@2bb0000 {
2002 compatible = "ti,am33xx-mcasp-audio";
2003 reg = <0x0 0x02bb0000 0x0 0x2000>,
2004 <0x0 0x02bb8000 0x0 0x1000>;
2005 reg-names = "mpu","dat";
2006 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>,
2007 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
2008 interrupt-names = "tx", "rx";
2010 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
2011 dma-names = "tx", "rx";
2013 clocks = <&k3_clks 185 1>;
2014 clock-names = "fck";
2015 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
2016 status = "disabled";
2019 watchdog0: watchdog@2200000 {
2020 compatible = "ti,j7-rti-wdt";
2021 reg = <0x0 0x2200000 0x0 0x100>;
2022 clocks = <&k3_clks 252 1>;
2023 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
2024 assigned-clocks = <&k3_clks 252 1>;
2025 assigned-clock-parents = <&k3_clks 252 5>;
2028 watchdog1: watchdog@2210000 {
2029 compatible = "ti,j7-rti-wdt";
2030 reg = <0x0 0x2210000 0x0 0x100>;
2031 clocks = <&k3_clks 253 1>;
2032 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
2033 assigned-clocks = <&k3_clks 253 1>;
2034 assigned-clock-parents = <&k3_clks 253 5>;
2037 main_r5fss0: r5fss@5c00000 {
2038 compatible = "ti,j721e-r5fss";
2039 ti,cluster-mode = <1>;
2040 #address-cells = <1>;
2042 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
2043 <0x5d00000 0x00 0x5d00000 0x20000>;
2044 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
2046 main_r5fss0_core0: r5f@5c00000 {
2047 compatible = "ti,j721e-r5f";
2048 reg = <0x5c00000 0x00008000>,
2049 <0x5c10000 0x00008000>;
2050 reg-names = "atcm", "btcm";
2052 ti,sci-dev-id = <245>;
2053 ti,sci-proc-ids = <0x06 0xff>;
2054 resets = <&k3_reset 245 1>;
2055 firmware-name = "j7-main-r5f0_0-fw";
2056 ti,atcm-enable = <1>;
2057 ti,btcm-enable = <1>;
2061 main_r5fss0_core1: r5f@5d00000 {
2062 compatible = "ti,j721e-r5f";
2063 reg = <0x5d00000 0x00008000>,
2064 <0x5d10000 0x00008000>;
2065 reg-names = "atcm", "btcm";
2067 ti,sci-dev-id = <246>;
2068 ti,sci-proc-ids = <0x07 0xff>;
2069 resets = <&k3_reset 246 1>;
2070 firmware-name = "j7-main-r5f0_1-fw";
2071 ti,atcm-enable = <1>;
2072 ti,btcm-enable = <1>;
2077 main_r5fss1: r5fss@5e00000 {
2078 compatible = "ti,j721e-r5fss";
2079 ti,cluster-mode = <1>;
2080 #address-cells = <1>;
2082 ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
2083 <0x5f00000 0x00 0x5f00000 0x20000>;
2084 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
2086 main_r5fss1_core0: r5f@5e00000 {
2087 compatible = "ti,j721e-r5f";
2088 reg = <0x5e00000 0x00008000>,
2089 <0x5e10000 0x00008000>;
2090 reg-names = "atcm", "btcm";
2092 ti,sci-dev-id = <247>;
2093 ti,sci-proc-ids = <0x08 0xff>;
2094 resets = <&k3_reset 247 1>;
2095 firmware-name = "j7-main-r5f1_0-fw";
2096 ti,atcm-enable = <1>;
2097 ti,btcm-enable = <1>;
2101 main_r5fss1_core1: r5f@5f00000 {
2102 compatible = "ti,j721e-r5f";
2103 reg = <0x5f00000 0x00008000>,
2104 <0x5f10000 0x00008000>;
2105 reg-names = "atcm", "btcm";
2107 ti,sci-dev-id = <248>;
2108 ti,sci-proc-ids = <0x09 0xff>;
2109 resets = <&k3_reset 248 1>;
2110 firmware-name = "j7-main-r5f1_1-fw";
2111 ti,atcm-enable = <1>;
2112 ti,btcm-enable = <1>;
2117 c66_0: dsp@4d80800000 {
2118 compatible = "ti,j721e-c66-dsp";
2119 reg = <0x4d 0x80800000 0x00 0x00048000>,
2120 <0x4d 0x80e00000 0x00 0x00008000>,
2121 <0x4d 0x80f00000 0x00 0x00008000>;
2122 reg-names = "l2sram", "l1pram", "l1dram";
2124 ti,sci-dev-id = <142>;
2125 ti,sci-proc-ids = <0x03 0xff>;
2126 resets = <&k3_reset 142 1>;
2127 firmware-name = "j7-c66_0-fw";
2128 status = "disabled";
2131 c66_1: dsp@4d81800000 {
2132 compatible = "ti,j721e-c66-dsp";
2133 reg = <0x4d 0x81800000 0x00 0x00048000>,
2134 <0x4d 0x81e00000 0x00 0x00008000>,
2135 <0x4d 0x81f00000 0x00 0x00008000>;
2136 reg-names = "l2sram", "l1pram", "l1dram";
2138 ti,sci-dev-id = <143>;
2139 ti,sci-proc-ids = <0x04 0xff>;
2140 resets = <&k3_reset 143 1>;
2141 firmware-name = "j7-c66_1-fw";
2142 status = "disabled";
2145 c71_0: dsp@64800000 {
2146 compatible = "ti,j721e-c71-dsp";
2147 reg = <0x00 0x64800000 0x00 0x00080000>,
2148 <0x00 0x64e00000 0x00 0x0000c000>;
2149 reg-names = "l2sram", "l1dram";
2151 ti,sci-dev-id = <15>;
2152 ti,sci-proc-ids = <0x30 0xff>;
2153 resets = <&k3_reset 15 1>;
2154 firmware-name = "j7-c71_0-fw";
2155 status = "disabled";
2158 icssg0: icssg@b000000 {
2159 compatible = "ti,j721e-icssg";
2160 reg = <0x00 0xb000000 0x00 0x80000>;
2161 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
2162 #address-cells = <1>;
2164 ranges = <0x0 0x00 0x0b000000 0x100000>;
2166 icssg0_mem: memories@0 {
2170 reg-names = "dram0", "dram1",
2174 icssg0_cfg: cfg@26000 {
2175 compatible = "ti,pruss-cfg", "syscon";
2176 reg = <0x26000 0x200>;
2177 #address-cells = <1>;
2179 ranges = <0x0 0x26000 0x2000>;
2182 #address-cells = <1>;
2185 icssg0_coreclk_mux: coreclk-mux@3c {
2188 clocks = <&k3_clks 119 24>, /* icssg0_core_clk */
2189 <&k3_clks 119 1>; /* icssg0_iclk */
2190 assigned-clocks = <&icssg0_coreclk_mux>;
2191 assigned-clock-parents = <&k3_clks 119 1>;
2194 icssg0_iepclk_mux: iepclk-mux@30 {
2197 clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */
2198 <&icssg0_coreclk_mux>; /* core_clk */
2199 assigned-clocks = <&icssg0_iepclk_mux>;
2200 assigned-clock-parents = <&icssg0_coreclk_mux>;
2205 icssg0_mii_rt: mii-rt@32000 {
2206 compatible = "ti,pruss-mii", "syscon";
2207 reg = <0x32000 0x100>;
2210 icssg0_mii_g_rt: mii-g-rt@33000 {
2211 compatible = "ti,pruss-mii-g", "syscon";
2212 reg = <0x33000 0x1000>;
2215 icssg0_intc: interrupt-controller@20000 {
2216 compatible = "ti,icssg-intc";
2217 reg = <0x20000 0x2000>;
2218 interrupt-controller;
2219 #interrupt-cells = <3>;
2220 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
2221 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
2222 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2223 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
2224 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
2225 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
2226 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
2227 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
2228 interrupt-names = "host_intr0", "host_intr1",
2229 "host_intr2", "host_intr3",
2230 "host_intr4", "host_intr5",
2231 "host_intr6", "host_intr7";
2235 compatible = "ti,j721e-pru";
2236 reg = <0x34000 0x3000>,
2239 reg-names = "iram", "control", "debug";
2240 firmware-name = "j7-pru0_0-fw";
2244 compatible = "ti,j721e-rtu";
2245 reg = <0x4000 0x2000>,
2248 reg-names = "iram", "control", "debug";
2249 firmware-name = "j7-rtu0_0-fw";
2252 tx_pru0_0: txpru@a000 {
2253 compatible = "ti,j721e-tx-pru";
2254 reg = <0xa000 0x1800>,
2257 reg-names = "iram", "control", "debug";
2258 firmware-name = "j7-txpru0_0-fw";
2262 compatible = "ti,j721e-pru";
2263 reg = <0x38000 0x3000>,
2266 reg-names = "iram", "control", "debug";
2267 firmware-name = "j7-pru0_1-fw";
2271 compatible = "ti,j721e-rtu";
2272 reg = <0x6000 0x2000>,
2275 reg-names = "iram", "control", "debug";
2276 firmware-name = "j7-rtu0_1-fw";
2279 tx_pru0_1: txpru@c000 {
2280 compatible = "ti,j721e-tx-pru";
2281 reg = <0xc000 0x1800>,
2284 reg-names = "iram", "control", "debug";
2285 firmware-name = "j7-txpru0_1-fw";
2288 icssg0_mdio: mdio@32400 {
2289 compatible = "ti,davinci_mdio";
2290 reg = <0x32400 0x100>;
2291 clocks = <&k3_clks 119 1>;
2292 clock-names = "fck";
2293 #address-cells = <1>;
2295 bus_freq = <1000000>;
2296 status = "disabled";
2300 icssg1: icssg@b100000 {
2301 compatible = "ti,j721e-icssg";
2302 reg = <0x00 0xb100000 0x00 0x80000>;
2303 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
2304 #address-cells = <1>;
2306 ranges = <0x0 0x00 0x0b100000 0x100000>;
2308 icssg1_mem: memories@b100000 {
2312 reg-names = "dram0", "dram1",
2316 icssg1_cfg: cfg@26000 {
2317 compatible = "ti,pruss-cfg", "syscon";
2318 reg = <0x26000 0x200>;
2319 #address-cells = <1>;
2321 ranges = <0x0 0x26000 0x2000>;
2324 #address-cells = <1>;
2327 icssg1_coreclk_mux: coreclk-mux@3c {
2330 clocks = <&k3_clks 120 54>, /* icssg1_core_clk */
2331 <&k3_clks 120 4>; /* icssg1_iclk */
2332 assigned-clocks = <&icssg1_coreclk_mux>;
2333 assigned-clock-parents = <&k3_clks 120 4>;
2336 icssg1_iepclk_mux: iepclk-mux@30 {
2339 clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */
2340 <&icssg1_coreclk_mux>; /* core_clk */
2341 assigned-clocks = <&icssg1_iepclk_mux>;
2342 assigned-clock-parents = <&icssg1_coreclk_mux>;
2347 icssg1_mii_rt: mii-rt@32000 {
2348 compatible = "ti,pruss-mii", "syscon";
2349 reg = <0x32000 0x100>;
2352 icssg1_mii_g_rt: mii-g-rt@33000 {
2353 compatible = "ti,pruss-mii-g", "syscon";
2354 reg = <0x33000 0x1000>;
2357 icssg1_intc: interrupt-controller@20000 {
2358 compatible = "ti,icssg-intc";
2359 reg = <0x20000 0x2000>;
2360 interrupt-controller;
2361 #interrupt-cells = <3>;
2362 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2363 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2364 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
2365 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
2366 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
2367 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
2368 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2369 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
2370 interrupt-names = "host_intr0", "host_intr1",
2371 "host_intr2", "host_intr3",
2372 "host_intr4", "host_intr5",
2373 "host_intr6", "host_intr7";
2377 compatible = "ti,j721e-pru";
2378 reg = <0x34000 0x4000>,
2381 reg-names = "iram", "control", "debug";
2382 firmware-name = "j7-pru1_0-fw";
2386 compatible = "ti,j721e-rtu";
2387 reg = <0x4000 0x2000>,
2390 reg-names = "iram", "control", "debug";
2391 firmware-name = "j7-rtu1_0-fw";
2394 tx_pru1_0: txpru@a000 {
2395 compatible = "ti,j721e-tx-pru";
2396 reg = <0xa000 0x1800>,
2399 reg-names = "iram", "control", "debug";
2400 firmware-name = "j7-txpru1_0-fw";
2404 compatible = "ti,j721e-pru";
2405 reg = <0x38000 0x4000>,
2408 reg-names = "iram", "control", "debug";
2409 firmware-name = "j7-pru1_1-fw";
2413 compatible = "ti,j721e-rtu";
2414 reg = <0x6000 0x2000>,
2417 reg-names = "iram", "control", "debug";
2418 firmware-name = "j7-rtu1_1-fw";
2421 tx_pru1_1: txpru@c000 {
2422 compatible = "ti,j721e-tx-pru";
2423 reg = <0xc000 0x1800>,
2426 reg-names = "iram", "control", "debug";
2427 firmware-name = "j7-txpru1_1-fw";
2430 icssg1_mdio: mdio@32400 {
2431 compatible = "ti,davinci_mdio";
2432 reg = <0x32400 0x100>;
2433 clocks = <&k3_clks 120 4>;
2434 clock-names = "fck";
2435 #address-cells = <1>;
2437 bus_freq = <1000000>;
2438 status = "disabled";
2442 main_mcan0: can@2701000 {
2443 compatible = "bosch,m_can";
2444 reg = <0x00 0x02701000 0x00 0x200>,
2445 <0x00 0x02708000 0x00 0x8000>;
2446 reg-names = "m_can", "message_ram";
2447 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
2448 clocks = <&k3_clks 156 0>, <&k3_clks 156 1>;
2449 clock-names = "hclk", "cclk";
2450 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
2451 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
2452 interrupt-names = "int0", "int1";
2453 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2454 status = "disabled";
2457 main_mcan1: can@2711000 {
2458 compatible = "bosch,m_can";
2459 reg = <0x00 0x02711000 0x00 0x200>,
2460 <0x00 0x02718000 0x00 0x8000>;
2461 reg-names = "m_can", "message_ram";
2462 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
2463 clocks = <&k3_clks 158 0>, <&k3_clks 158 1>;
2464 clock-names = "hclk", "cclk";
2465 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
2466 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
2467 interrupt-names = "int0", "int1";
2468 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2469 status = "disabled";
2472 main_mcan2: can@2721000 {
2473 compatible = "bosch,m_can";
2474 reg = <0x00 0x02721000 0x00 0x200>,
2475 <0x00 0x02728000 0x00 0x8000>;
2476 reg-names = "m_can", "message_ram";
2477 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
2478 clocks = <&k3_clks 160 0>, <&k3_clks 160 1>;
2479 clock-names = "hclk", "cclk";
2480 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2481 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2482 interrupt-names = "int0", "int1";
2483 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2484 status = "disabled";
2487 main_mcan3: can@2731000 {
2488 compatible = "bosch,m_can";
2489 reg = <0x00 0x02731000 0x00 0x200>,
2490 <0x00 0x02738000 0x00 0x8000>;
2491 reg-names = "m_can", "message_ram";
2492 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
2493 clocks = <&k3_clks 161 0>, <&k3_clks 161 1>;
2494 clock-names = "hclk", "cclk";
2495 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
2496 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
2497 interrupt-names = "int0", "int1";
2498 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2499 status = "disabled";
2502 main_mcan4: can@2741000 {
2503 compatible = "bosch,m_can";
2504 reg = <0x00 0x02741000 0x00 0x200>,
2505 <0x00 0x02748000 0x00 0x8000>;
2506 reg-names = "m_can", "message_ram";
2507 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
2508 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>;
2509 clock-names = "hclk", "cclk";
2510 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2511 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
2512 interrupt-names = "int0", "int1";
2513 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2514 status = "disabled";
2517 main_mcan5: can@2751000 {
2518 compatible = "bosch,m_can";
2519 reg = <0x00 0x02751000 0x00 0x200>,
2520 <0x00 0x02758000 0x00 0x8000>;
2521 reg-names = "m_can", "message_ram";
2522 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
2523 clocks = <&k3_clks 163 0>, <&k3_clks 163 1>;
2524 clock-names = "hclk", "cclk";
2525 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
2526 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
2527 interrupt-names = "int0", "int1";
2528 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2529 status = "disabled";
2532 main_mcan6: can@2761000 {
2533 compatible = "bosch,m_can";
2534 reg = <0x00 0x02761000 0x00 0x200>,
2535 <0x00 0x02768000 0x00 0x8000>;
2536 reg-names = "m_can", "message_ram";
2537 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
2538 clocks = <&k3_clks 164 0>, <&k3_clks 164 1>;
2539 clock-names = "hclk", "cclk";
2540 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2541 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
2542 interrupt-names = "int0", "int1";
2543 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2544 status = "disabled";
2547 main_mcan7: can@2771000 {
2548 compatible = "bosch,m_can";
2549 reg = <0x00 0x02771000 0x00 0x200>,
2550 <0x00 0x02778000 0x00 0x8000>;
2551 reg-names = "m_can", "message_ram";
2552 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
2553 clocks = <&k3_clks 165 0>, <&k3_clks 165 1>;
2554 clock-names = "hclk", "cclk";
2555 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2556 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
2557 interrupt-names = "int0", "int1";
2558 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2559 status = "disabled";
2562 main_mcan8: can@2781000 {
2563 compatible = "bosch,m_can";
2564 reg = <0x00 0x02781000 0x00 0x200>,
2565 <0x00 0x02788000 0x00 0x8000>;
2566 reg-names = "m_can", "message_ram";
2567 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
2568 clocks = <&k3_clks 166 0>, <&k3_clks 166 1>;
2569 clock-names = "hclk", "cclk";
2570 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
2571 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
2572 interrupt-names = "int0", "int1";
2573 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2574 status = "disabled";
2577 main_mcan9: can@2791000 {
2578 compatible = "bosch,m_can";
2579 reg = <0x00 0x02791000 0x00 0x200>,
2580 <0x00 0x02798000 0x00 0x8000>;
2581 reg-names = "m_can", "message_ram";
2582 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
2583 clocks = <&k3_clks 167 0>, <&k3_clks 167 1>;
2584 clock-names = "hclk", "cclk";
2585 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
2586 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
2587 interrupt-names = "int0", "int1";
2588 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2589 status = "disabled";
2592 main_mcan10: can@27a1000 {
2593 compatible = "bosch,m_can";
2594 reg = <0x00 0x027a1000 0x00 0x200>,
2595 <0x00 0x027a8000 0x00 0x8000>;
2596 reg-names = "m_can", "message_ram";
2597 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
2598 clocks = <&k3_clks 168 0>, <&k3_clks 168 1>;
2599 clock-names = "hclk", "cclk";
2600 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
2601 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
2602 interrupt-names = "int0", "int1";
2603 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2604 status = "disabled";
2607 main_mcan11: can@27b1000 {
2608 compatible = "bosch,m_can";
2609 reg = <0x00 0x027b1000 0x00 0x200>,
2610 <0x00 0x027b8000 0x00 0x8000>;
2611 reg-names = "m_can", "message_ram";
2612 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>;
2613 clocks = <&k3_clks 169 0>, <&k3_clks 169 1>;
2614 clock-names = "hclk", "cclk";
2615 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
2616 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
2617 interrupt-names = "int0", "int1";
2618 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2619 status = "disabled";
2622 main_mcan12: can@27c1000 {
2623 compatible = "bosch,m_can";
2624 reg = <0x00 0x027c1000 0x00 0x200>,
2625 <0x00 0x027c8000 0x00 0x8000>;
2626 reg-names = "m_can", "message_ram";
2627 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>;
2628 clocks = <&k3_clks 170 0>, <&k3_clks 170 1>;
2629 clock-names = "hclk", "cclk";
2630 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
2631 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
2632 interrupt-names = "int0", "int1";
2633 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2634 status = "disabled";
2637 main_mcan13: can@27d1000 {
2638 compatible = "bosch,m_can";
2639 reg = <0x00 0x027d1000 0x00 0x200>,
2640 <0x00 0x027d8000 0x00 0x8000>;
2641 reg-names = "m_can", "message_ram";
2642 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>;
2643 clocks = <&k3_clks 171 0>, <&k3_clks 171 1>;
2644 clock-names = "hclk", "cclk";
2645 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
2646 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
2647 interrupt-names = "int0", "int1";
2648 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2649 status = "disabled";
2652 main_spi0: spi@2100000 {
2653 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2654 reg = <0x00 0x02100000 0x00 0x400>;
2655 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2656 #address-cells = <1>;
2658 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
2659 clocks = <&k3_clks 266 1>;
2660 status = "disabled";
2663 main_spi1: spi@2110000 {
2664 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2665 reg = <0x00 0x02110000 0x00 0x400>;
2666 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
2667 #address-cells = <1>;
2669 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
2670 clocks = <&k3_clks 267 1>;
2671 status = "disabled";
2674 main_spi2: spi@2120000 {
2675 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2676 reg = <0x00 0x02120000 0x00 0x400>;
2677 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
2678 #address-cells = <1>;
2680 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
2681 clocks = <&k3_clks 268 1>;
2682 status = "disabled";
2685 main_spi3: spi@2130000 {
2686 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2687 reg = <0x00 0x02130000 0x00 0x400>;
2688 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
2689 #address-cells = <1>;
2691 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
2692 clocks = <&k3_clks 269 1>;
2693 status = "disabled";
2696 main_spi4: spi@2140000 {
2697 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2698 reg = <0x00 0x02140000 0x00 0x400>;
2699 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
2700 #address-cells = <1>;
2702 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
2703 clocks = <&k3_clks 270 1>;
2704 status = "disabled";
2707 main_spi5: spi@2150000 {
2708 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2709 reg = <0x00 0x02150000 0x00 0x400>;
2710 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
2711 #address-cells = <1>;
2713 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
2714 clocks = <&k3_clks 271 1>;
2715 status = "disabled";
2718 main_spi6: spi@2160000 {
2719 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2720 reg = <0x00 0x02160000 0x00 0x400>;
2721 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
2722 #address-cells = <1>;
2724 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
2725 clocks = <&k3_clks 272 1>;
2726 status = "disabled";
2729 main_spi7: spi@2170000 {
2730 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
2731 reg = <0x00 0x02170000 0x00 0x400>;
2732 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
2733 #address-cells = <1>;
2735 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
2736 clocks = <&k3_clks 273 1>;
2737 status = "disabled";
2740 main_esm: esm@700000 {
2741 compatible = "ti,j721e-esm";
2742 reg = <0x0 0x700000 0x0 0x1000>;
2743 ti,esm-pins = <344>, <345>;