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Squashed 'dts/upstream/' changes from aaba2d45dc2a..b35b9bd1d4ee
[thirdparty/u-boot.git] / src / arm64 / ti / k3-j721s2-main.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for J721S2 SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
10
11 / {
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
16 };
17 };
18
19 &cbass_main {
20 msmc_ram: sram@70000000 {
21 compatible = "mmio-sram";
22 reg = <0x0 0x70000000 0x0 0x400000>;
23 #address-cells = <1>;
24 #size-cells = <1>;
25 ranges = <0x0 0x0 0x70000000 0x400000>;
26
27 atf-sram@0 {
28 reg = <0x0 0x20000>;
29 };
30
31 tifs-sram@1f0000 {
32 reg = <0x1f0000 0x10000>;
33 };
34
35 l3cache-sram@200000 {
36 reg = <0x200000 0x200000>;
37 };
38 };
39
40 scm_conf: syscon@104000 {
41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
42 reg = <0x00 0x00104000 0x00 0x18000>;
43 #address-cells = <1>;
44 #size-cells = <1>;
45 ranges = <0x00 0x00 0x00104000 0x18000>;
46
47 usb_serdes_mux: mux-controller@0 {
48 compatible = "mmio-mux";
49 reg = <0x0 0x4>;
50 #mux-control-cells = <1>;
51 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
52 };
53
54 phy_gmii_sel_cpsw: phy@34 {
55 compatible = "ti,am654-phy-gmii-sel";
56 reg = <0x34 0x4>;
57 #phy-cells = <1>;
58 };
59
60 serdes_ln_ctrl: mux-controller@80 {
61 compatible = "mmio-mux";
62 reg = <0x80 0x10>;
63 #mux-control-cells = <1>;
64 mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
65 <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
66 };
67
68 ehrpwm_tbclk: clock-controller@140 {
69 compatible = "ti,am654-ehrpwm-tbclk";
70 reg = <0x140 0x18>;
71 #clock-cells = <1>;
72 };
73 };
74
75 main_ehrpwm0: pwm@3000000 {
76 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
77 #pwm-cells = <3>;
78 reg = <0x00 0x3000000 0x00 0x100>;
79 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
80 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>;
81 clock-names = "tbclk", "fck";
82 status = "disabled";
83 };
84
85 main_ehrpwm1: pwm@3010000 {
86 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
87 #pwm-cells = <3>;
88 reg = <0x00 0x3010000 0x00 0x100>;
89 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
90 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>;
91 clock-names = "tbclk", "fck";
92 status = "disabled";
93 };
94
95 main_ehrpwm2: pwm@3020000 {
96 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
97 #pwm-cells = <3>;
98 reg = <0x00 0x3020000 0x00 0x100>;
99 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
100 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>;
101 clock-names = "tbclk", "fck";
102 status = "disabled";
103 };
104
105 main_ehrpwm3: pwm@3030000 {
106 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
107 #pwm-cells = <3>;
108 reg = <0x00 0x3030000 0x00 0x100>;
109 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
110 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>;
111 clock-names = "tbclk", "fck";
112 status = "disabled";
113 };
114
115 main_ehrpwm4: pwm@3040000 {
116 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
117 #pwm-cells = <3>;
118 reg = <0x00 0x3040000 0x00 0x100>;
119 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
120 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>;
121 clock-names = "tbclk", "fck";
122 status = "disabled";
123 };
124
125 main_ehrpwm5: pwm@3050000 {
126 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
127 #pwm-cells = <3>;
128 reg = <0x00 0x3050000 0x00 0x100>;
129 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
130 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>;
131 clock-names = "tbclk", "fck";
132 status = "disabled";
133 };
134
135 gic500: interrupt-controller@1800000 {
136 compatible = "arm,gic-v3";
137 #address-cells = <2>;
138 #size-cells = <2>;
139 ranges;
140 #interrupt-cells = <3>;
141 interrupt-controller;
142 reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */
143 <0x00 0x01900000 0x00 0x100000>, /* GICR */
144 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
145 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
146 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
147
148 /* vcpumntirq: virtual CPU interface maintenance interrupt */
149 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
150
151 gic_its: msi-controller@1820000 {
152 compatible = "arm,gic-v3-its";
153 reg = <0x00 0x01820000 0x00 0x10000>;
154 socionext,synquacer-pre-its = <0x1000000 0x400000>;
155 msi-controller;
156 #msi-cells = <1>;
157 };
158 };
159
160 main_gpio_intr: interrupt-controller@a00000 {
161 compatible = "ti,sci-intr";
162 reg = <0x00 0x00a00000 0x00 0x800>;
163 ti,intr-trigger-type = <1>;
164 interrupt-controller;
165 interrupt-parent = <&gic500>;
166 #interrupt-cells = <1>;
167 ti,sci = <&sms>;
168 ti,sci-dev-id = <148>;
169 ti,interrupt-ranges = <8 392 56>;
170 };
171
172 main_pmx0: pinctrl@11c000 {
173 compatible = "pinctrl-single";
174 /* Proxy 0 addressing */
175 reg = <0x0 0x11c000 0x0 0x120>;
176 #pinctrl-cells = <1>;
177 pinctrl-single,register-width = <32>;
178 pinctrl-single,function-mask = <0xffffffff>;
179 };
180
181 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
182 main_timerio_input: pinctrl@104200 {
183 compatible = "pinctrl-single";
184 reg = <0x00 0x104200 0x00 0x50>;
185 #pinctrl-cells = <1>;
186 pinctrl-single,register-width = <32>;
187 pinctrl-single,function-mask = <0x00000007>;
188 };
189
190 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
191 main_timerio_output: pinctrl@104280 {
192 compatible = "pinctrl-single";
193 reg = <0x00 0x104280 0x00 0x20>;
194 #pinctrl-cells = <1>;
195 pinctrl-single,register-width = <32>;
196 pinctrl-single,function-mask = <0x0000001f>;
197 };
198
199 main_crypto: crypto@4e00000 {
200 compatible = "ti,j721e-sa2ul";
201 reg = <0x00 0x04e00000 0x00 0x1200>;
202 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
203 #address-cells = <2>;
204 #size-cells = <2>;
205 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
206
207 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
208 <&main_udmap 0x4a41>;
209 dma-names = "tx", "rx1", "rx2";
210
211 rng: rng@4e10000 {
212 compatible = "inside-secure,safexcel-eip76";
213 reg = <0x00 0x04e10000 0x00 0x7d>;
214 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
215 };
216 };
217
218 main_timer0: timer@2400000 {
219 compatible = "ti,am654-timer";
220 reg = <0x00 0x2400000 0x00 0x400>;
221 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&k3_clks 63 1>;
223 clock-names = "fck";
224 assigned-clocks = <&k3_clks 63 1>;
225 assigned-clock-parents = <&k3_clks 63 2>;
226 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
227 ti,timer-pwm;
228 };
229
230 main_timer1: timer@2410000 {
231 compatible = "ti,am654-timer";
232 reg = <0x00 0x2410000 0x00 0x400>;
233 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&k3_clks 64 1>;
235 clock-names = "fck";
236 assigned-clocks = <&k3_clks 64 1>;
237 assigned-clock-parents = <&k3_clks 64 2>;
238 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
239 ti,timer-pwm;
240 };
241
242 main_timer2: timer@2420000 {
243 compatible = "ti,am654-timer";
244 reg = <0x00 0x2420000 0x00 0x400>;
245 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&k3_clks 65 1>;
247 clock-names = "fck";
248 assigned-clocks = <&k3_clks 65 1>;
249 assigned-clock-parents = <&k3_clks 65 2>;
250 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
251 ti,timer-pwm;
252 };
253
254 main_timer3: timer@2430000 {
255 compatible = "ti,am654-timer";
256 reg = <0x00 0x2430000 0x00 0x400>;
257 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&k3_clks 66 1>;
259 clock-names = "fck";
260 assigned-clocks = <&k3_clks 66 1>;
261 assigned-clock-parents = <&k3_clks 66 2>;
262 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
263 ti,timer-pwm;
264 };
265
266 main_timer4: timer@2440000 {
267 compatible = "ti,am654-timer";
268 reg = <0x00 0x2440000 0x00 0x400>;
269 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&k3_clks 67 1>;
271 clock-names = "fck";
272 assigned-clocks = <&k3_clks 67 1>;
273 assigned-clock-parents = <&k3_clks 67 2>;
274 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
275 ti,timer-pwm;
276 };
277
278 main_timer5: timer@2450000 {
279 compatible = "ti,am654-timer";
280 reg = <0x00 0x2450000 0x00 0x400>;
281 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&k3_clks 68 1>;
283 clock-names = "fck";
284 assigned-clocks = <&k3_clks 68 1>;
285 assigned-clock-parents = <&k3_clks 68 2>;
286 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
287 ti,timer-pwm;
288 };
289
290 main_timer6: timer@2460000 {
291 compatible = "ti,am654-timer";
292 reg = <0x00 0x2460000 0x00 0x400>;
293 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&k3_clks 69 1>;
295 clock-names = "fck";
296 assigned-clocks = <&k3_clks 69 1>;
297 assigned-clock-parents = <&k3_clks 69 2>;
298 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
299 ti,timer-pwm;
300 };
301
302 main_timer7: timer@2470000 {
303 compatible = "ti,am654-timer";
304 reg = <0x00 0x2470000 0x00 0x400>;
305 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&k3_clks 70 1>;
307 clock-names = "fck";
308 assigned-clocks = <&k3_clks 70 1>;
309 assigned-clock-parents = <&k3_clks 70 2>;
310 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
311 ti,timer-pwm;
312 };
313
314 main_timer8: timer@2480000 {
315 compatible = "ti,am654-timer";
316 reg = <0x00 0x2480000 0x00 0x400>;
317 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&k3_clks 71 1>;
319 clock-names = "fck";
320 assigned-clocks = <&k3_clks 71 1>;
321 assigned-clock-parents = <&k3_clks 71 2>;
322 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>;
323 ti,timer-pwm;
324 };
325
326 main_timer9: timer@2490000 {
327 compatible = "ti,am654-timer";
328 reg = <0x00 0x2490000 0x00 0x400>;
329 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&k3_clks 72 1>;
331 clock-names = "fck";
332 assigned-clocks = <&k3_clks 72 1>;
333 assigned-clock-parents = <&k3_clks 72 2>;
334 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>;
335 ti,timer-pwm;
336 };
337
338 main_timer10: timer@24a0000 {
339 compatible = "ti,am654-timer";
340 reg = <0x00 0x24a0000 0x00 0x400>;
341 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&k3_clks 73 1>;
343 clock-names = "fck";
344 assigned-clocks = <&k3_clks 73 1>;
345 assigned-clock-parents = <&k3_clks 73 2>;
346 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>;
347 ti,timer-pwm;
348 };
349
350 main_timer11: timer@24b0000 {
351 compatible = "ti,am654-timer";
352 reg = <0x00 0x24b0000 0x00 0x400>;
353 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&k3_clks 74 1>;
355 clock-names = "fck";
356 assigned-clocks = <&k3_clks 74 1>;
357 assigned-clock-parents = <&k3_clks 74 2>;
358 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>;
359 ti,timer-pwm;
360 };
361
362 main_timer12: timer@24c0000 {
363 compatible = "ti,am654-timer";
364 reg = <0x00 0x24c0000 0x00 0x400>;
365 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&k3_clks 75 1>;
367 clock-names = "fck";
368 assigned-clocks = <&k3_clks 75 1>;
369 assigned-clock-parents = <&k3_clks 75 2>;
370 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
371 ti,timer-pwm;
372 };
373
374 main_timer13: timer@24d0000 {
375 compatible = "ti,am654-timer";
376 reg = <0x00 0x24d0000 0x00 0x400>;
377 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&k3_clks 76 1>;
379 clock-names = "fck";
380 assigned-clocks = <&k3_clks 76 1>;
381 assigned-clock-parents = <&k3_clks 76 2>;
382 power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>;
383 ti,timer-pwm;
384 };
385
386 main_timer14: timer@24e0000 {
387 compatible = "ti,am654-timer";
388 reg = <0x00 0x24e0000 0x00 0x400>;
389 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&k3_clks 77 1>;
391 clock-names = "fck";
392 assigned-clocks = <&k3_clks 77 1>;
393 assigned-clock-parents = <&k3_clks 77 2>;
394 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
395 ti,timer-pwm;
396 };
397
398 main_timer15: timer@24f0000 {
399 compatible = "ti,am654-timer";
400 reg = <0x00 0x24f0000 0x00 0x400>;
401 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&k3_clks 78 1>;
403 clock-names = "fck";
404 assigned-clocks = <&k3_clks 78 1>;
405 assigned-clock-parents = <&k3_clks 78 2>;
406 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
407 ti,timer-pwm;
408 };
409
410 main_timer16: timer@2500000 {
411 compatible = "ti,am654-timer";
412 reg = <0x00 0x2500000 0x00 0x400>;
413 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&k3_clks 79 1>;
415 clock-names = "fck";
416 assigned-clocks = <&k3_clks 79 1>;
417 assigned-clock-parents = <&k3_clks 79 2>;
418 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
419 ti,timer-pwm;
420 };
421
422 main_timer17: timer@2510000 {
423 compatible = "ti,am654-timer";
424 reg = <0x00 0x2510000 0x00 0x400>;
425 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&k3_clks 80 1>;
427 clock-names = "fck";
428 assigned-clocks = <&k3_clks 80 1>;
429 assigned-clock-parents = <&k3_clks 80 2>;
430 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
431 ti,timer-pwm;
432 };
433
434 main_timer18: timer@2520000 {
435 compatible = "ti,am654-timer";
436 reg = <0x00 0x2520000 0x00 0x400>;
437 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&k3_clks 81 1>;
439 clock-names = "fck";
440 assigned-clocks = <&k3_clks 81 1>;
441 assigned-clock-parents = <&k3_clks 81 2>;
442 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>;
443 ti,timer-pwm;
444 };
445
446 main_timer19: timer@2530000 {
447 compatible = "ti,am654-timer";
448 reg = <0x00 0x2530000 0x00 0x400>;
449 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&k3_clks 82 1>;
451 clock-names = "fck";
452 assigned-clocks = <&k3_clks 82 1>;
453 assigned-clock-parents = <&k3_clks 82 2>;
454 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>;
455 ti,timer-pwm;
456 };
457
458 main_uart0: serial@2800000 {
459 compatible = "ti,j721e-uart", "ti,am654-uart";
460 reg = <0x00 0x02800000 0x00 0x200>;
461 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
462 current-speed = <115200>;
463 clocks = <&k3_clks 146 3>;
464 clock-names = "fclk";
465 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
466 status = "disabled";
467 };
468
469 main_uart1: serial@2810000 {
470 compatible = "ti,j721e-uart", "ti,am654-uart";
471 reg = <0x00 0x02810000 0x00 0x200>;
472 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
473 current-speed = <115200>;
474 clocks = <&k3_clks 350 3>;
475 clock-names = "fclk";
476 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
477 status = "disabled";
478 };
479
480 main_uart2: serial@2820000 {
481 compatible = "ti,j721e-uart", "ti,am654-uart";
482 reg = <0x00 0x02820000 0x00 0x200>;
483 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
484 current-speed = <115200>;
485 clocks = <&k3_clks 351 3>;
486 clock-names = "fclk";
487 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
488 status = "disabled";
489 };
490
491 main_uart3: serial@2830000 {
492 compatible = "ti,j721e-uart", "ti,am654-uart";
493 reg = <0x00 0x02830000 0x00 0x200>;
494 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
495 current-speed = <115200>;
496 clocks = <&k3_clks 352 3>;
497 clock-names = "fclk";
498 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
499 status = "disabled";
500 };
501
502 main_uart4: serial@2840000 {
503 compatible = "ti,j721e-uart", "ti,am654-uart";
504 reg = <0x00 0x02840000 0x00 0x200>;
505 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
506 current-speed = <115200>;
507 clocks = <&k3_clks 353 3>;
508 clock-names = "fclk";
509 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
510 status = "disabled";
511 };
512
513 main_uart5: serial@2850000 {
514 compatible = "ti,j721e-uart", "ti,am654-uart";
515 reg = <0x00 0x02850000 0x00 0x200>;
516 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
517 current-speed = <115200>;
518 clocks = <&k3_clks 354 3>;
519 clock-names = "fclk";
520 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
521 status = "disabled";
522 };
523
524 main_uart6: serial@2860000 {
525 compatible = "ti,j721e-uart", "ti,am654-uart";
526 reg = <0x00 0x02860000 0x00 0x200>;
527 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
528 current-speed = <115200>;
529 clocks = <&k3_clks 355 3>;
530 clock-names = "fclk";
531 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
532 status = "disabled";
533 };
534
535 main_uart7: serial@2870000 {
536 compatible = "ti,j721e-uart", "ti,am654-uart";
537 reg = <0x00 0x02870000 0x00 0x200>;
538 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
539 current-speed = <115200>;
540 clocks = <&k3_clks 356 3>;
541 clock-names = "fclk";
542 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
543 status = "disabled";
544 };
545
546 main_uart8: serial@2880000 {
547 compatible = "ti,j721e-uart", "ti,am654-uart";
548 reg = <0x00 0x02880000 0x00 0x200>;
549 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
550 current-speed = <115200>;
551 clocks = <&k3_clks 357 3>;
552 clock-names = "fclk";
553 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
554 status = "disabled";
555 };
556
557 main_uart9: serial@2890000 {
558 compatible = "ti,j721e-uart", "ti,am654-uart";
559 reg = <0x00 0x02890000 0x00 0x200>;
560 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
561 current-speed = <115200>;
562 clocks = <&k3_clks 358 3>;
563 clock-names = "fclk";
564 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
565 status = "disabled";
566 };
567
568 main_gpio0: gpio@600000 {
569 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
570 reg = <0x00 0x00600000 0x00 0x100>;
571 gpio-controller;
572 #gpio-cells = <2>;
573 interrupt-parent = <&main_gpio_intr>;
574 interrupts = <145>, <146>, <147>, <148>, <149>;
575 interrupt-controller;
576 #interrupt-cells = <2>;
577 ti,ngpio = <66>;
578 ti,davinci-gpio-unbanked = <0>;
579 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
580 clocks = <&k3_clks 111 0>;
581 clock-names = "gpio";
582 status = "disabled";
583 };
584
585 main_gpio2: gpio@610000 {
586 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
587 reg = <0x00 0x00610000 0x00 0x100>;
588 gpio-controller;
589 #gpio-cells = <2>;
590 interrupt-parent = <&main_gpio_intr>;
591 interrupts = <154>, <155>, <156>, <157>, <158>;
592 interrupt-controller;
593 #interrupt-cells = <2>;
594 ti,ngpio = <66>;
595 ti,davinci-gpio-unbanked = <0>;
596 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
597 clocks = <&k3_clks 112 0>;
598 clock-names = "gpio";
599 status = "disabled";
600 };
601
602 main_gpio4: gpio@620000 {
603 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
604 reg = <0x00 0x00620000 0x00 0x100>;
605 gpio-controller;
606 #gpio-cells = <2>;
607 interrupt-parent = <&main_gpio_intr>;
608 interrupts = <163>, <164>, <165>, <166>, <167>;
609 interrupt-controller;
610 #interrupt-cells = <2>;
611 ti,ngpio = <66>;
612 ti,davinci-gpio-unbanked = <0>;
613 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
614 clocks = <&k3_clks 113 0>;
615 clock-names = "gpio";
616 status = "disabled";
617 };
618
619 main_gpio6: gpio@630000 {
620 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
621 reg = <0x00 0x00630000 0x00 0x100>;
622 gpio-controller;
623 #gpio-cells = <2>;
624 interrupt-parent = <&main_gpio_intr>;
625 interrupts = <172>, <173>, <174>, <175>, <176>;
626 interrupt-controller;
627 #interrupt-cells = <2>;
628 ti,ngpio = <66>;
629 ti,davinci-gpio-unbanked = <0>;
630 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
631 clocks = <&k3_clks 114 0>;
632 clock-names = "gpio";
633 status = "disabled";
634 };
635
636 main_i2c0: i2c@2000000 {
637 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
638 reg = <0x00 0x02000000 0x00 0x100>;
639 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
640 #address-cells = <1>;
641 #size-cells = <0>;
642 clocks = <&k3_clks 214 1>;
643 clock-names = "fck";
644 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
645 };
646
647 main_i2c1: i2c@2010000 {
648 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
649 reg = <0x00 0x02010000 0x00 0x100>;
650 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
651 #address-cells = <1>;
652 #size-cells = <0>;
653 clocks = <&k3_clks 215 1>;
654 clock-names = "fck";
655 power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
656 status = "disabled";
657 };
658
659 main_i2c2: i2c@2020000 {
660 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
661 reg = <0x00 0x02020000 0x00 0x100>;
662 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
663 #address-cells = <1>;
664 #size-cells = <0>;
665 clocks = <&k3_clks 216 1>;
666 clock-names = "fck";
667 power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
668 status = "disabled";
669 };
670
671 main_i2c3: i2c@2030000 {
672 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
673 reg = <0x00 0x02030000 0x00 0x100>;
674 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
675 #address-cells = <1>;
676 #size-cells = <0>;
677 clocks = <&k3_clks 217 1>;
678 clock-names = "fck";
679 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
680 status = "disabled";
681 };
682
683 main_i2c4: i2c@2040000 {
684 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
685 reg = <0x00 0x02040000 0x00 0x100>;
686 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
687 #address-cells = <1>;
688 #size-cells = <0>;
689 clocks = <&k3_clks 218 1>;
690 clock-names = "fck";
691 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
692 status = "disabled";
693 };
694
695 main_i2c5: i2c@2050000 {
696 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
697 reg = <0x00 0x02050000 0x00 0x100>;
698 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
699 #address-cells = <1>;
700 #size-cells = <0>;
701 clocks = <&k3_clks 219 1>;
702 clock-names = "fck";
703 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
704 status = "disabled";
705 };
706
707 main_i2c6: i2c@2060000 {
708 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
709 reg = <0x00 0x02060000 0x00 0x100>;
710 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
711 #address-cells = <1>;
712 #size-cells = <0>;
713 clocks = <&k3_clks 220 1>;
714 clock-names = "fck";
715 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
716 status = "disabled";
717 };
718
719 main_sdhci0: mmc@4f80000 {
720 compatible = "ti,j721e-sdhci-8bit";
721 reg = <0x00 0x04f80000 0x00 0x1000>,
722 <0x00 0x04f88000 0x00 0x400>;
723 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
724 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
725 clocks = <&k3_clks 98 7>, <&k3_clks 98 1>;
726 clock-names = "clk_ahb", "clk_xin";
727 assigned-clocks = <&k3_clks 98 1>;
728 assigned-clock-parents = <&k3_clks 98 2>;
729 bus-width = <8>;
730 ti,otap-del-sel-legacy = <0x0>;
731 ti,otap-del-sel-mmc-hs = <0x0>;
732 ti,otap-del-sel-ddr52 = <0x6>;
733 ti,otap-del-sel-hs200 = <0x8>;
734 ti,otap-del-sel-hs400 = <0x5>;
735 ti,itap-del-sel-legacy = <0x10>;
736 ti,itap-del-sel-mmc-hs = <0xa>;
737 ti,strobe-sel = <0x77>;
738 ti,clkbuf-sel = <0x7>;
739 ti,trm-icp = <0x8>;
740 mmc-ddr-1_8v;
741 mmc-hs200-1_8v;
742 mmc-hs400-1_8v;
743 dma-coherent;
744 status = "disabled";
745 };
746
747 main_sdhci1: mmc@4fb0000 {
748 compatible = "ti,j721e-sdhci-4bit";
749 reg = <0x00 0x04fb0000 0x00 0x1000>,
750 <0x00 0x04fb8000 0x00 0x400>;
751 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
752 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
753 clocks = <&k3_clks 99 8>, <&k3_clks 99 1>;
754 clock-names = "clk_ahb", "clk_xin";
755 assigned-clocks = <&k3_clks 99 1>;
756 assigned-clock-parents = <&k3_clks 99 2>;
757 bus-width = <4>;
758 ti,otap-del-sel-legacy = <0x0>;
759 ti,otap-del-sel-sd-hs = <0x0>;
760 ti,otap-del-sel-sdr12 = <0xf>;
761 ti,otap-del-sel-sdr25 = <0xf>;
762 ti,otap-del-sel-sdr50 = <0xc>;
763 ti,otap-del-sel-sdr104 = <0x5>;
764 ti,otap-del-sel-ddr50 = <0xc>;
765 ti,itap-del-sel-legacy = <0x0>;
766 ti,itap-del-sel-sd-hs = <0x0>;
767 ti,itap-del-sel-sdr12 = <0x0>;
768 ti,itap-del-sel-sdr25 = <0x0>;
769 ti,itap-del-sel-ddr50 = <0x2>;
770 ti,clkbuf-sel = <0x7>;
771 ti,trm-icp = <0x8>;
772 dma-coherent;
773 /* Masking support for SDR104 capability */
774 sdhci-caps-mask = <0x00000003 0x00000000>;
775 status = "disabled";
776 };
777
778 main_navss: bus@30000000 {
779 compatible = "simple-bus";
780 #address-cells = <2>;
781 #size-cells = <2>;
782 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
783 ti,sci-dev-id = <224>;
784 dma-coherent;
785 dma-ranges;
786
787 main_navss_intr: interrupt-controller@310e0000 {
788 compatible = "ti,sci-intr";
789 reg = <0x00 0x310e0000 0x00 0x4000>;
790 ti,intr-trigger-type = <4>;
791 interrupt-controller;
792 interrupt-parent = <&gic500>;
793 #interrupt-cells = <1>;
794 ti,sci = <&sms>;
795 ti,sci-dev-id = <227>;
796 ti,interrupt-ranges = <0 64 64>,
797 <64 448 64>,
798 <128 672 64>;
799 };
800
801 main_udmass_inta: msi-controller@33d00000 {
802 compatible = "ti,sci-inta";
803 reg = <0x00 0x33d00000 0x00 0x100000>;
804 interrupt-controller;
805 #interrupt-cells = <0>;
806 interrupt-parent = <&main_navss_intr>;
807 msi-controller;
808 ti,sci = <&sms>;
809 ti,sci-dev-id = <265>;
810 ti,interrupt-ranges = <0 0 256>;
811 ti,unmapped-event-sources = <&main_bcdma_csi>;
812 };
813
814 secure_proxy_main: mailbox@32c00000 {
815 compatible = "ti,am654-secure-proxy";
816 #mbox-cells = <1>;
817 reg-names = "target_data", "rt", "scfg";
818 reg = <0x00 0x32c00000 0x00 0x100000>,
819 <0x00 0x32400000 0x00 0x100000>,
820 <0x00 0x32800000 0x00 0x100000>;
821 interrupt-names = "rx_011";
822 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
823 };
824
825 hwspinlock: spinlock@30e00000 {
826 compatible = "ti,am654-hwspinlock";
827 reg = <0x00 0x30e00000 0x00 0x1000>;
828 #hwlock-cells = <1>;
829 };
830
831 mailbox0_cluster0: mailbox@31f80000 {
832 compatible = "ti,am654-mailbox";
833 reg = <0x00 0x31f80000 0x00 0x200>;
834 #mbox-cells = <1>;
835 ti,mbox-num-users = <4>;
836 ti,mbox-num-fifos = <16>;
837 interrupt-parent = <&main_navss_intr>;
838 status = "disabled";
839 };
840
841 mailbox0_cluster1: mailbox@31f81000 {
842 compatible = "ti,am654-mailbox";
843 reg = <0x00 0x31f81000 0x00 0x200>;
844 #mbox-cells = <1>;
845 ti,mbox-num-users = <4>;
846 ti,mbox-num-fifos = <16>;
847 interrupt-parent = <&main_navss_intr>;
848 status = "disabled";
849 };
850
851 mailbox0_cluster2: mailbox@31f82000 {
852 compatible = "ti,am654-mailbox";
853 reg = <0x00 0x31f82000 0x00 0x200>;
854 #mbox-cells = <1>;
855 ti,mbox-num-users = <4>;
856 ti,mbox-num-fifos = <16>;
857 interrupt-parent = <&main_navss_intr>;
858 status = "disabled";
859 };
860
861 mailbox0_cluster3: mailbox@31f83000 {
862 compatible = "ti,am654-mailbox";
863 reg = <0x00 0x31f83000 0x00 0x200>;
864 #mbox-cells = <1>;
865 ti,mbox-num-users = <4>;
866 ti,mbox-num-fifos = <16>;
867 interrupt-parent = <&main_navss_intr>;
868 status = "disabled";
869 };
870
871 mailbox0_cluster4: mailbox@31f84000 {
872 compatible = "ti,am654-mailbox";
873 reg = <0x00 0x31f84000 0x00 0x200>;
874 #mbox-cells = <1>;
875 ti,mbox-num-users = <4>;
876 ti,mbox-num-fifos = <16>;
877 interrupt-parent = <&main_navss_intr>;
878 status = "disabled";
879 };
880
881 mailbox0_cluster5: mailbox@31f85000 {
882 compatible = "ti,am654-mailbox";
883 reg = <0x00 0x31f85000 0x00 0x200>;
884 #mbox-cells = <1>;
885 ti,mbox-num-users = <4>;
886 ti,mbox-num-fifos = <16>;
887 interrupt-parent = <&main_navss_intr>;
888 status = "disabled";
889 };
890
891 mailbox0_cluster6: mailbox@31f86000 {
892 compatible = "ti,am654-mailbox";
893 reg = <0x00 0x31f86000 0x00 0x200>;
894 #mbox-cells = <1>;
895 ti,mbox-num-users = <4>;
896 ti,mbox-num-fifos = <16>;
897 interrupt-parent = <&main_navss_intr>;
898 status = "disabled";
899 };
900
901 mailbox0_cluster7: mailbox@31f87000 {
902 compatible = "ti,am654-mailbox";
903 reg = <0x00 0x31f87000 0x00 0x200>;
904 #mbox-cells = <1>;
905 ti,mbox-num-users = <4>;
906 ti,mbox-num-fifos = <16>;
907 interrupt-parent = <&main_navss_intr>;
908 status = "disabled";
909 };
910
911 mailbox0_cluster8: mailbox@31f88000 {
912 compatible = "ti,am654-mailbox";
913 reg = <0x00 0x31f88000 0x00 0x200>;
914 #mbox-cells = <1>;
915 ti,mbox-num-users = <4>;
916 ti,mbox-num-fifos = <16>;
917 interrupt-parent = <&main_navss_intr>;
918 status = "disabled";
919 };
920
921 mailbox0_cluster9: mailbox@31f89000 {
922 compatible = "ti,am654-mailbox";
923 reg = <0x00 0x31f89000 0x00 0x200>;
924 #mbox-cells = <1>;
925 ti,mbox-num-users = <4>;
926 ti,mbox-num-fifos = <16>;
927 interrupt-parent = <&main_navss_intr>;
928 status = "disabled";
929 };
930
931 mailbox0_cluster10: mailbox@31f8a000 {
932 compatible = "ti,am654-mailbox";
933 reg = <0x00 0x31f8a000 0x00 0x200>;
934 #mbox-cells = <1>;
935 ti,mbox-num-users = <4>;
936 ti,mbox-num-fifos = <16>;
937 interrupt-parent = <&main_navss_intr>;
938 status = "disabled";
939 };
940
941 mailbox0_cluster11: mailbox@31f8b000 {
942 compatible = "ti,am654-mailbox";
943 reg = <0x00 0x31f8b000 0x00 0x200>;
944 #mbox-cells = <1>;
945 ti,mbox-num-users = <4>;
946 ti,mbox-num-fifos = <16>;
947 interrupt-parent = <&main_navss_intr>;
948 status = "disabled";
949 };
950
951 mailbox1_cluster0: mailbox@31f90000 {
952 compatible = "ti,am654-mailbox";
953 reg = <0x00 0x31f90000 0x00 0x200>;
954 #mbox-cells = <1>;
955 ti,mbox-num-users = <4>;
956 ti,mbox-num-fifos = <16>;
957 interrupt-parent = <&main_navss_intr>;
958 status = "disabled";
959 };
960
961 mailbox1_cluster1: mailbox@31f91000 {
962 compatible = "ti,am654-mailbox";
963 reg = <0x00 0x31f91000 0x00 0x200>;
964 #mbox-cells = <1>;
965 ti,mbox-num-users = <4>;
966 ti,mbox-num-fifos = <16>;
967 interrupt-parent = <&main_navss_intr>;
968 status = "disabled";
969 };
970
971 mailbox1_cluster2: mailbox@31f92000 {
972 compatible = "ti,am654-mailbox";
973 reg = <0x00 0x31f92000 0x00 0x200>;
974 #mbox-cells = <1>;
975 ti,mbox-num-users = <4>;
976 ti,mbox-num-fifos = <16>;
977 interrupt-parent = <&main_navss_intr>;
978 status = "disabled";
979 };
980
981 mailbox1_cluster3: mailbox@31f93000 {
982 compatible = "ti,am654-mailbox";
983 reg = <0x00 0x31f93000 0x00 0x200>;
984 #mbox-cells = <1>;
985 ti,mbox-num-users = <4>;
986 ti,mbox-num-fifos = <16>;
987 interrupt-parent = <&main_navss_intr>;
988 status = "disabled";
989 };
990
991 mailbox1_cluster4: mailbox@31f94000 {
992 compatible = "ti,am654-mailbox";
993 reg = <0x00 0x31f94000 0x00 0x200>;
994 #mbox-cells = <1>;
995 ti,mbox-num-users = <4>;
996 ti,mbox-num-fifos = <16>;
997 interrupt-parent = <&main_navss_intr>;
998 status = "disabled";
999 };
1000
1001 mailbox1_cluster5: mailbox@31f95000 {
1002 compatible = "ti,am654-mailbox";
1003 reg = <0x00 0x31f95000 0x00 0x200>;
1004 #mbox-cells = <1>;
1005 ti,mbox-num-users = <4>;
1006 ti,mbox-num-fifos = <16>;
1007 interrupt-parent = <&main_navss_intr>;
1008 status = "disabled";
1009 };
1010
1011 mailbox1_cluster6: mailbox@31f96000 {
1012 compatible = "ti,am654-mailbox";
1013 reg = <0x00 0x31f96000 0x00 0x200>;
1014 #mbox-cells = <1>;
1015 ti,mbox-num-users = <4>;
1016 ti,mbox-num-fifos = <16>;
1017 interrupt-parent = <&main_navss_intr>;
1018 status = "disabled";
1019 };
1020
1021 mailbox1_cluster7: mailbox@31f97000 {
1022 compatible = "ti,am654-mailbox";
1023 reg = <0x00 0x31f97000 0x00 0x200>;
1024 #mbox-cells = <1>;
1025 ti,mbox-num-users = <4>;
1026 ti,mbox-num-fifos = <16>;
1027 interrupt-parent = <&main_navss_intr>;
1028 status = "disabled";
1029 };
1030
1031 mailbox1_cluster8: mailbox@31f98000 {
1032 compatible = "ti,am654-mailbox";
1033 reg = <0x00 0x31f98000 0x00 0x200>;
1034 #mbox-cells = <1>;
1035 ti,mbox-num-users = <4>;
1036 ti,mbox-num-fifos = <16>;
1037 interrupt-parent = <&main_navss_intr>;
1038 status = "disabled";
1039 };
1040
1041 mailbox1_cluster9: mailbox@31f99000 {
1042 compatible = "ti,am654-mailbox";
1043 reg = <0x00 0x31f99000 0x00 0x200>;
1044 #mbox-cells = <1>;
1045 ti,mbox-num-users = <4>;
1046 ti,mbox-num-fifos = <16>;
1047 interrupt-parent = <&main_navss_intr>;
1048 status = "disabled";
1049 };
1050
1051 mailbox1_cluster10: mailbox@31f9a000 {
1052 compatible = "ti,am654-mailbox";
1053 reg = <0x00 0x31f9a000 0x00 0x200>;
1054 #mbox-cells = <1>;
1055 ti,mbox-num-users = <4>;
1056 ti,mbox-num-fifos = <16>;
1057 interrupt-parent = <&main_navss_intr>;
1058 status = "disabled";
1059 };
1060
1061 mailbox1_cluster11: mailbox@31f9b000 {
1062 compatible = "ti,am654-mailbox";
1063 reg = <0x00 0x31f9b000 0x00 0x200>;
1064 #mbox-cells = <1>;
1065 ti,mbox-num-users = <4>;
1066 ti,mbox-num-fifos = <16>;
1067 interrupt-parent = <&main_navss_intr>;
1068 status = "disabled";
1069 };
1070
1071 main_ringacc: ringacc@3c000000 {
1072 compatible = "ti,am654-navss-ringacc";
1073 reg = <0x0 0x3c000000 0x0 0x400000>,
1074 <0x0 0x38000000 0x0 0x400000>,
1075 <0x0 0x31120000 0x0 0x100>,
1076 <0x0 0x33000000 0x0 0x40000>,
1077 <0x0 0x31080000 0x0 0x40000>;
1078 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
1079 ti,num-rings = <1024>;
1080 ti,sci-rm-range-gp-rings = <0x1>;
1081 ti,sci = <&sms>;
1082 ti,sci-dev-id = <259>;
1083 msi-parent = <&main_udmass_inta>;
1084 };
1085
1086 main_udmap: dma-controller@31150000 {
1087 compatible = "ti,j721e-navss-main-udmap";
1088 reg = <0x0 0x31150000 0x0 0x100>,
1089 <0x0 0x34000000 0x0 0x80000>,
1090 <0x0 0x35000000 0x0 0x200000>,
1091 <0x0 0x30b00000 0x0 0x20000>,
1092 <0x0 0x30c00000 0x0 0x8000>,
1093 <0x0 0x30d00000 0x0 0x4000>;
1094 reg-names = "gcfg", "rchanrt", "tchanrt",
1095 "tchan", "rchan", "rflow";
1096 msi-parent = <&main_udmass_inta>;
1097 #dma-cells = <1>;
1098
1099 ti,sci = <&sms>;
1100 ti,sci-dev-id = <263>;
1101 ti,ringacc = <&main_ringacc>;
1102
1103 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
1104 <0x0f>, /* TX_HCHAN */
1105 <0x10>; /* TX_UHCHAN */
1106 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
1107 <0x0b>, /* RX_HCHAN */
1108 <0x0c>; /* RX_UHCHAN */
1109 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
1110 };
1111
1112 main_bcdma_csi: dma-controller@311a0000 {
1113 compatible = "ti,j721s2-dmss-bcdma-csi";
1114 reg = <0x00 0x311a0000 0x00 0x100>,
1115 <0x00 0x35d00000 0x00 0x20000>,
1116 <0x00 0x35c00000 0x00 0x10000>,
1117 <0x00 0x35e00000 0x00 0x80000>;
1118 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
1119 msi-parent = <&main_udmass_inta>;
1120 #dma-cells = <3>;
1121 ti,sci = <&sms>;
1122 ti,sci-dev-id = <225>;
1123 ti,sci-rm-range-rchan = <0x21>;
1124 ti,sci-rm-range-tchan = <0x22>;
1125 status = "disabled";
1126 };
1127
1128 cpts@310d0000 {
1129 compatible = "ti,j721e-cpts";
1130 reg = <0x0 0x310d0000 0x0 0x400>;
1131 reg-names = "cpts";
1132 clocks = <&k3_clks 226 5>;
1133 clock-names = "cpts";
1134 assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */
1135 assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */
1136 interrupts-extended = <&main_navss_intr 391>;
1137 interrupt-names = "cpts";
1138 ti,cpts-periodic-outputs = <6>;
1139 ti,cpts-ext-ts-inputs = <8>;
1140 };
1141 };
1142
1143 main_cpsw: ethernet@c200000 {
1144 compatible = "ti,j721e-cpsw-nuss";
1145 reg = <0x00 0xc200000 0x00 0x200000>;
1146 reg-names = "cpsw_nuss";
1147 ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>;
1148 #address-cells = <2>;
1149 #size-cells = <2>;
1150 dma-coherent;
1151 clocks = <&k3_clks 28 28>;
1152 clock-names = "fck";
1153 power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;
1154
1155 dmas = <&main_udmap 0xc640>,
1156 <&main_udmap 0xc641>,
1157 <&main_udmap 0xc642>,
1158 <&main_udmap 0xc643>,
1159 <&main_udmap 0xc644>,
1160 <&main_udmap 0xc645>,
1161 <&main_udmap 0xc646>,
1162 <&main_udmap 0xc647>,
1163 <&main_udmap 0x4640>;
1164 dma-names = "tx0", "tx1", "tx2", "tx3",
1165 "tx4", "tx5", "tx6", "tx7",
1166 "rx";
1167
1168 status = "disabled";
1169
1170 ethernet-ports {
1171 #address-cells = <1>;
1172 #size-cells = <0>;
1173
1174 main_cpsw_port1: port@1 {
1175 reg = <1>;
1176 ti,mac-only;
1177 label = "port1";
1178 phys = <&phy_gmii_sel_cpsw 1>;
1179 status = "disabled";
1180 };
1181 };
1182
1183 main_cpsw_mdio: mdio@f00 {
1184 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1185 reg = <0x00 0xf00 0x00 0x100>;
1186 #address-cells = <1>;
1187 #size-cells = <0>;
1188 clocks = <&k3_clks 28 28>;
1189 clock-names = "fck";
1190 bus_freq = <1000000>;
1191 status = "disabled";
1192 };
1193
1194 cpts@3d000 {
1195 compatible = "ti,am65-cpts";
1196 reg = <0x00 0x3d000 0x00 0x400>;
1197 clocks = <&k3_clks 28 3>;
1198 clock-names = "cpts";
1199 interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1200 interrupt-names = "cpts";
1201 ti,cpts-ext-ts-inputs = <4>;
1202 ti,cpts-periodic-outputs = <2>;
1203 };
1204 };
1205
1206 usbss0: cdns-usb@4104000 {
1207 compatible = "ti,j721e-usb";
1208 reg = <0x00 0x04104000 0x00 0x100>;
1209 clocks = <&k3_clks 360 16>, <&k3_clks 360 15>;
1210 clock-names = "ref", "lpm";
1211 assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
1212 assigned-clock-parents = <&k3_clks 360 17>;
1213 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
1214 #address-cells = <2>;
1215 #size-cells = <2>;
1216 ranges;
1217 dma-coherent;
1218
1219 status = "disabled"; /* Needs pinmux */
1220
1221 usb0: usb@6000000 {
1222 compatible = "cdns,usb3";
1223 reg = <0x00 0x06000000 0x00 0x10000>,
1224 <0x00 0x06010000 0x00 0x10000>,
1225 <0x00 0x06020000 0x00 0x10000>;
1226 reg-names = "otg", "xhci", "dev";
1227 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1230 interrupt-names = "host", "peripheral", "otg";
1231 maximum-speed = "super-speed";
1232 dr_mode = "otg";
1233 };
1234 };
1235
1236 serdes_wiz0: wiz@5060000 {
1237 compatible = "ti,j721s2-wiz-10g";
1238 #address-cells = <1>;
1239 #size-cells = <1>;
1240 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
1241 clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
1242 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
1243 num-lanes = <4>;
1244 #reset-cells = <1>;
1245 #clock-cells = <1>;
1246 ranges = <0x5060000 0x0 0x5060000 0x10000>;
1247
1248 assigned-clocks = <&k3_clks 365 3>;
1249 assigned-clock-parents = <&k3_clks 365 7>;
1250
1251 serdes0: serdes@5060000 {
1252 compatible = "ti,j721e-serdes-10g";
1253 reg = <0x05060000 0x00010000>;
1254 reg-names = "torrent_phy";
1255 resets = <&serdes_wiz0 0>;
1256 reset-names = "torrent_reset";
1257 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
1258 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
1259 clock-names = "refclk", "phy_en_refclk";
1260 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
1261 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
1262 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
1263 assigned-clock-parents = <&k3_clks 365 3>,
1264 <&k3_clks 365 3>,
1265 <&k3_clks 365 3>;
1266 #address-cells = <1>;
1267 #size-cells = <0>;
1268 #clock-cells = <1>;
1269
1270 status = "disabled"; /* Needs lane config */
1271 };
1272 };
1273
1274 pcie1_rc: pcie@2910000 {
1275 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
1276 reg = <0x00 0x02910000 0x00 0x1000>,
1277 <0x00 0x02917000 0x00 0x400>,
1278 <0x00 0x0d800000 0x00 0x800000>,
1279 <0x00 0x18000000 0x00 0x1000>;
1280 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
1281 interrupt-names = "link_state";
1282 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
1283 device_type = "pci";
1284 ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
1285 max-link-speed = <3>;
1286 num-lanes = <4>;
1287 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
1288 clocks = <&k3_clks 276 41>;
1289 clock-names = "fck";
1290 #address-cells = <3>;
1291 #size-cells = <2>;
1292 bus-range = <0x0 0xff>;
1293 vendor-id = <0x104c>;
1294 device-id = <0xb013>;
1295 msi-map = <0x0 &gic_its 0x0 0x10000>;
1296 dma-coherent;
1297 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
1298 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
1299 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1300 #interrupt-cells = <1>;
1301 interrupt-map-mask = <0 0 0 7>;
1302 interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
1303 <0 0 0 2 &pcie1_intc 0>, /* INT B */
1304 <0 0 0 3 &pcie1_intc 0>, /* INT C */
1305 <0 0 0 4 &pcie1_intc 0>; /* INT D */
1306
1307 status = "disabled"; /* Needs gpio and serdes info */
1308
1309 pcie1_intc: interrupt-controller {
1310 interrupt-controller;
1311 #interrupt-cells = <1>;
1312 interrupt-parent = <&gic500>;
1313 interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
1314 };
1315 };
1316
1317 main_mcan0: can@2701000 {
1318 compatible = "bosch,m_can";
1319 reg = <0x00 0x02701000 0x00 0x200>,
1320 <0x00 0x02708000 0x00 0x8000>;
1321 reg-names = "m_can", "message_ram";
1322 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1323 clocks = <&k3_clks 182 0>, <&k3_clks 182 1>;
1324 clock-names = "hclk", "cclk";
1325 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1326 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
1327 interrupt-names = "int0", "int1";
1328 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1329 status = "disabled";
1330 };
1331
1332 main_mcan1: can@2711000 {
1333 compatible = "bosch,m_can";
1334 reg = <0x00 0x02711000 0x00 0x200>,
1335 <0x00 0x02718000 0x00 0x8000>;
1336 reg-names = "m_can", "message_ram";
1337 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1338 clocks = <&k3_clks 183 0>, <&k3_clks 183 1>;
1339 clock-names = "hclk", "cclk";
1340 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
1342 interrupt-names = "int0", "int1";
1343 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1344 status = "disabled";
1345 };
1346
1347 main_mcan2: can@2721000 {
1348 compatible = "bosch,m_can";
1349 reg = <0x00 0x02721000 0x00 0x200>,
1350 <0x00 0x02728000 0x00 0x8000>;
1351 reg-names = "m_can", "message_ram";
1352 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
1353 clocks = <&k3_clks 184 0>, <&k3_clks 184 1>;
1354 clock-names = "hclk", "cclk";
1355 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1356 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1357 interrupt-names = "int0", "int1";
1358 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1359 status = "disabled";
1360 };
1361
1362 main_mcan3: can@2731000 {
1363 compatible = "bosch,m_can";
1364 reg = <0x00 0x02731000 0x00 0x200>,
1365 <0x00 0x02738000 0x00 0x8000>;
1366 reg-names = "m_can", "message_ram";
1367 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1368 clocks = <&k3_clks 185 0>, <&k3_clks 185 1>;
1369 clock-names = "hclk", "cclk";
1370 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
1372 interrupt-names = "int0", "int1";
1373 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1374 status = "disabled";
1375 };
1376
1377 main_mcan4: can@2741000 {
1378 compatible = "bosch,m_can";
1379 reg = <0x00 0x02741000 0x00 0x200>,
1380 <0x00 0x02748000 0x00 0x8000>;
1381 reg-names = "m_can", "message_ram";
1382 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
1383 clocks = <&k3_clks 186 0>, <&k3_clks 186 1>;
1384 clock-names = "hclk", "cclk";
1385 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1386 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1387 interrupt-names = "int0", "int1";
1388 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1389 status = "disabled";
1390 };
1391
1392 main_mcan5: can@2751000 {
1393 compatible = "bosch,m_can";
1394 reg = <0x00 0x02751000 0x00 0x200>,
1395 <0x00 0x02758000 0x00 0x8000>;
1396 reg-names = "m_can", "message_ram";
1397 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
1398 clocks = <&k3_clks 187 0>, <&k3_clks 187 1>;
1399 clock-names = "hclk", "cclk";
1400 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
1401 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1402 interrupt-names = "int0", "int1";
1403 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1404 status = "disabled";
1405 };
1406
1407 main_mcan6: can@2761000 {
1408 compatible = "bosch,m_can";
1409 reg = <0x00 0x02761000 0x00 0x200>,
1410 <0x00 0x02768000 0x00 0x8000>;
1411 reg-names = "m_can", "message_ram";
1412 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1413 clocks = <&k3_clks 188 0>, <&k3_clks 188 1>;
1414 clock-names = "hclk", "cclk";
1415 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1416 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1417 interrupt-names = "int0", "int1";
1418 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1419 status = "disabled";
1420 };
1421
1422 main_mcan7: can@2771000 {
1423 compatible = "bosch,m_can";
1424 reg = <0x00 0x02771000 0x00 0x200>,
1425 <0x00 0x02778000 0x00 0x8000>;
1426 reg-names = "m_can", "message_ram";
1427 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1428 clocks = <&k3_clks 189 0>, <&k3_clks 189 1>;
1429 clock-names = "hclk", "cclk";
1430 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1431 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1432 interrupt-names = "int0", "int1";
1433 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1434 status = "disabled";
1435 };
1436
1437 main_mcan8: can@2781000 {
1438 compatible = "bosch,m_can";
1439 reg = <0x00 0x02781000 0x00 0x200>,
1440 <0x00 0x02788000 0x00 0x8000>;
1441 reg-names = "m_can", "message_ram";
1442 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1443 clocks = <&k3_clks 190 0>, <&k3_clks 190 1>;
1444 clock-names = "hclk", "cclk";
1445 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
1447 interrupt-names = "int0", "int1";
1448 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1449 status = "disabled";
1450 };
1451
1452 main_mcan9: can@2791000 {
1453 compatible = "bosch,m_can";
1454 reg = <0x00 0x02791000 0x00 0x200>,
1455 <0x00 0x02798000 0x00 0x8000>;
1456 reg-names = "m_can", "message_ram";
1457 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1458 clocks = <&k3_clks 191 0>, <&k3_clks 191 1>;
1459 clock-names = "hclk", "cclk";
1460 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
1461 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
1462 interrupt-names = "int0", "int1";
1463 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1464 status = "disabled";
1465 };
1466
1467 main_mcan10: can@27a1000 {
1468 compatible = "bosch,m_can";
1469 reg = <0x00 0x027a1000 0x00 0x200>,
1470 <0x00 0x027a8000 0x00 0x8000>;
1471 reg-names = "m_can", "message_ram";
1472 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1473 clocks = <&k3_clks 192 0>, <&k3_clks 192 1>;
1474 clock-names = "hclk", "cclk";
1475 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
1476 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1477 interrupt-names = "int0", "int1";
1478 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1479 status = "disabled";
1480 };
1481
1482 main_mcan11: can@27b1000 {
1483 compatible = "bosch,m_can";
1484 reg = <0x00 0x027b1000 0x00 0x200>,
1485 <0x00 0x027b8000 0x00 0x8000>;
1486 reg-names = "m_can", "message_ram";
1487 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1488 clocks = <&k3_clks 193 0>, <&k3_clks 193 1>;
1489 clock-names = "hclk", "cclk";
1490 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
1491 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1492 interrupt-names = "int0", "int1";
1493 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1494 status = "disabled";
1495 };
1496
1497 main_mcan12: can@27c1000 {
1498 compatible = "bosch,m_can";
1499 reg = <0x00 0x027c1000 0x00 0x200>,
1500 <0x00 0x027c8000 0x00 0x8000>;
1501 reg-names = "m_can", "message_ram";
1502 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
1503 clocks = <&k3_clks 194 0>, <&k3_clks 194 1>;
1504 clock-names = "hclk", "cclk";
1505 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1506 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
1507 interrupt-names = "int0", "int1";
1508 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1509 status = "disabled";
1510 };
1511
1512 main_mcan13: can@27d1000 {
1513 compatible = "bosch,m_can";
1514 reg = <0x00 0x027d1000 0x00 0x200>,
1515 <0x00 0x027d8000 0x00 0x8000>;
1516 reg-names = "m_can", "message_ram";
1517 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
1518 clocks = <&k3_clks 195 0>, <&k3_clks 195 1>;
1519 clock-names = "hclk", "cclk";
1520 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1521 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
1522 interrupt-names = "int0", "int1";
1523 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1524 status = "disabled";
1525 };
1526
1527 main_mcan14: can@2681000 {
1528 compatible = "bosch,m_can";
1529 reg = <0x00 0x02681000 0x00 0x200>,
1530 <0x00 0x02688000 0x00 0x8000>;
1531 reg-names = "m_can", "message_ram";
1532 power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
1533 clocks = <&k3_clks 197 0>, <&k3_clks 197 1>;
1534 clock-names = "hclk", "cclk";
1535 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
1537 interrupt-names = "int0", "int1";
1538 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1539 status = "disabled";
1540 };
1541
1542 main_mcan15: can@2691000 {
1543 compatible = "bosch,m_can";
1544 reg = <0x00 0x02691000 0x00 0x200>,
1545 <0x00 0x02698000 0x00 0x8000>;
1546 reg-names = "m_can", "message_ram";
1547 power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>;
1548 clocks = <&k3_clks 199 0>, <&k3_clks 199 1>;
1549 clock-names = "hclk", "cclk";
1550 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1551 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
1552 interrupt-names = "int0", "int1";
1553 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1554 status = "disabled";
1555 };
1556
1557 main_mcan16: can@26a1000 {
1558 compatible = "bosch,m_can";
1559 reg = <0x00 0x026a1000 0x00 0x200>,
1560 <0x00 0x026a8000 0x00 0x8000>;
1561 reg-names = "m_can", "message_ram";
1562 power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
1563 clocks = <&k3_clks 201 0>, <&k3_clks 201 1>;
1564 clock-names = "hclk", "cclk";
1565 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
1566 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
1567 interrupt-names = "int0", "int1";
1568 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1569 status = "disabled";
1570 };
1571
1572 main_mcan17: can@26b1000 {
1573 compatible = "bosch,m_can";
1574 reg = <0x00 0x026b1000 0x00 0x200>,
1575 <0x00 0x026b8000 0x00 0x8000>;
1576 reg-names = "m_can", "message_ram";
1577 power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>;
1578 clocks = <&k3_clks 206 0>, <&k3_clks 206 1>;
1579 clock-names = "hclk", "cclk";
1580 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
1581 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
1582 interrupt-names = "int0", "int1";
1583 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
1584 status = "disabled";
1585 };
1586
1587 main_spi0: spi@2100000 {
1588 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1589 reg = <0x00 0x02100000 0x00 0x400>;
1590 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1591 #address-cells = <1>;
1592 #size-cells = <0>;
1593 power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>;
1594 clocks = <&k3_clks 339 1>;
1595 status = "disabled";
1596 };
1597
1598 main_spi1: spi@2110000 {
1599 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1600 reg = <0x00 0x02110000 0x00 0x400>;
1601 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
1602 #address-cells = <1>;
1603 #size-cells = <0>;
1604 power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>;
1605 clocks = <&k3_clks 340 1>;
1606 status = "disabled";
1607 };
1608
1609 main_spi2: spi@2120000 {
1610 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1611 reg = <0x00 0x02120000 0x00 0x400>;
1612 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1613 #address-cells = <1>;
1614 #size-cells = <0>;
1615 power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>;
1616 clocks = <&k3_clks 341 1>;
1617 status = "disabled";
1618 };
1619
1620 main_spi3: spi@2130000 {
1621 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1622 reg = <0x00 0x02130000 0x00 0x400>;
1623 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1624 #address-cells = <1>;
1625 #size-cells = <0>;
1626 power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>;
1627 clocks = <&k3_clks 342 1>;
1628 status = "disabled";
1629 };
1630
1631 main_spi4: spi@2140000 {
1632 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1633 reg = <0x00 0x02140000 0x00 0x400>;
1634 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1635 #address-cells = <1>;
1636 #size-cells = <0>;
1637 power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>;
1638 clocks = <&k3_clks 343 1>;
1639 status = "disabled";
1640 };
1641
1642 main_spi5: spi@2150000 {
1643 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1644 reg = <0x00 0x02150000 0x00 0x400>;
1645 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1646 #address-cells = <1>;
1647 #size-cells = <0>;
1648 power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>;
1649 clocks = <&k3_clks 344 1>;
1650 status = "disabled";
1651 };
1652
1653 main_spi6: spi@2160000 {
1654 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1655 reg = <0x00 0x02160000 0x00 0x400>;
1656 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1657 #address-cells = <1>;
1658 #size-cells = <0>;
1659 power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
1660 clocks = <&k3_clks 345 1>;
1661 status = "disabled";
1662 };
1663
1664 main_spi7: spi@2170000 {
1665 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1666 reg = <0x00 0x02170000 0x00 0x400>;
1667 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1668 #address-cells = <1>;
1669 #size-cells = <0>;
1670 power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>;
1671 clocks = <&k3_clks 346 1>;
1672 status = "disabled";
1673 };
1674
1675 dss: dss@4a00000 {
1676 compatible = "ti,j721e-dss";
1677 reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1678 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1679 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1680 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1681 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1682 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1683 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1684 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1685 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1686 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1687 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1688 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1689 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1690 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1691 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1692 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1693 <0x00 0x04af0000 0x00 0x10000>; /* wb */
1694 reg-names = "common_m", "common_s0",
1695 "common_s1", "common_s2",
1696 "vidl1", "vidl2","vid1","vid2",
1697 "ovr1", "ovr2", "ovr3", "ovr4",
1698 "vp1", "vp2", "vp3", "vp4",
1699 "wb";
1700 clocks = <&k3_clks 158 0>,
1701 <&k3_clks 158 2>,
1702 <&k3_clks 158 5>,
1703 <&k3_clks 158 14>,
1704 <&k3_clks 158 18>;
1705 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1706 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
1707 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
1708 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
1709 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
1710 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1711 interrupt-names = "common_m",
1712 "common_s0",
1713 "common_s1",
1714 "common_s2";
1715 status = "disabled";
1716
1717 dss_ports: ports {
1718 };
1719 };
1720
1721 main_r5fss0: r5fss@5c00000 {
1722 compatible = "ti,j721s2-r5fss";
1723 ti,cluster-mode = <1>;
1724 #address-cells = <1>;
1725 #size-cells = <1>;
1726 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
1727 <0x5d00000 0x00 0x5d00000 0x20000>;
1728 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1729
1730 main_r5fss0_core0: r5f@5c00000 {
1731 compatible = "ti,j721s2-r5f";
1732 reg = <0x5c00000 0x00010000>,
1733 <0x5c10000 0x00010000>;
1734 reg-names = "atcm", "btcm";
1735 ti,sci = <&sms>;
1736 ti,sci-dev-id = <279>;
1737 ti,sci-proc-ids = <0x06 0xff>;
1738 resets = <&k3_reset 279 1>;
1739 firmware-name = "j721s2-main-r5f0_0-fw";
1740 ti,atcm-enable = <1>;
1741 ti,btcm-enable = <1>;
1742 ti,loczrama = <1>;
1743 };
1744
1745 main_r5fss0_core1: r5f@5d00000 {
1746 compatible = "ti,j721s2-r5f";
1747 reg = <0x5d00000 0x00010000>,
1748 <0x5d10000 0x00010000>;
1749 reg-names = "atcm", "btcm";
1750 ti,sci = <&sms>;
1751 ti,sci-dev-id = <280>;
1752 ti,sci-proc-ids = <0x07 0xff>;
1753 resets = <&k3_reset 280 1>;
1754 firmware-name = "j721s2-main-r5f0_1-fw";
1755 ti,atcm-enable = <1>;
1756 ti,btcm-enable = <1>;
1757 ti,loczrama = <1>;
1758 };
1759 };
1760
1761 main_r5fss1: r5fss@5e00000 {
1762 compatible = "ti,j721s2-r5fss";
1763 ti,cluster-mode = <1>;
1764 #address-cells = <1>;
1765 #size-cells = <1>;
1766 ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
1767 <0x5f00000 0x00 0x5f00000 0x20000>;
1768 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
1769
1770 main_r5fss1_core0: r5f@5e00000 {
1771 compatible = "ti,j721s2-r5f";
1772 reg = <0x5e00000 0x00010000>,
1773 <0x5e10000 0x00010000>;
1774 reg-names = "atcm", "btcm";
1775 ti,sci = <&sms>;
1776 ti,sci-dev-id = <281>;
1777 ti,sci-proc-ids = <0x08 0xff>;
1778 resets = <&k3_reset 281 1>;
1779 firmware-name = "j721s2-main-r5f1_0-fw";
1780 ti,atcm-enable = <1>;
1781 ti,btcm-enable = <1>;
1782 ti,loczrama = <1>;
1783 };
1784
1785 main_r5fss1_core1: r5f@5f00000 {
1786 compatible = "ti,j721s2-r5f";
1787 reg = <0x5f00000 0x00010000>,
1788 <0x5f10000 0x00010000>;
1789 reg-names = "atcm", "btcm";
1790 ti,sci = <&sms>;
1791 ti,sci-dev-id = <282>;
1792 ti,sci-proc-ids = <0x09 0xff>;
1793 resets = <&k3_reset 282 1>;
1794 firmware-name = "j721s2-main-r5f1_1-fw";
1795 ti,atcm-enable = <1>;
1796 ti,btcm-enable = <1>;
1797 ti,loczrama = <1>;
1798 };
1799 };
1800
1801 c71_0: dsp@64800000 {
1802 compatible = "ti,j721s2-c71-dsp";
1803 reg = <0x00 0x64800000 0x00 0x00080000>,
1804 <0x00 0x64e00000 0x00 0x0000c000>;
1805 reg-names = "l2sram", "l1dram";
1806 ti,sci = <&sms>;
1807 ti,sci-dev-id = <8>;
1808 ti,sci-proc-ids = <0x30 0xff>;
1809 resets = <&k3_reset 8 1>;
1810 firmware-name = "j721s2-c71_0-fw";
1811 status = "disabled";
1812 };
1813
1814 c71_1: dsp@65800000 {
1815 compatible = "ti,j721s2-c71-dsp";
1816 reg = <0x00 0x65800000 0x00 0x00080000>,
1817 <0x00 0x65e00000 0x00 0x0000c000>;
1818 reg-names = "l2sram", "l1dram";
1819 ti,sci = <&sms>;
1820 ti,sci-dev-id = <11>;
1821 ti,sci-proc-ids = <0x31 0xff>;
1822 resets = <&k3_reset 11 1>;
1823 firmware-name = "j721s2-c71_1-fw";
1824 status = "disabled";
1825 };
1826
1827 main_esm: esm@700000 {
1828 compatible = "ti,j721e-esm";
1829 reg = <0x00 0x700000 0x00 0x1000>;
1830 ti,esm-pins = <688>, <689>;
1831 bootph-pre-ram;
1832 };
1833
1834 watchdog0: watchdog@2200000 {
1835 compatible = "ti,j7-rti-wdt";
1836 reg = <0x00 0x2200000 0x00 0x100>;
1837 clocks = <&k3_clks 286 1>;
1838 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
1839 assigned-clocks = <&k3_clks 286 1>;
1840 assigned-clock-parents = <&k3_clks 286 5>;
1841 };
1842
1843 watchdog1: watchdog@2210000 {
1844 compatible = "ti,j7-rti-wdt";
1845 reg = <0x00 0x2210000 0x00 0x100>;
1846 clocks = <&k3_clks 287 1>;
1847 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
1848 assigned-clocks = <&k3_clks 287 1>;
1849 assigned-clock-parents = <&k3_clks 287 5>;
1850 };
1851
1852 /*
1853 * The following RTI instances are coupled with MCU R5Fs, c7x and
1854 * GPU so keeping them reserved as these will be used by their
1855 * respective firmware
1856 */
1857 watchdog2: watchdog@22f0000 {
1858 compatible = "ti,j7-rti-wdt";
1859 reg = <0x00 0x22f0000 0x00 0x100>;
1860 clocks = <&k3_clks 290 1>;
1861 power-domains = <&k3_pds 290 TI_SCI_PD_EXCLUSIVE>;
1862 assigned-clocks = <&k3_clks 290 1>;
1863 assigned-clock-parents = <&k3_clks 290 5>;
1864 /* reserved for GPU */
1865 status = "reserved";
1866 };
1867
1868 watchdog3: watchdog@2300000 {
1869 compatible = "ti,j7-rti-wdt";
1870 reg = <0x00 0x2300000 0x00 0x100>;
1871 clocks = <&k3_clks 288 1>;
1872 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1873 assigned-clocks = <&k3_clks 288 1>;
1874 assigned-clock-parents = <&k3_clks 288 5>;
1875 /* reserved for C7X_0 */
1876 status = "reserved";
1877 };
1878
1879 watchdog4: watchdog@2310000 {
1880 compatible = "ti,j7-rti-wdt";
1881 reg = <0x00 0x2310000 0x00 0x100>;
1882 clocks = <&k3_clks 289 1>;
1883 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
1884 assigned-clocks = <&k3_clks 289 1>;
1885 assigned-clock-parents = <&k3_clks 289 5>;
1886 /* reserved for C7X_1 */
1887 status = "reserved";
1888 };
1889
1890 watchdog5: watchdog@23c0000 {
1891 compatible = "ti,j7-rti-wdt";
1892 reg = <0x00 0x23c0000 0x00 0x100>;
1893 clocks = <&k3_clks 291 1>;
1894 power-domains = <&k3_pds 291 TI_SCI_PD_EXCLUSIVE>;
1895 assigned-clocks = <&k3_clks 291 1>;
1896 assigned-clock-parents = <&k3_clks 291 5>;
1897 /* reserved for MAIN_R5F0_0 */
1898 status = "reserved";
1899 };
1900
1901 watchdog6: watchdog@23d0000 {
1902 compatible = "ti,j7-rti-wdt";
1903 reg = <0x00 0x23d0000 0x00 0x100>;
1904 clocks = <&k3_clks 292 1>;
1905 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
1906 assigned-clocks = <&k3_clks 292 1>;
1907 assigned-clock-parents = <&k3_clks 292 5>;
1908 /* reserved for MAIN_R5F0_1 */
1909 status = "reserved";
1910 };
1911
1912 watchdog7: watchdog@23e0000 {
1913 compatible = "ti,j7-rti-wdt";
1914 reg = <0x00 0x23e0000 0x00 0x100>;
1915 clocks = <&k3_clks 293 1>;
1916 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
1917 assigned-clocks = <&k3_clks 293 1>;
1918 assigned-clock-parents = <&k3_clks 293 5>;
1919 /* reserved for MAIN_R5F1_0 */
1920 status = "reserved";
1921 };
1922
1923 watchdog8: watchdog@23f0000 {
1924 compatible = "ti,j7-rti-wdt";
1925 reg = <0x00 0x23f0000 0x00 0x100>;
1926 clocks = <&k3_clks 294 1>;
1927 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
1928 assigned-clocks = <&k3_clks 294 1>;
1929 assigned-clock-parents = <&k3_clks 294 5>;
1930 /* reserved for MAIN_R5F1_1 */
1931 status = "reserved";
1932 };
1933 };
"Das U-Boot" Source Tree