1 /****************************************************************************
3 * Realmode X86 Emulator Library
5 * Copyright (C) 1996-1999 SciTech Software, Inc.
6 * Copyright (C) David Mosberger-Tang
7 * Copyright (C) 1999 Egbert Eich
9 * ========================================================================
11 * Permission to use, copy, modify, distribute, and sell this software and
12 * its documentation for any purpose is hereby granted without fee,
13 * provided that the above copyright notice appear in all copies and that
14 * both that copyright notice and this permission notice appear in
15 * supporting documentation, and that the name of the authors not be used
16 * in advertising or publicity pertaining to distribution of the software
17 * without specific, written prior permission. The authors makes no
18 * representations about the suitability of this software for any purpose.
19 * It is provided "as is" without express or implied warranty.
21 * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
22 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
23 * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
24 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
25 * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
26 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
27 * PERFORMANCE OF THIS SOFTWARE.
29 * ========================================================================
33 * Developer: Kendall Bennett
35 * Description: This file includes subroutines to implement the decoding
36 * and emulation of all the x86 extended two-byte processor
39 ****************************************************************************/
40 /* $XFree86: xc/extras/x86emu/src/x86emu/ops2.c,v 1.6tsi Exp $ */
42 #include "x86emu/x86emui.h"
44 /*----------------------------- Implementation ----------------------------*/
46 /****************************************************************************
48 op1 - Instruction op code
51 Handles illegal opcodes.
52 ****************************************************************************/
53 static void x86emuOp2_illegal_op(
57 DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
59 printk("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n",
60 M
.x86
.R_CS
, M
.x86
.R_IP
-2,op2
);
65 #define xorl(a,b) ((a) && !(b)) || (!(a) && (b))
67 /****************************************************************************
69 Handles opcode 0x0f,0x80-0x8F
70 ****************************************************************************/
71 static void x86emuOp2_long_jump(u8 op2
)
77 /* conditional jump to word offset. */
82 cond
= ACCESS_FLAG(F_OF
);
86 cond
= !ACCESS_FLAG(F_OF
);
90 cond
= ACCESS_FLAG(F_CF
);
94 cond
= !ACCESS_FLAG(F_CF
);
98 cond
= ACCESS_FLAG(F_ZF
);
102 cond
= !ACCESS_FLAG(F_ZF
);
106 cond
= ACCESS_FLAG(F_CF
) || ACCESS_FLAG(F_ZF
);
110 cond
= !(ACCESS_FLAG(F_CF
) || ACCESS_FLAG(F_ZF
));
114 cond
= ACCESS_FLAG(F_SF
);
118 cond
= !ACCESS_FLAG(F_SF
);
122 cond
= ACCESS_FLAG(F_PF
);
126 cond
= !ACCESS_FLAG(F_PF
);
130 cond
= xorl(ACCESS_FLAG(F_SF
), ACCESS_FLAG(F_OF
));
134 cond
= xorl(ACCESS_FLAG(F_SF
), ACCESS_FLAG(F_OF
));
138 cond
= (xorl(ACCESS_FLAG(F_SF
), ACCESS_FLAG(F_OF
)) ||
143 cond
= !(xorl(ACCESS_FLAG(F_SF
), ACCESS_FLAG(F_OF
)) ||
149 target
= (s16
) fetch_word_imm();
150 target
+= (s16
) M
.x86
.R_IP
;
151 DECODE_PRINTF2("%04x\n", target
);
154 M
.x86
.R_IP
= (u16
)target
;
155 DECODE_CLEAR_SEGOVR();
159 /****************************************************************************
161 Handles opcode 0x0f,0x90-0x9F
162 ****************************************************************************/
163 static void x86emuOp2_set_byte(u8 op2
)
175 cond
= ACCESS_FLAG(F_OF
);
179 cond
= !ACCESS_FLAG(F_OF
);
183 cond
= ACCESS_FLAG(F_CF
);
187 cond
= !ACCESS_FLAG(F_CF
);
191 cond
= ACCESS_FLAG(F_ZF
);
195 cond
= !ACCESS_FLAG(F_ZF
);
199 cond
= ACCESS_FLAG(F_CF
) || ACCESS_FLAG(F_ZF
);
203 cond
= !(ACCESS_FLAG(F_CF
) || ACCESS_FLAG(F_ZF
));
207 cond
= ACCESS_FLAG(F_SF
);
211 cond
= !ACCESS_FLAG(F_SF
);
215 cond
= ACCESS_FLAG(F_PF
);
219 cond
= !ACCESS_FLAG(F_PF
);
223 cond
= xorl(ACCESS_FLAG(F_SF
), ACCESS_FLAG(F_OF
));
227 cond
= xorl(ACCESS_FLAG(F_SF
), ACCESS_FLAG(F_OF
));
231 cond
= (xorl(ACCESS_FLAG(F_SF
), ACCESS_FLAG(F_OF
)) ||
236 cond
= !(xorl(ACCESS_FLAG(F_SF
), ACCESS_FLAG(F_OF
)) ||
242 FETCH_DECODE_MODRM(mod
, rh
, rl
);
245 destoffset
= decode_rm00_address(rl
);
247 store_data_byte(destoffset
, cond
? 0x01 : 0x00);
250 destoffset
= decode_rm01_address(rl
);
252 store_data_byte(destoffset
, cond
? 0x01 : 0x00);
255 destoffset
= decode_rm10_address(rl
);
257 store_data_byte(destoffset
, cond
? 0x01 : 0x00);
259 case 3: /* register to register */
260 destreg
= DECODE_RM_BYTE_REGISTER(rl
);
262 *destreg
= cond
? 0x01 : 0x00;
265 DECODE_CLEAR_SEGOVR();
269 /****************************************************************************
271 Handles opcode 0x0f,0xa0
272 ****************************************************************************/
273 static void x86emuOp2_push_FS(u8
X86EMU_UNUSED(op2
))
276 DECODE_PRINTF("PUSH\tFS\n");
278 push_word(M
.x86
.R_FS
);
279 DECODE_CLEAR_SEGOVR();
283 /****************************************************************************
285 Handles opcode 0x0f,0xa1
286 ****************************************************************************/
287 static void x86emuOp2_pop_FS(u8
X86EMU_UNUSED(op2
))
290 DECODE_PRINTF("POP\tFS\n");
292 M
.x86
.R_FS
= pop_word();
293 DECODE_CLEAR_SEGOVR();
297 /****************************************************************************
299 Handles opcode 0x0f,0xa3
300 ****************************************************************************/
301 static void x86emuOp2_bt_R(u8
X86EMU_UNUSED(op2
))
308 DECODE_PRINTF("BT\t");
309 FETCH_DECODE_MODRM(mod
, rh
, rl
);
312 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
316 srcoffset
= decode_rm00_address(rl
);
318 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
320 bit
= *shiftreg
& 0x1F;
321 disp
= (s16
)*shiftreg
>> 5;
322 srcval
= fetch_data_long(srcoffset
+disp
);
323 CONDITIONAL_SET_FLAG(srcval
& (0x1 << bit
),F_CF
);
328 srcoffset
= decode_rm00_address(rl
);
330 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
332 bit
= *shiftreg
& 0xF;
333 disp
= (s16
)*shiftreg
>> 4;
334 srcval
= fetch_data_word(srcoffset
+disp
);
335 CONDITIONAL_SET_FLAG(srcval
& (0x1 << bit
),F_CF
);
339 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
343 srcoffset
= decode_rm01_address(rl
);
345 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
347 bit
= *shiftreg
& 0x1F;
348 disp
= (s16
)*shiftreg
>> 5;
349 srcval
= fetch_data_long(srcoffset
+disp
);
350 CONDITIONAL_SET_FLAG(srcval
& (0x1 << bit
),F_CF
);
355 srcoffset
= decode_rm01_address(rl
);
357 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
359 bit
= *shiftreg
& 0xF;
360 disp
= (s16
)*shiftreg
>> 4;
361 srcval
= fetch_data_word(srcoffset
+disp
);
362 CONDITIONAL_SET_FLAG(srcval
& (0x1 << bit
),F_CF
);
366 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
370 srcoffset
= decode_rm10_address(rl
);
372 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
374 bit
= *shiftreg
& 0x1F;
375 disp
= (s16
)*shiftreg
>> 5;
376 srcval
= fetch_data_long(srcoffset
+disp
);
377 CONDITIONAL_SET_FLAG(srcval
& (0x1 << bit
),F_CF
);
382 srcoffset
= decode_rm10_address(rl
);
384 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
386 bit
= *shiftreg
& 0xF;
387 disp
= (s16
)*shiftreg
>> 4;
388 srcval
= fetch_data_word(srcoffset
+disp
);
389 CONDITIONAL_SET_FLAG(srcval
& (0x1 << bit
),F_CF
);
392 case 3: /* register to register */
393 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
394 u32
*srcreg
,*shiftreg
;
396 srcreg
= DECODE_RM_LONG_REGISTER(rl
);
398 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
400 bit
= *shiftreg
& 0x1F;
401 CONDITIONAL_SET_FLAG(*srcreg
& (0x1 << bit
),F_CF
);
403 u16
*srcreg
,*shiftreg
;
405 srcreg
= DECODE_RM_WORD_REGISTER(rl
);
407 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
409 bit
= *shiftreg
& 0xF;
410 CONDITIONAL_SET_FLAG(*srcreg
& (0x1 << bit
),F_CF
);
414 DECODE_CLEAR_SEGOVR();
418 /****************************************************************************
420 Handles opcode 0x0f,0xa4
421 ****************************************************************************/
422 static void x86emuOp2_shld_IMM(u8
X86EMU_UNUSED(op2
))
429 DECODE_PRINTF("SHLD\t");
430 FETCH_DECODE_MODRM(mod
, rh
, rl
);
433 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
437 destoffset
= decode_rm00_address(rl
);
439 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
441 shift
= fetch_byte_imm();
442 DECODE_PRINTF2("%d\n", shift
);
444 destval
= fetch_data_long(destoffset
);
445 destval
= shld_long(destval
,*shiftreg
,shift
);
446 store_data_long(destoffset
, destval
);
451 destoffset
= decode_rm00_address(rl
);
453 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
455 shift
= fetch_byte_imm();
456 DECODE_PRINTF2("%d\n", shift
);
458 destval
= fetch_data_word(destoffset
);
459 destval
= shld_word(destval
,*shiftreg
,shift
);
460 store_data_word(destoffset
, destval
);
464 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
468 destoffset
= decode_rm01_address(rl
);
470 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
472 shift
= fetch_byte_imm();
473 DECODE_PRINTF2("%d\n", shift
);
475 destval
= fetch_data_long(destoffset
);
476 destval
= shld_long(destval
,*shiftreg
,shift
);
477 store_data_long(destoffset
, destval
);
482 destoffset
= decode_rm01_address(rl
);
484 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
486 shift
= fetch_byte_imm();
487 DECODE_PRINTF2("%d\n", shift
);
489 destval
= fetch_data_word(destoffset
);
490 destval
= shld_word(destval
,*shiftreg
,shift
);
491 store_data_word(destoffset
, destval
);
495 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
499 destoffset
= decode_rm10_address(rl
);
501 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
503 shift
= fetch_byte_imm();
504 DECODE_PRINTF2("%d\n", shift
);
506 destval
= fetch_data_long(destoffset
);
507 destval
= shld_long(destval
,*shiftreg
,shift
);
508 store_data_long(destoffset
, destval
);
513 destoffset
= decode_rm10_address(rl
);
515 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
517 shift
= fetch_byte_imm();
518 DECODE_PRINTF2("%d\n", shift
);
520 destval
= fetch_data_word(destoffset
);
521 destval
= shld_word(destval
,*shiftreg
,shift
);
522 store_data_word(destoffset
, destval
);
525 case 3: /* register to register */
526 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
527 u32
*destreg
,*shiftreg
;
529 destreg
= DECODE_RM_LONG_REGISTER(rl
);
531 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
533 shift
= fetch_byte_imm();
534 DECODE_PRINTF2("%d\n", shift
);
536 *destreg
= shld_long(*destreg
,*shiftreg
,shift
);
538 u16
*destreg
,*shiftreg
;
540 destreg
= DECODE_RM_WORD_REGISTER(rl
);
542 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
544 shift
= fetch_byte_imm();
545 DECODE_PRINTF2("%d\n", shift
);
547 *destreg
= shld_word(*destreg
,*shiftreg
,shift
);
551 DECODE_CLEAR_SEGOVR();
555 /****************************************************************************
557 Handles opcode 0x0f,0xa5
558 ****************************************************************************/
559 static void x86emuOp2_shld_CL(u8
X86EMU_UNUSED(op2
))
565 DECODE_PRINTF("SHLD\t");
566 FETCH_DECODE_MODRM(mod
, rh
, rl
);
569 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
573 destoffset
= decode_rm00_address(rl
);
575 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
576 DECODE_PRINTF(",CL\n");
578 destval
= fetch_data_long(destoffset
);
579 destval
= shld_long(destval
,*shiftreg
,M
.x86
.R_CL
);
580 store_data_long(destoffset
, destval
);
585 destoffset
= decode_rm00_address(rl
);
587 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
588 DECODE_PRINTF(",CL\n");
590 destval
= fetch_data_word(destoffset
);
591 destval
= shld_word(destval
,*shiftreg
,M
.x86
.R_CL
);
592 store_data_word(destoffset
, destval
);
596 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
600 destoffset
= decode_rm01_address(rl
);
602 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
603 DECODE_PRINTF(",CL\n");
605 destval
= fetch_data_long(destoffset
);
606 destval
= shld_long(destval
,*shiftreg
,M
.x86
.R_CL
);
607 store_data_long(destoffset
, destval
);
612 destoffset
= decode_rm01_address(rl
);
614 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
615 DECODE_PRINTF(",CL\n");
617 destval
= fetch_data_word(destoffset
);
618 destval
= shld_word(destval
,*shiftreg
,M
.x86
.R_CL
);
619 store_data_word(destoffset
, destval
);
623 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
627 destoffset
= decode_rm10_address(rl
);
629 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
630 DECODE_PRINTF(",CL\n");
632 destval
= fetch_data_long(destoffset
);
633 destval
= shld_long(destval
,*shiftreg
,M
.x86
.R_CL
);
634 store_data_long(destoffset
, destval
);
639 destoffset
= decode_rm10_address(rl
);
641 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
642 DECODE_PRINTF(",CL\n");
644 destval
= fetch_data_word(destoffset
);
645 destval
= shld_word(destval
,*shiftreg
,M
.x86
.R_CL
);
646 store_data_word(destoffset
, destval
);
649 case 3: /* register to register */
650 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
651 u32
*destreg
,*shiftreg
;
653 destreg
= DECODE_RM_LONG_REGISTER(rl
);
655 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
656 DECODE_PRINTF(",CL\n");
658 *destreg
= shld_long(*destreg
,*shiftreg
,M
.x86
.R_CL
);
660 u16
*destreg
,*shiftreg
;
662 destreg
= DECODE_RM_WORD_REGISTER(rl
);
664 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
665 DECODE_PRINTF(",CL\n");
667 *destreg
= shld_word(*destreg
,*shiftreg
,M
.x86
.R_CL
);
671 DECODE_CLEAR_SEGOVR();
675 /****************************************************************************
677 Handles opcode 0x0f,0xa8
678 ****************************************************************************/
679 static void x86emuOp2_push_GS(u8
X86EMU_UNUSED(op2
))
682 DECODE_PRINTF("PUSH\tGS\n");
684 push_word(M
.x86
.R_GS
);
685 DECODE_CLEAR_SEGOVR();
689 /****************************************************************************
691 Handles opcode 0x0f,0xa9
692 ****************************************************************************/
693 static void x86emuOp2_pop_GS(u8
X86EMU_UNUSED(op2
))
696 DECODE_PRINTF("POP\tGS\n");
698 M
.x86
.R_GS
= pop_word();
699 DECODE_CLEAR_SEGOVR();
704 /****************************************************************************
706 Handles opcode 0x0f,0xaa
707 ****************************************************************************/
708 static void x86emuOp2_bts_R(u8
X86EMU_UNUSED(op2
))
715 DECODE_PRINTF("BTS\t");
716 FETCH_DECODE_MODRM(mod
, rh
, rl
);
719 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
723 srcoffset
= decode_rm00_address(rl
);
725 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
727 bit
= *shiftreg
& 0x1F;
728 disp
= (s16
)*shiftreg
>> 5;
729 srcval
= fetch_data_long(srcoffset
+disp
);
731 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
732 store_data_long(srcoffset
+disp
, srcval
| mask
);
737 srcoffset
= decode_rm00_address(rl
);
739 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
741 bit
= *shiftreg
& 0xF;
742 disp
= (s16
)*shiftreg
>> 4;
743 srcval
= fetch_data_word(srcoffset
+disp
);
744 mask
= (u16
)(0x1 << bit
);
745 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
746 store_data_word(srcoffset
+disp
, srcval
| mask
);
750 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
754 srcoffset
= decode_rm01_address(rl
);
756 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
758 bit
= *shiftreg
& 0x1F;
759 disp
= (s16
)*shiftreg
>> 5;
760 srcval
= fetch_data_long(srcoffset
+disp
);
762 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
763 store_data_long(srcoffset
+disp
, srcval
| mask
);
768 srcoffset
= decode_rm01_address(rl
);
770 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
772 bit
= *shiftreg
& 0xF;
773 disp
= (s16
)*shiftreg
>> 4;
774 srcval
= fetch_data_word(srcoffset
+disp
);
775 mask
= (u16
)(0x1 << bit
);
776 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
777 store_data_word(srcoffset
+disp
, srcval
| mask
);
781 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
785 srcoffset
= decode_rm10_address(rl
);
787 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
789 bit
= *shiftreg
& 0x1F;
790 disp
= (s16
)*shiftreg
>> 5;
791 srcval
= fetch_data_long(srcoffset
+disp
);
793 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
794 store_data_long(srcoffset
+disp
, srcval
| mask
);
799 srcoffset
= decode_rm10_address(rl
);
801 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
803 bit
= *shiftreg
& 0xF;
804 disp
= (s16
)*shiftreg
>> 4;
805 srcval
= fetch_data_word(srcoffset
+disp
);
806 mask
= (u16
)(0x1 << bit
);
807 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
808 store_data_word(srcoffset
+disp
, srcval
| mask
);
811 case 3: /* register to register */
812 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
813 u32
*srcreg
,*shiftreg
;
816 srcreg
= DECODE_RM_LONG_REGISTER(rl
);
818 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
820 bit
= *shiftreg
& 0x1F;
822 CONDITIONAL_SET_FLAG(*srcreg
& mask
,F_CF
);
825 u16
*srcreg
,*shiftreg
;
828 srcreg
= DECODE_RM_WORD_REGISTER(rl
);
830 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
832 bit
= *shiftreg
& 0xF;
833 mask
= (u16
)(0x1 << bit
);
834 CONDITIONAL_SET_FLAG(*srcreg
& mask
,F_CF
);
839 DECODE_CLEAR_SEGOVR();
844 /****************************************************************************
846 Handles opcode 0x0f,0xac
847 ****************************************************************************/
848 static void x86emuOp2_shrd_IMM(u8
X86EMU_UNUSED(op2
))
855 DECODE_PRINTF("SHLD\t");
856 FETCH_DECODE_MODRM(mod
, rh
, rl
);
859 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
863 destoffset
= decode_rm00_address(rl
);
865 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
867 shift
= fetch_byte_imm();
868 DECODE_PRINTF2("%d\n", shift
);
870 destval
= fetch_data_long(destoffset
);
871 destval
= shrd_long(destval
,*shiftreg
,shift
);
872 store_data_long(destoffset
, destval
);
877 destoffset
= decode_rm00_address(rl
);
879 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
881 shift
= fetch_byte_imm();
882 DECODE_PRINTF2("%d\n", shift
);
884 destval
= fetch_data_word(destoffset
);
885 destval
= shrd_word(destval
,*shiftreg
,shift
);
886 store_data_word(destoffset
, destval
);
890 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
894 destoffset
= decode_rm01_address(rl
);
896 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
898 shift
= fetch_byte_imm();
899 DECODE_PRINTF2("%d\n", shift
);
901 destval
= fetch_data_long(destoffset
);
902 destval
= shrd_long(destval
,*shiftreg
,shift
);
903 store_data_long(destoffset
, destval
);
908 destoffset
= decode_rm01_address(rl
);
910 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
912 shift
= fetch_byte_imm();
913 DECODE_PRINTF2("%d\n", shift
);
915 destval
= fetch_data_word(destoffset
);
916 destval
= shrd_word(destval
,*shiftreg
,shift
);
917 store_data_word(destoffset
, destval
);
921 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
925 destoffset
= decode_rm10_address(rl
);
927 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
929 shift
= fetch_byte_imm();
930 DECODE_PRINTF2("%d\n", shift
);
932 destval
= fetch_data_long(destoffset
);
933 destval
= shrd_long(destval
,*shiftreg
,shift
);
934 store_data_long(destoffset
, destval
);
939 destoffset
= decode_rm10_address(rl
);
941 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
943 shift
= fetch_byte_imm();
944 DECODE_PRINTF2("%d\n", shift
);
946 destval
= fetch_data_word(destoffset
);
947 destval
= shrd_word(destval
,*shiftreg
,shift
);
948 store_data_word(destoffset
, destval
);
951 case 3: /* register to register */
952 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
953 u32
*destreg
,*shiftreg
;
955 destreg
= DECODE_RM_LONG_REGISTER(rl
);
957 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
959 shift
= fetch_byte_imm();
960 DECODE_PRINTF2("%d\n", shift
);
962 *destreg
= shrd_long(*destreg
,*shiftreg
,shift
);
964 u16
*destreg
,*shiftreg
;
966 destreg
= DECODE_RM_WORD_REGISTER(rl
);
968 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
970 shift
= fetch_byte_imm();
971 DECODE_PRINTF2("%d\n", shift
);
973 *destreg
= shrd_word(*destreg
,*shiftreg
,shift
);
977 DECODE_CLEAR_SEGOVR();
981 /****************************************************************************
983 Handles opcode 0x0f,0xad
984 ****************************************************************************/
985 static void x86emuOp2_shrd_CL(u8
X86EMU_UNUSED(op2
))
991 DECODE_PRINTF("SHLD\t");
992 FETCH_DECODE_MODRM(mod
, rh
, rl
);
995 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
999 destoffset
= decode_rm00_address(rl
);
1001 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
1002 DECODE_PRINTF(",CL\n");
1004 destval
= fetch_data_long(destoffset
);
1005 destval
= shrd_long(destval
,*shiftreg
,M
.x86
.R_CL
);
1006 store_data_long(destoffset
, destval
);
1011 destoffset
= decode_rm00_address(rl
);
1013 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
1014 DECODE_PRINTF(",CL\n");
1016 destval
= fetch_data_word(destoffset
);
1017 destval
= shrd_word(destval
,*shiftreg
,M
.x86
.R_CL
);
1018 store_data_word(destoffset
, destval
);
1022 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
1026 destoffset
= decode_rm01_address(rl
);
1028 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
1029 DECODE_PRINTF(",CL\n");
1031 destval
= fetch_data_long(destoffset
);
1032 destval
= shrd_long(destval
,*shiftreg
,M
.x86
.R_CL
);
1033 store_data_long(destoffset
, destval
);
1038 destoffset
= decode_rm01_address(rl
);
1040 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
1041 DECODE_PRINTF(",CL\n");
1043 destval
= fetch_data_word(destoffset
);
1044 destval
= shrd_word(destval
,*shiftreg
,M
.x86
.R_CL
);
1045 store_data_word(destoffset
, destval
);
1049 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
1053 destoffset
= decode_rm10_address(rl
);
1055 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
1056 DECODE_PRINTF(",CL\n");
1058 destval
= fetch_data_long(destoffset
);
1059 destval
= shrd_long(destval
,*shiftreg
,M
.x86
.R_CL
);
1060 store_data_long(destoffset
, destval
);
1065 destoffset
= decode_rm10_address(rl
);
1067 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
1068 DECODE_PRINTF(",CL\n");
1070 destval
= fetch_data_word(destoffset
);
1071 destval
= shrd_word(destval
,*shiftreg
,M
.x86
.R_CL
);
1072 store_data_word(destoffset
, destval
);
1075 case 3: /* register to register */
1076 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
1077 u32
*destreg
,*shiftreg
;
1079 destreg
= DECODE_RM_LONG_REGISTER(rl
);
1081 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
1082 DECODE_PRINTF(",CL\n");
1084 *destreg
= shrd_long(*destreg
,*shiftreg
,M
.x86
.R_CL
);
1086 u16
*destreg
,*shiftreg
;
1088 destreg
= DECODE_RM_WORD_REGISTER(rl
);
1090 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
1091 DECODE_PRINTF(",CL\n");
1093 *destreg
= shrd_word(*destreg
,*shiftreg
,M
.x86
.R_CL
);
1097 DECODE_CLEAR_SEGOVR();
1101 /****************************************************************************
1103 Handles opcode 0x0f,0xaf
1104 ****************************************************************************/
1105 static void x86emuOp2_imul_R_RM(u8
X86EMU_UNUSED(op2
))
1111 DECODE_PRINTF("IMUL\t");
1112 FETCH_DECODE_MODRM(mod
, rh
, rl
);
1115 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
1120 destreg
= DECODE_RM_LONG_REGISTER(rh
);
1122 srcoffset
= decode_rm00_address(rl
);
1123 srcval
= fetch_data_long(srcoffset
);
1125 imul_long_direct(&res_lo
,&res_hi
,(s32
)*destreg
,(s32
)srcval
);
1133 *destreg
= (u32
)res_lo
;
1139 destreg
= DECODE_RM_WORD_REGISTER(rh
);
1141 srcoffset
= decode_rm00_address(rl
);
1142 srcval
= fetch_data_word(srcoffset
);
1144 res
= (s16
)*destreg
* (s16
)srcval
;
1152 *destreg
= (u16
)res
;
1156 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
1161 destreg
= DECODE_RM_LONG_REGISTER(rh
);
1163 srcoffset
= decode_rm01_address(rl
);
1164 srcval
= fetch_data_long(srcoffset
);
1166 imul_long_direct(&res_lo
,&res_hi
,(s32
)*destreg
,(s32
)srcval
);
1174 *destreg
= (u32
)res_lo
;
1180 destreg
= DECODE_RM_WORD_REGISTER(rh
);
1182 srcoffset
= decode_rm01_address(rl
);
1183 srcval
= fetch_data_word(srcoffset
);
1185 res
= (s16
)*destreg
* (s16
)srcval
;
1193 *destreg
= (u16
)res
;
1197 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
1202 destreg
= DECODE_RM_LONG_REGISTER(rh
);
1204 srcoffset
= decode_rm10_address(rl
);
1205 srcval
= fetch_data_long(srcoffset
);
1207 imul_long_direct(&res_lo
,&res_hi
,(s32
)*destreg
,(s32
)srcval
);
1215 *destreg
= (u32
)res_lo
;
1221 destreg
= DECODE_RM_WORD_REGISTER(rh
);
1223 srcoffset
= decode_rm10_address(rl
);
1224 srcval
= fetch_data_word(srcoffset
);
1226 res
= (s16
)*destreg
* (s16
)srcval
;
1234 *destreg
= (u16
)res
;
1237 case 3: /* register to register */
1238 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
1239 u32
*destreg
,*srcreg
;
1242 destreg
= DECODE_RM_LONG_REGISTER(rh
);
1244 srcreg
= DECODE_RM_LONG_REGISTER(rl
);
1246 imul_long_direct(&res_lo
,&res_hi
,(s32
)*destreg
,(s32
)*srcreg
);
1254 *destreg
= (u32
)res_lo
;
1256 u16
*destreg
,*srcreg
;
1259 destreg
= DECODE_RM_WORD_REGISTER(rh
);
1261 srcreg
= DECODE_RM_WORD_REGISTER(rl
);
1262 res
= (s16
)*destreg
* (s16
)*srcreg
;
1270 *destreg
= (u16
)res
;
1274 DECODE_CLEAR_SEGOVR();
1278 /****************************************************************************
1280 Handles opcode 0x0f,0xb2
1281 ****************************************************************************/
1282 static void x86emuOp2_lss_R_IMM(u8
X86EMU_UNUSED(op2
))
1289 DECODE_PRINTF("LSS\t");
1290 FETCH_DECODE_MODRM(mod
, rh
, rl
);
1293 dstreg
= DECODE_RM_WORD_REGISTER(rh
);
1295 srcoffset
= decode_rm00_address(rl
);
1296 DECODE_PRINTF("\n");
1298 *dstreg
= fetch_data_word(srcoffset
);
1299 M
.x86
.R_SS
= fetch_data_word(srcoffset
+ 2);
1302 dstreg
= DECODE_RM_WORD_REGISTER(rh
);
1304 srcoffset
= decode_rm01_address(rl
);
1305 DECODE_PRINTF("\n");
1307 *dstreg
= fetch_data_word(srcoffset
);
1308 M
.x86
.R_SS
= fetch_data_word(srcoffset
+ 2);
1311 dstreg
= DECODE_RM_WORD_REGISTER(rh
);
1313 srcoffset
= decode_rm10_address(rl
);
1314 DECODE_PRINTF("\n");
1316 *dstreg
= fetch_data_word(srcoffset
);
1317 M
.x86
.R_SS
= fetch_data_word(srcoffset
+ 2);
1319 case 3: /* register to register */
1323 DECODE_CLEAR_SEGOVR();
1327 /****************************************************************************
1329 Handles opcode 0x0f,0xb3
1330 ****************************************************************************/
1331 static void x86emuOp2_btr_R(u8
X86EMU_UNUSED(op2
))
1338 DECODE_PRINTF("BTR\t");
1339 FETCH_DECODE_MODRM(mod
, rh
, rl
);
1342 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
1346 srcoffset
= decode_rm00_address(rl
);
1348 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
1350 bit
= *shiftreg
& 0x1F;
1351 disp
= (s16
)*shiftreg
>> 5;
1352 srcval
= fetch_data_long(srcoffset
+disp
);
1353 mask
= (0x1 << bit
);
1354 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
1355 store_data_long(srcoffset
+disp
, srcval
& ~mask
);
1360 srcoffset
= decode_rm00_address(rl
);
1362 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
1364 bit
= *shiftreg
& 0xF;
1365 disp
= (s16
)*shiftreg
>> 4;
1366 srcval
= fetch_data_word(srcoffset
+disp
);
1367 mask
= (u16
)(0x1 << bit
);
1368 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
1369 store_data_word(srcoffset
+disp
, (u16
)(srcval
& ~mask
));
1373 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
1377 srcoffset
= decode_rm01_address(rl
);
1379 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
1381 bit
= *shiftreg
& 0x1F;
1382 disp
= (s16
)*shiftreg
>> 5;
1383 srcval
= fetch_data_long(srcoffset
+disp
);
1384 mask
= (0x1 << bit
);
1385 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
1386 store_data_long(srcoffset
+disp
, srcval
& ~mask
);
1391 srcoffset
= decode_rm01_address(rl
);
1393 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
1395 bit
= *shiftreg
& 0xF;
1396 disp
= (s16
)*shiftreg
>> 4;
1397 srcval
= fetch_data_word(srcoffset
+disp
);
1398 mask
= (u16
)(0x1 << bit
);
1399 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
1400 store_data_word(srcoffset
+disp
, (u16
)(srcval
& ~mask
));
1404 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
1408 srcoffset
= decode_rm10_address(rl
);
1410 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
1412 bit
= *shiftreg
& 0x1F;
1413 disp
= (s16
)*shiftreg
>> 5;
1414 srcval
= fetch_data_long(srcoffset
+disp
);
1415 mask
= (0x1 << bit
);
1416 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
1417 store_data_long(srcoffset
+disp
, srcval
& ~mask
);
1422 srcoffset
= decode_rm10_address(rl
);
1424 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
1426 bit
= *shiftreg
& 0xF;
1427 disp
= (s16
)*shiftreg
>> 4;
1428 srcval
= fetch_data_word(srcoffset
+disp
);
1429 mask
= (u16
)(0x1 << bit
);
1430 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
1431 store_data_word(srcoffset
+disp
, (u16
)(srcval
& ~mask
));
1434 case 3: /* register to register */
1435 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
1436 u32
*srcreg
,*shiftreg
;
1439 srcreg
= DECODE_RM_LONG_REGISTER(rl
);
1441 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
1443 bit
= *shiftreg
& 0x1F;
1444 mask
= (0x1 << bit
);
1445 CONDITIONAL_SET_FLAG(*srcreg
& mask
,F_CF
);
1448 u16
*srcreg
,*shiftreg
;
1451 srcreg
= DECODE_RM_WORD_REGISTER(rl
);
1453 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
1455 bit
= *shiftreg
& 0xF;
1456 mask
= (u16
)(0x1 << bit
);
1457 CONDITIONAL_SET_FLAG(*srcreg
& mask
,F_CF
);
1462 DECODE_CLEAR_SEGOVR();
1466 /****************************************************************************
1468 Handles opcode 0x0f,0xb4
1469 ****************************************************************************/
1470 static void x86emuOp2_lfs_R_IMM(u8
X86EMU_UNUSED(op2
))
1477 DECODE_PRINTF("LFS\t");
1478 FETCH_DECODE_MODRM(mod
, rh
, rl
);
1481 dstreg
= DECODE_RM_WORD_REGISTER(rh
);
1483 srcoffset
= decode_rm00_address(rl
);
1484 DECODE_PRINTF("\n");
1486 *dstreg
= fetch_data_word(srcoffset
);
1487 M
.x86
.R_FS
= fetch_data_word(srcoffset
+ 2);
1490 dstreg
= DECODE_RM_WORD_REGISTER(rh
);
1492 srcoffset
= decode_rm01_address(rl
);
1493 DECODE_PRINTF("\n");
1495 *dstreg
= fetch_data_word(srcoffset
);
1496 M
.x86
.R_FS
= fetch_data_word(srcoffset
+ 2);
1499 dstreg
= DECODE_RM_WORD_REGISTER(rh
);
1501 srcoffset
= decode_rm10_address(rl
);
1502 DECODE_PRINTF("\n");
1504 *dstreg
= fetch_data_word(srcoffset
);
1505 M
.x86
.R_FS
= fetch_data_word(srcoffset
+ 2);
1507 case 3: /* register to register */
1511 DECODE_CLEAR_SEGOVR();
1515 /****************************************************************************
1517 Handles opcode 0x0f,0xb5
1518 ****************************************************************************/
1519 static void x86emuOp2_lgs_R_IMM(u8
X86EMU_UNUSED(op2
))
1526 DECODE_PRINTF("LGS\t");
1527 FETCH_DECODE_MODRM(mod
, rh
, rl
);
1530 dstreg
= DECODE_RM_WORD_REGISTER(rh
);
1532 srcoffset
= decode_rm00_address(rl
);
1533 DECODE_PRINTF("\n");
1535 *dstreg
= fetch_data_word(srcoffset
);
1536 M
.x86
.R_GS
= fetch_data_word(srcoffset
+ 2);
1539 dstreg
= DECODE_RM_WORD_REGISTER(rh
);
1541 srcoffset
= decode_rm01_address(rl
);
1542 DECODE_PRINTF("\n");
1544 *dstreg
= fetch_data_word(srcoffset
);
1545 M
.x86
.R_GS
= fetch_data_word(srcoffset
+ 2);
1548 dstreg
= DECODE_RM_WORD_REGISTER(rh
);
1550 srcoffset
= decode_rm10_address(rl
);
1551 DECODE_PRINTF("\n");
1553 *dstreg
= fetch_data_word(srcoffset
);
1554 M
.x86
.R_GS
= fetch_data_word(srcoffset
+ 2);
1556 case 3: /* register to register */
1560 DECODE_CLEAR_SEGOVR();
1564 /****************************************************************************
1566 Handles opcode 0x0f,0xb6
1567 ****************************************************************************/
1568 static void x86emuOp2_movzx_byte_R_RM(u8
X86EMU_UNUSED(op2
))
1574 DECODE_PRINTF("MOVZX\t");
1575 FETCH_DECODE_MODRM(mod
, rh
, rl
);
1578 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
1582 destreg
= DECODE_RM_LONG_REGISTER(rh
);
1584 srcoffset
= decode_rm00_address(rl
);
1585 srcval
= fetch_data_byte(srcoffset
);
1586 DECODE_PRINTF("\n");
1593 destreg
= DECODE_RM_WORD_REGISTER(rh
);
1595 srcoffset
= decode_rm00_address(rl
);
1596 srcval
= fetch_data_byte(srcoffset
);
1597 DECODE_PRINTF("\n");
1603 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
1607 destreg
= DECODE_RM_LONG_REGISTER(rh
);
1609 srcoffset
= decode_rm01_address(rl
);
1610 srcval
= fetch_data_byte(srcoffset
);
1611 DECODE_PRINTF("\n");
1618 destreg
= DECODE_RM_WORD_REGISTER(rh
);
1620 srcoffset
= decode_rm01_address(rl
);
1621 srcval
= fetch_data_byte(srcoffset
);
1622 DECODE_PRINTF("\n");
1628 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
1632 destreg
= DECODE_RM_LONG_REGISTER(rh
);
1634 srcoffset
= decode_rm10_address(rl
);
1635 srcval
= fetch_data_byte(srcoffset
);
1636 DECODE_PRINTF("\n");
1643 destreg
= DECODE_RM_WORD_REGISTER(rh
);
1645 srcoffset
= decode_rm10_address(rl
);
1646 srcval
= fetch_data_byte(srcoffset
);
1647 DECODE_PRINTF("\n");
1652 case 3: /* register to register */
1653 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
1657 destreg
= DECODE_RM_LONG_REGISTER(rh
);
1659 srcreg
= DECODE_RM_BYTE_REGISTER(rl
);
1660 DECODE_PRINTF("\n");
1667 destreg
= DECODE_RM_WORD_REGISTER(rh
);
1669 srcreg
= DECODE_RM_BYTE_REGISTER(rl
);
1670 DECODE_PRINTF("\n");
1676 DECODE_CLEAR_SEGOVR();
1680 /****************************************************************************
1682 Handles opcode 0x0f,0xb7
1683 ****************************************************************************/
1684 static void x86emuOp2_movzx_word_R_RM(u8
X86EMU_UNUSED(op2
))
1693 DECODE_PRINTF("MOVZX\t");
1694 FETCH_DECODE_MODRM(mod
, rh
, rl
);
1697 destreg
= DECODE_RM_LONG_REGISTER(rh
);
1699 srcoffset
= decode_rm00_address(rl
);
1700 srcval
= fetch_data_word(srcoffset
);
1701 DECODE_PRINTF("\n");
1706 destreg
= DECODE_RM_LONG_REGISTER(rh
);
1708 srcoffset
= decode_rm01_address(rl
);
1709 srcval
= fetch_data_word(srcoffset
);
1710 DECODE_PRINTF("\n");
1715 destreg
= DECODE_RM_LONG_REGISTER(rh
);
1717 srcoffset
= decode_rm10_address(rl
);
1718 srcval
= fetch_data_word(srcoffset
);
1719 DECODE_PRINTF("\n");
1723 case 3: /* register to register */
1724 destreg
= DECODE_RM_LONG_REGISTER(rh
);
1726 srcreg
= DECODE_RM_WORD_REGISTER(rl
);
1727 DECODE_PRINTF("\n");
1732 DECODE_CLEAR_SEGOVR();
1736 /****************************************************************************
1738 Handles opcode 0x0f,0xba
1739 ****************************************************************************/
1740 static void x86emuOp2_btX_I(u8
X86EMU_UNUSED(op2
))
1747 FETCH_DECODE_MODRM(mod
, rh
, rl
);
1750 DECODE_PRINTF("BT\t");
1753 DECODE_PRINTF("BTS\t");
1756 DECODE_PRINTF("BTR\t");
1759 DECODE_PRINTF("BTC\t");
1762 DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
1764 printk("%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n",
1765 M
.x86
.R_CS
, M
.x86
.R_IP
-3,op2
, (mod
<<6)|(rh
<<3)|rl
);
1770 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
1774 srcoffset
= decode_rm00_address(rl
);
1776 shift
= fetch_byte_imm();
1779 srcval
= fetch_data_long(srcoffset
);
1780 mask
= (0x1 << bit
);
1781 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
1784 store_data_long(srcoffset
, srcval
| mask
);
1787 store_data_long(srcoffset
, srcval
& ~mask
);
1790 store_data_long(srcoffset
, srcval
^ mask
);
1799 srcoffset
= decode_rm00_address(rl
);
1801 shift
= fetch_byte_imm();
1804 srcval
= fetch_data_word(srcoffset
);
1805 mask
= (0x1 << bit
);
1806 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
1809 store_data_word(srcoffset
, srcval
| mask
);
1812 store_data_word(srcoffset
, srcval
& ~mask
);
1815 store_data_word(srcoffset
, srcval
^ mask
);
1823 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
1827 srcoffset
= decode_rm01_address(rl
);
1829 shift
= fetch_byte_imm();
1832 srcval
= fetch_data_long(srcoffset
);
1833 mask
= (0x1 << bit
);
1834 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
1837 store_data_long(srcoffset
, srcval
| mask
);
1840 store_data_long(srcoffset
, srcval
& ~mask
);
1843 store_data_long(srcoffset
, srcval
^ mask
);
1852 srcoffset
= decode_rm01_address(rl
);
1854 shift
= fetch_byte_imm();
1857 srcval
= fetch_data_word(srcoffset
);
1858 mask
= (0x1 << bit
);
1859 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
1862 store_data_word(srcoffset
, srcval
| mask
);
1865 store_data_word(srcoffset
, srcval
& ~mask
);
1868 store_data_word(srcoffset
, srcval
^ mask
);
1876 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
1880 srcoffset
= decode_rm10_address(rl
);
1882 shift
= fetch_byte_imm();
1885 srcval
= fetch_data_long(srcoffset
);
1886 mask
= (0x1 << bit
);
1887 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
1890 store_data_long(srcoffset
, srcval
| mask
);
1893 store_data_long(srcoffset
, srcval
& ~mask
);
1896 store_data_long(srcoffset
, srcval
^ mask
);
1905 srcoffset
= decode_rm10_address(rl
);
1907 shift
= fetch_byte_imm();
1910 srcval
= fetch_data_word(srcoffset
);
1911 mask
= (0x1 << bit
);
1912 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
1915 store_data_word(srcoffset
, srcval
| mask
);
1918 store_data_word(srcoffset
, srcval
& ~mask
);
1921 store_data_word(srcoffset
, srcval
^ mask
);
1928 case 3: /* register to register */
1929 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
1934 srcreg
= DECODE_RM_LONG_REGISTER(rl
);
1936 shift
= fetch_byte_imm();
1939 mask
= (0x1 << bit
);
1940 CONDITIONAL_SET_FLAG(*srcreg
& mask
,F_CF
);
1959 srcreg
= DECODE_RM_WORD_REGISTER(rl
);
1961 shift
= fetch_byte_imm();
1964 mask
= (0x1 << bit
);
1965 CONDITIONAL_SET_FLAG(*srcreg
& mask
,F_CF
);
1982 DECODE_CLEAR_SEGOVR();
1986 /****************************************************************************
1988 Handles opcode 0x0f,0xbb
1989 ****************************************************************************/
1990 static void x86emuOp2_btc_R(u8
X86EMU_UNUSED(op2
))
1997 DECODE_PRINTF("BTC\t");
1998 FETCH_DECODE_MODRM(mod
, rh
, rl
);
2001 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
2005 srcoffset
= decode_rm00_address(rl
);
2007 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
2009 bit
= *shiftreg
& 0x1F;
2010 disp
= (s16
)*shiftreg
>> 5;
2011 srcval
= fetch_data_long(srcoffset
+disp
);
2012 mask
= (0x1 << bit
);
2013 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
2014 store_data_long(srcoffset
+disp
, srcval
^ mask
);
2019 srcoffset
= decode_rm00_address(rl
);
2021 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
2023 bit
= *shiftreg
& 0xF;
2024 disp
= (s16
)*shiftreg
>> 4;
2025 srcval
= fetch_data_word(srcoffset
+disp
);
2026 mask
= (u16
)(0x1 << bit
);
2027 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
2028 store_data_word(srcoffset
+disp
, (u16
)(srcval
^ mask
));
2032 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
2036 srcoffset
= decode_rm01_address(rl
);
2038 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
2040 bit
= *shiftreg
& 0x1F;
2041 disp
= (s16
)*shiftreg
>> 5;
2042 srcval
= fetch_data_long(srcoffset
+disp
);
2043 mask
= (0x1 << bit
);
2044 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
2045 store_data_long(srcoffset
+disp
, srcval
^ mask
);
2050 srcoffset
= decode_rm01_address(rl
);
2052 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
2054 bit
= *shiftreg
& 0xF;
2055 disp
= (s16
)*shiftreg
>> 4;
2056 srcval
= fetch_data_word(srcoffset
+disp
);
2057 mask
= (u16
)(0x1 << bit
);
2058 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
2059 store_data_word(srcoffset
+disp
, (u16
)(srcval
^ mask
));
2063 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
2067 srcoffset
= decode_rm10_address(rl
);
2069 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
2071 bit
= *shiftreg
& 0x1F;
2072 disp
= (s16
)*shiftreg
>> 5;
2073 srcval
= fetch_data_long(srcoffset
+disp
);
2074 mask
= (0x1 << bit
);
2075 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
2076 store_data_long(srcoffset
+disp
, srcval
^ mask
);
2081 srcoffset
= decode_rm10_address(rl
);
2083 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
2085 bit
= *shiftreg
& 0xF;
2086 disp
= (s16
)*shiftreg
>> 4;
2087 srcval
= fetch_data_word(srcoffset
+disp
);
2088 mask
= (u16
)(0x1 << bit
);
2089 CONDITIONAL_SET_FLAG(srcval
& mask
,F_CF
);
2090 store_data_word(srcoffset
+disp
, (u16
)(srcval
^ mask
));
2093 case 3: /* register to register */
2094 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
2095 u32
*srcreg
,*shiftreg
;
2098 srcreg
= DECODE_RM_LONG_REGISTER(rl
);
2100 shiftreg
= DECODE_RM_LONG_REGISTER(rh
);
2102 bit
= *shiftreg
& 0x1F;
2103 mask
= (0x1 << bit
);
2104 CONDITIONAL_SET_FLAG(*srcreg
& mask
,F_CF
);
2107 u16
*srcreg
,*shiftreg
;
2110 srcreg
= DECODE_RM_WORD_REGISTER(rl
);
2112 shiftreg
= DECODE_RM_WORD_REGISTER(rh
);
2114 bit
= *shiftreg
& 0xF;
2115 mask
= (u16
)(0x1 << bit
);
2116 CONDITIONAL_SET_FLAG(*srcreg
& mask
,F_CF
);
2121 DECODE_CLEAR_SEGOVR();
2125 /****************************************************************************
2127 Handles opcode 0x0f,0xbc
2128 ****************************************************************************/
2129 static void x86emuOp2_bsf(u8
X86EMU_UNUSED(op2
))
2135 DECODE_PRINTF("BSF\n");
2136 FETCH_DECODE_MODRM(mod
, rh
, rl
);
2139 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
2140 u32 srcval
, *dstreg
;
2142 srcoffset
= decode_rm00_address(rl
);
2144 dstreg
= DECODE_RM_LONG_REGISTER(rh
);
2146 srcval
= fetch_data_long(srcoffset
);
2147 CONDITIONAL_SET_FLAG(srcval
== 0, F_ZF
);
2148 for(*dstreg
= 0; *dstreg
< 32; (*dstreg
)++)
2149 if ((srcval
>> *dstreg
) & 1) break;
2151 u16 srcval
, *dstreg
;
2153 srcoffset
= decode_rm00_address(rl
);
2155 dstreg
= DECODE_RM_WORD_REGISTER(rh
);
2157 srcval
= fetch_data_word(srcoffset
);
2158 CONDITIONAL_SET_FLAG(srcval
== 0, F_ZF
);
2159 for(*dstreg
= 0; *dstreg
< 16; (*dstreg
)++)
2160 if ((srcval
>> *dstreg
) & 1) break;
2164 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
2165 u32 srcval
, *dstreg
;
2167 srcoffset
= decode_rm01_address(rl
);
2169 dstreg
= DECODE_RM_LONG_REGISTER(rh
);
2171 srcval
= fetch_data_long(srcoffset
);
2172 CONDITIONAL_SET_FLAG(srcval
== 0, F_ZF
);
2173 for(*dstreg
= 0; *dstreg
< 32; (*dstreg
)++)
2174 if ((srcval
>> *dstreg
) & 1) break;
2176 u16 srcval
, *dstreg
;
2178 srcoffset
= decode_rm01_address(rl
);
2180 dstreg
= DECODE_RM_WORD_REGISTER(rh
);
2182 srcval
= fetch_data_word(srcoffset
);
2183 CONDITIONAL_SET_FLAG(srcval
== 0, F_ZF
);
2184 for(*dstreg
= 0; *dstreg
< 16; (*dstreg
)++)
2185 if ((srcval
>> *dstreg
) & 1) break;
2189 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
2190 u32 srcval
, *dstreg
;
2192 srcoffset
= decode_rm10_address(rl
);
2194 dstreg
= DECODE_RM_LONG_REGISTER(rh
);
2196 srcval
= fetch_data_long(srcoffset
);
2197 CONDITIONAL_SET_FLAG(srcval
== 0, F_ZF
);
2198 for(*dstreg
= 0; *dstreg
< 32; (*dstreg
)++)
2199 if ((srcval
>> *dstreg
) & 1) break;
2201 u16 srcval
, *dstreg
;
2203 srcoffset
= decode_rm10_address(rl
);
2205 dstreg
= DECODE_RM_WORD_REGISTER(rh
);
2207 srcval
= fetch_data_word(srcoffset
);
2208 CONDITIONAL_SET_FLAG(srcval
== 0, F_ZF
);
2209 for(*dstreg
= 0; *dstreg
< 16; (*dstreg
)++)
2210 if ((srcval
>> *dstreg
) & 1) break;
2213 case 3: /* register to register */
2214 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
2215 u32
*srcreg
, *dstreg
;
2217 srcreg
= DECODE_RM_LONG_REGISTER(rl
);
2219 dstreg
= DECODE_RM_LONG_REGISTER(rh
);
2221 CONDITIONAL_SET_FLAG(*srcreg
== 0, F_ZF
);
2222 for(*dstreg
= 0; *dstreg
< 32; (*dstreg
)++)
2223 if ((*srcreg
>> *dstreg
) & 1) break;
2225 u16
*srcreg
, *dstreg
;
2227 srcreg
= DECODE_RM_WORD_REGISTER(rl
);
2229 dstreg
= DECODE_RM_WORD_REGISTER(rh
);
2231 CONDITIONAL_SET_FLAG(*srcreg
== 0, F_ZF
);
2232 for(*dstreg
= 0; *dstreg
< 16; (*dstreg
)++)
2233 if ((*srcreg
>> *dstreg
) & 1) break;
2237 DECODE_CLEAR_SEGOVR();
2241 /****************************************************************************
2243 Handles opcode 0x0f,0xbd
2244 ****************************************************************************/
2245 static void x86emuOp2_bsr(u8
X86EMU_UNUSED(op2
))
2251 DECODE_PRINTF("BSF\n");
2252 FETCH_DECODE_MODRM(mod
, rh
, rl
);
2255 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
2256 u32 srcval
, *dstreg
;
2258 srcoffset
= decode_rm00_address(rl
);
2260 dstreg
= DECODE_RM_LONG_REGISTER(rh
);
2262 srcval
= fetch_data_long(srcoffset
);
2263 CONDITIONAL_SET_FLAG(srcval
== 0, F_ZF
);
2264 for(*dstreg
= 31; *dstreg
> 0; (*dstreg
)--)
2265 if ((srcval
>> *dstreg
) & 1) break;
2267 u16 srcval
, *dstreg
;
2269 srcoffset
= decode_rm00_address(rl
);
2271 dstreg
= DECODE_RM_WORD_REGISTER(rh
);
2273 srcval
= fetch_data_word(srcoffset
);
2274 CONDITIONAL_SET_FLAG(srcval
== 0, F_ZF
);
2275 for(*dstreg
= 15; *dstreg
> 0; (*dstreg
)--)
2276 if ((srcval
>> *dstreg
) & 1) break;
2280 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
2281 u32 srcval
, *dstreg
;
2283 srcoffset
= decode_rm01_address(rl
);
2285 dstreg
= DECODE_RM_LONG_REGISTER(rh
);
2287 srcval
= fetch_data_long(srcoffset
);
2288 CONDITIONAL_SET_FLAG(srcval
== 0, F_ZF
);
2289 for(*dstreg
= 31; *dstreg
> 0; (*dstreg
)--)
2290 if ((srcval
>> *dstreg
) & 1) break;
2292 u16 srcval
, *dstreg
;
2294 srcoffset
= decode_rm01_address(rl
);
2296 dstreg
= DECODE_RM_WORD_REGISTER(rh
);
2298 srcval
= fetch_data_word(srcoffset
);
2299 CONDITIONAL_SET_FLAG(srcval
== 0, F_ZF
);
2300 for(*dstreg
= 15; *dstreg
> 0; (*dstreg
)--)
2301 if ((srcval
>> *dstreg
) & 1) break;
2305 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
2306 u32 srcval
, *dstreg
;
2308 srcoffset
= decode_rm10_address(rl
);
2310 dstreg
= DECODE_RM_LONG_REGISTER(rh
);
2312 srcval
= fetch_data_long(srcoffset
);
2313 CONDITIONAL_SET_FLAG(srcval
== 0, F_ZF
);
2314 for(*dstreg
= 31; *dstreg
> 0; (*dstreg
)--)
2315 if ((srcval
>> *dstreg
) & 1) break;
2317 u16 srcval
, *dstreg
;
2319 srcoffset
= decode_rm10_address(rl
);
2321 dstreg
= DECODE_RM_WORD_REGISTER(rh
);
2323 srcval
= fetch_data_word(srcoffset
);
2324 CONDITIONAL_SET_FLAG(srcval
== 0, F_ZF
);
2325 for(*dstreg
= 15; *dstreg
> 0; (*dstreg
)--)
2326 if ((srcval
>> *dstreg
) & 1) break;
2329 case 3: /* register to register */
2330 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
2331 u32
*srcreg
, *dstreg
;
2333 srcreg
= DECODE_RM_LONG_REGISTER(rl
);
2335 dstreg
= DECODE_RM_LONG_REGISTER(rh
);
2337 CONDITIONAL_SET_FLAG(*srcreg
== 0, F_ZF
);
2338 for(*dstreg
= 31; *dstreg
> 0; (*dstreg
)--)
2339 if ((*srcreg
>> *dstreg
) & 1) break;
2341 u16
*srcreg
, *dstreg
;
2343 srcreg
= DECODE_RM_WORD_REGISTER(rl
);
2345 dstreg
= DECODE_RM_WORD_REGISTER(rh
);
2347 CONDITIONAL_SET_FLAG(*srcreg
== 0, F_ZF
);
2348 for(*dstreg
= 15; *dstreg
> 0; (*dstreg
)--)
2349 if ((*srcreg
>> *dstreg
) & 1) break;
2353 DECODE_CLEAR_SEGOVR();
2357 /****************************************************************************
2359 Handles opcode 0x0f,0xbe
2360 ****************************************************************************/
2361 static void x86emuOp2_movsx_byte_R_RM(u8
X86EMU_UNUSED(op2
))
2367 DECODE_PRINTF("MOVSX\t");
2368 FETCH_DECODE_MODRM(mod
, rh
, rl
);
2371 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
2375 destreg
= DECODE_RM_LONG_REGISTER(rh
);
2377 srcoffset
= decode_rm00_address(rl
);
2378 srcval
= (s32
)((s8
)fetch_data_byte(srcoffset
));
2379 DECODE_PRINTF("\n");
2386 destreg
= DECODE_RM_WORD_REGISTER(rh
);
2388 srcoffset
= decode_rm00_address(rl
);
2389 srcval
= (s16
)((s8
)fetch_data_byte(srcoffset
));
2390 DECODE_PRINTF("\n");
2396 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
2400 destreg
= DECODE_RM_LONG_REGISTER(rh
);
2402 srcoffset
= decode_rm01_address(rl
);
2403 srcval
= (s32
)((s8
)fetch_data_byte(srcoffset
));
2404 DECODE_PRINTF("\n");
2411 destreg
= DECODE_RM_WORD_REGISTER(rh
);
2413 srcoffset
= decode_rm01_address(rl
);
2414 srcval
= (s16
)((s8
)fetch_data_byte(srcoffset
));
2415 DECODE_PRINTF("\n");
2421 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
2425 destreg
= DECODE_RM_LONG_REGISTER(rh
);
2427 srcoffset
= decode_rm10_address(rl
);
2428 srcval
= (s32
)((s8
)fetch_data_byte(srcoffset
));
2429 DECODE_PRINTF("\n");
2436 destreg
= DECODE_RM_WORD_REGISTER(rh
);
2438 srcoffset
= decode_rm10_address(rl
);
2439 srcval
= (s16
)((s8
)fetch_data_byte(srcoffset
));
2440 DECODE_PRINTF("\n");
2445 case 3: /* register to register */
2446 if (M
.x86
.mode
& SYSMODE_PREFIX_DATA
) {
2450 destreg
= DECODE_RM_LONG_REGISTER(rh
);
2452 srcreg
= DECODE_RM_BYTE_REGISTER(rl
);
2453 DECODE_PRINTF("\n");
2455 *destreg
= (s32
)((s8
)*srcreg
);
2460 destreg
= DECODE_RM_WORD_REGISTER(rh
);
2462 srcreg
= DECODE_RM_BYTE_REGISTER(rl
);
2463 DECODE_PRINTF("\n");
2465 *destreg
= (s16
)((s8
)*srcreg
);
2469 DECODE_CLEAR_SEGOVR();
2473 /****************************************************************************
2475 Handles opcode 0x0f,0xbf
2476 ****************************************************************************/
2477 static void x86emuOp2_movsx_word_R_RM(u8
X86EMU_UNUSED(op2
))
2486 DECODE_PRINTF("MOVSX\t");
2487 FETCH_DECODE_MODRM(mod
, rh
, rl
);
2490 destreg
= DECODE_RM_LONG_REGISTER(rh
);
2492 srcoffset
= decode_rm00_address(rl
);
2493 srcval
= (s32
)((s16
)fetch_data_word(srcoffset
));
2494 DECODE_PRINTF("\n");
2499 destreg
= DECODE_RM_LONG_REGISTER(rh
);
2501 srcoffset
= decode_rm01_address(rl
);
2502 srcval
= (s32
)((s16
)fetch_data_word(srcoffset
));
2503 DECODE_PRINTF("\n");
2508 destreg
= DECODE_RM_LONG_REGISTER(rh
);
2510 srcoffset
= decode_rm10_address(rl
);
2511 srcval
= (s32
)((s16
)fetch_data_word(srcoffset
));
2512 DECODE_PRINTF("\n");
2516 case 3: /* register to register */
2517 destreg
= DECODE_RM_LONG_REGISTER(rh
);
2519 srcreg
= DECODE_RM_WORD_REGISTER(rl
);
2520 DECODE_PRINTF("\n");
2522 *destreg
= (s32
)((s16
)*srcreg
);
2525 DECODE_CLEAR_SEGOVR();
2529 /***************************************************************************
2530 * Double byte operation code table:
2531 **************************************************************************/
2532 void (*x86emu_optab2
[256])(u8
) =
2534 /* 0x00 */ x86emuOp2_illegal_op
, /* Group F (ring 0 PM) */
2535 /* 0x01 */ x86emuOp2_illegal_op
, /* Group G (ring 0 PM) */
2536 /* 0x02 */ x86emuOp2_illegal_op
, /* lar (ring 0 PM) */
2537 /* 0x03 */ x86emuOp2_illegal_op
, /* lsl (ring 0 PM) */
2538 /* 0x04 */ x86emuOp2_illegal_op
,
2539 /* 0x05 */ x86emuOp2_illegal_op
, /* loadall (undocumented) */
2540 /* 0x06 */ x86emuOp2_illegal_op
, /* clts (ring 0 PM) */
2541 /* 0x07 */ x86emuOp2_illegal_op
, /* loadall (undocumented) */
2542 /* 0x08 */ x86emuOp2_illegal_op
, /* invd (ring 0 PM) */
2543 /* 0x09 */ x86emuOp2_illegal_op
, /* wbinvd (ring 0 PM) */
2544 /* 0x0a */ x86emuOp2_illegal_op
,
2545 /* 0x0b */ x86emuOp2_illegal_op
,
2546 /* 0x0c */ x86emuOp2_illegal_op
,
2547 /* 0x0d */ x86emuOp2_illegal_op
,
2548 /* 0x0e */ x86emuOp2_illegal_op
,
2549 /* 0x0f */ x86emuOp2_illegal_op
,
2551 /* 0x10 */ x86emuOp2_illegal_op
,
2552 /* 0x11 */ x86emuOp2_illegal_op
,
2553 /* 0x12 */ x86emuOp2_illegal_op
,
2554 /* 0x13 */ x86emuOp2_illegal_op
,
2555 /* 0x14 */ x86emuOp2_illegal_op
,
2556 /* 0x15 */ x86emuOp2_illegal_op
,
2557 /* 0x16 */ x86emuOp2_illegal_op
,
2558 /* 0x17 */ x86emuOp2_illegal_op
,
2559 /* 0x18 */ x86emuOp2_illegal_op
,
2560 /* 0x19 */ x86emuOp2_illegal_op
,
2561 /* 0x1a */ x86emuOp2_illegal_op
,
2562 /* 0x1b */ x86emuOp2_illegal_op
,
2563 /* 0x1c */ x86emuOp2_illegal_op
,
2564 /* 0x1d */ x86emuOp2_illegal_op
,
2565 /* 0x1e */ x86emuOp2_illegal_op
,
2566 /* 0x1f */ x86emuOp2_illegal_op
,
2568 /* 0x20 */ x86emuOp2_illegal_op
, /* mov reg32,creg (ring 0 PM) */
2569 /* 0x21 */ x86emuOp2_illegal_op
, /* mov reg32,dreg (ring 0 PM) */
2570 /* 0x22 */ x86emuOp2_illegal_op
, /* mov creg,reg32 (ring 0 PM) */
2571 /* 0x23 */ x86emuOp2_illegal_op
, /* mov dreg,reg32 (ring 0 PM) */
2572 /* 0x24 */ x86emuOp2_illegal_op
, /* mov reg32,treg (ring 0 PM) */
2573 /* 0x25 */ x86emuOp2_illegal_op
,
2574 /* 0x26 */ x86emuOp2_illegal_op
, /* mov treg,reg32 (ring 0 PM) */
2575 /* 0x27 */ x86emuOp2_illegal_op
,
2576 /* 0x28 */ x86emuOp2_illegal_op
,
2577 /* 0x29 */ x86emuOp2_illegal_op
,
2578 /* 0x2a */ x86emuOp2_illegal_op
,
2579 /* 0x2b */ x86emuOp2_illegal_op
,
2580 /* 0x2c */ x86emuOp2_illegal_op
,
2581 /* 0x2d */ x86emuOp2_illegal_op
,
2582 /* 0x2e */ x86emuOp2_illegal_op
,
2583 /* 0x2f */ x86emuOp2_illegal_op
,
2585 /* 0x30 */ x86emuOp2_illegal_op
,
2586 /* 0x31 */ x86emuOp2_illegal_op
,
2587 /* 0x32 */ x86emuOp2_illegal_op
,
2588 /* 0x33 */ x86emuOp2_illegal_op
,
2589 /* 0x34 */ x86emuOp2_illegal_op
,
2590 /* 0x35 */ x86emuOp2_illegal_op
,
2591 /* 0x36 */ x86emuOp2_illegal_op
,
2592 /* 0x37 */ x86emuOp2_illegal_op
,
2593 /* 0x38 */ x86emuOp2_illegal_op
,
2594 /* 0x39 */ x86emuOp2_illegal_op
,
2595 /* 0x3a */ x86emuOp2_illegal_op
,
2596 /* 0x3b */ x86emuOp2_illegal_op
,
2597 /* 0x3c */ x86emuOp2_illegal_op
,
2598 /* 0x3d */ x86emuOp2_illegal_op
,
2599 /* 0x3e */ x86emuOp2_illegal_op
,
2600 /* 0x3f */ x86emuOp2_illegal_op
,
2602 /* 0x40 */ x86emuOp2_illegal_op
,
2603 /* 0x41 */ x86emuOp2_illegal_op
,
2604 /* 0x42 */ x86emuOp2_illegal_op
,
2605 /* 0x43 */ x86emuOp2_illegal_op
,
2606 /* 0x44 */ x86emuOp2_illegal_op
,
2607 /* 0x45 */ x86emuOp2_illegal_op
,
2608 /* 0x46 */ x86emuOp2_illegal_op
,
2609 /* 0x47 */ x86emuOp2_illegal_op
,
2610 /* 0x48 */ x86emuOp2_illegal_op
,
2611 /* 0x49 */ x86emuOp2_illegal_op
,
2612 /* 0x4a */ x86emuOp2_illegal_op
,
2613 /* 0x4b */ x86emuOp2_illegal_op
,
2614 /* 0x4c */ x86emuOp2_illegal_op
,
2615 /* 0x4d */ x86emuOp2_illegal_op
,
2616 /* 0x4e */ x86emuOp2_illegal_op
,
2617 /* 0x4f */ x86emuOp2_illegal_op
,
2619 /* 0x50 */ x86emuOp2_illegal_op
,
2620 /* 0x51 */ x86emuOp2_illegal_op
,
2621 /* 0x52 */ x86emuOp2_illegal_op
,
2622 /* 0x53 */ x86emuOp2_illegal_op
,
2623 /* 0x54 */ x86emuOp2_illegal_op
,
2624 /* 0x55 */ x86emuOp2_illegal_op
,
2625 /* 0x56 */ x86emuOp2_illegal_op
,
2626 /* 0x57 */ x86emuOp2_illegal_op
,
2627 /* 0x58 */ x86emuOp2_illegal_op
,
2628 /* 0x59 */ x86emuOp2_illegal_op
,
2629 /* 0x5a */ x86emuOp2_illegal_op
,
2630 /* 0x5b */ x86emuOp2_illegal_op
,
2631 /* 0x5c */ x86emuOp2_illegal_op
,
2632 /* 0x5d */ x86emuOp2_illegal_op
,
2633 /* 0x5e */ x86emuOp2_illegal_op
,
2634 /* 0x5f */ x86emuOp2_illegal_op
,
2636 /* 0x60 */ x86emuOp2_illegal_op
,
2637 /* 0x61 */ x86emuOp2_illegal_op
,
2638 /* 0x62 */ x86emuOp2_illegal_op
,
2639 /* 0x63 */ x86emuOp2_illegal_op
,
2640 /* 0x64 */ x86emuOp2_illegal_op
,
2641 /* 0x65 */ x86emuOp2_illegal_op
,
2642 /* 0x66 */ x86emuOp2_illegal_op
,
2643 /* 0x67 */ x86emuOp2_illegal_op
,
2644 /* 0x68 */ x86emuOp2_illegal_op
,
2645 /* 0x69 */ x86emuOp2_illegal_op
,
2646 /* 0x6a */ x86emuOp2_illegal_op
,
2647 /* 0x6b */ x86emuOp2_illegal_op
,
2648 /* 0x6c */ x86emuOp2_illegal_op
,
2649 /* 0x6d */ x86emuOp2_illegal_op
,
2650 /* 0x6e */ x86emuOp2_illegal_op
,
2651 /* 0x6f */ x86emuOp2_illegal_op
,
2653 /* 0x70 */ x86emuOp2_illegal_op
,
2654 /* 0x71 */ x86emuOp2_illegal_op
,
2655 /* 0x72 */ x86emuOp2_illegal_op
,
2656 /* 0x73 */ x86emuOp2_illegal_op
,
2657 /* 0x74 */ x86emuOp2_illegal_op
,
2658 /* 0x75 */ x86emuOp2_illegal_op
,
2659 /* 0x76 */ x86emuOp2_illegal_op
,
2660 /* 0x77 */ x86emuOp2_illegal_op
,
2661 /* 0x78 */ x86emuOp2_illegal_op
,
2662 /* 0x79 */ x86emuOp2_illegal_op
,
2663 /* 0x7a */ x86emuOp2_illegal_op
,
2664 /* 0x7b */ x86emuOp2_illegal_op
,
2665 /* 0x7c */ x86emuOp2_illegal_op
,
2666 /* 0x7d */ x86emuOp2_illegal_op
,
2667 /* 0x7e */ x86emuOp2_illegal_op
,
2668 /* 0x7f */ x86emuOp2_illegal_op
,
2670 /* 0x80 */ x86emuOp2_long_jump
,
2671 /* 0x81 */ x86emuOp2_long_jump
,
2672 /* 0x82 */ x86emuOp2_long_jump
,
2673 /* 0x83 */ x86emuOp2_long_jump
,
2674 /* 0x84 */ x86emuOp2_long_jump
,
2675 /* 0x85 */ x86emuOp2_long_jump
,
2676 /* 0x86 */ x86emuOp2_long_jump
,
2677 /* 0x87 */ x86emuOp2_long_jump
,
2678 /* 0x88 */ x86emuOp2_long_jump
,
2679 /* 0x89 */ x86emuOp2_long_jump
,
2680 /* 0x8a */ x86emuOp2_long_jump
,
2681 /* 0x8b */ x86emuOp2_long_jump
,
2682 /* 0x8c */ x86emuOp2_long_jump
,
2683 /* 0x8d */ x86emuOp2_long_jump
,
2684 /* 0x8e */ x86emuOp2_long_jump
,
2685 /* 0x8f */ x86emuOp2_long_jump
,
2687 /* 0x90 */ x86emuOp2_set_byte
,
2688 /* 0x91 */ x86emuOp2_set_byte
,
2689 /* 0x92 */ x86emuOp2_set_byte
,
2690 /* 0x93 */ x86emuOp2_set_byte
,
2691 /* 0x94 */ x86emuOp2_set_byte
,
2692 /* 0x95 */ x86emuOp2_set_byte
,
2693 /* 0x96 */ x86emuOp2_set_byte
,
2694 /* 0x97 */ x86emuOp2_set_byte
,
2695 /* 0x98 */ x86emuOp2_set_byte
,
2696 /* 0x99 */ x86emuOp2_set_byte
,
2697 /* 0x9a */ x86emuOp2_set_byte
,
2698 /* 0x9b */ x86emuOp2_set_byte
,
2699 /* 0x9c */ x86emuOp2_set_byte
,
2700 /* 0x9d */ x86emuOp2_set_byte
,
2701 /* 0x9e */ x86emuOp2_set_byte
,
2702 /* 0x9f */ x86emuOp2_set_byte
,
2704 /* 0xa0 */ x86emuOp2_push_FS
,
2705 /* 0xa1 */ x86emuOp2_pop_FS
,
2706 /* 0xa2 */ x86emuOp2_illegal_op
,
2707 /* 0xa3 */ x86emuOp2_bt_R
,
2708 /* 0xa4 */ x86emuOp2_shld_IMM
,
2709 /* 0xa5 */ x86emuOp2_shld_CL
,
2710 /* 0xa6 */ x86emuOp2_illegal_op
,
2711 /* 0xa7 */ x86emuOp2_illegal_op
,
2712 /* 0xa8 */ x86emuOp2_push_GS
,
2713 /* 0xa9 */ x86emuOp2_pop_GS
,
2714 /* 0xaa */ x86emuOp2_illegal_op
,
2715 /* 0xab */ x86emuOp2_bt_R
,
2716 /* 0xac */ x86emuOp2_shrd_IMM
,
2717 /* 0xad */ x86emuOp2_shrd_CL
,
2718 /* 0xae */ x86emuOp2_illegal_op
,
2719 /* 0xaf */ x86emuOp2_imul_R_RM
,
2721 /* 0xb0 */ x86emuOp2_illegal_op
, /* TODO: cmpxchg */
2722 /* 0xb1 */ x86emuOp2_illegal_op
, /* TODO: cmpxchg */
2723 /* 0xb2 */ x86emuOp2_lss_R_IMM
,
2724 /* 0xb3 */ x86emuOp2_btr_R
,
2725 /* 0xb4 */ x86emuOp2_lfs_R_IMM
,
2726 /* 0xb5 */ x86emuOp2_lgs_R_IMM
,
2727 /* 0xb6 */ x86emuOp2_movzx_byte_R_RM
,
2728 /* 0xb7 */ x86emuOp2_movzx_word_R_RM
,
2729 /* 0xb8 */ x86emuOp2_illegal_op
,
2730 /* 0xb9 */ x86emuOp2_illegal_op
,
2731 /* 0xba */ x86emuOp2_btX_I
,
2732 /* 0xbb */ x86emuOp2_btc_R
,
2733 /* 0xbc */ x86emuOp2_bsf
,
2734 /* 0xbd */ x86emuOp2_bsr
,
2735 /* 0xbe */ x86emuOp2_movsx_byte_R_RM
,
2736 /* 0xbf */ x86emuOp2_movsx_word_R_RM
,
2738 /* 0xc0 */ x86emuOp2_illegal_op
, /* TODO: xadd */
2739 /* 0xc1 */ x86emuOp2_illegal_op
, /* TODO: xadd */
2740 /* 0xc2 */ x86emuOp2_illegal_op
,
2741 /* 0xc3 */ x86emuOp2_illegal_op
,
2742 /* 0xc4 */ x86emuOp2_illegal_op
,
2743 /* 0xc5 */ x86emuOp2_illegal_op
,
2744 /* 0xc6 */ x86emuOp2_illegal_op
,
2745 /* 0xc7 */ x86emuOp2_illegal_op
,
2746 /* 0xc8 */ x86emuOp2_illegal_op
, /* TODO: bswap */
2747 /* 0xc9 */ x86emuOp2_illegal_op
, /* TODO: bswap */
2748 /* 0xca */ x86emuOp2_illegal_op
, /* TODO: bswap */
2749 /* 0xcb */ x86emuOp2_illegal_op
, /* TODO: bswap */
2750 /* 0xcc */ x86emuOp2_illegal_op
, /* TODO: bswap */
2751 /* 0xcd */ x86emuOp2_illegal_op
, /* TODO: bswap */
2752 /* 0xce */ x86emuOp2_illegal_op
, /* TODO: bswap */
2753 /* 0xcf */ x86emuOp2_illegal_op
, /* TODO: bswap */
2755 /* 0xd0 */ x86emuOp2_illegal_op
,
2756 /* 0xd1 */ x86emuOp2_illegal_op
,
2757 /* 0xd2 */ x86emuOp2_illegal_op
,
2758 /* 0xd3 */ x86emuOp2_illegal_op
,
2759 /* 0xd4 */ x86emuOp2_illegal_op
,
2760 /* 0xd5 */ x86emuOp2_illegal_op
,
2761 /* 0xd6 */ x86emuOp2_illegal_op
,
2762 /* 0xd7 */ x86emuOp2_illegal_op
,
2763 /* 0xd8 */ x86emuOp2_illegal_op
,
2764 /* 0xd9 */ x86emuOp2_illegal_op
,
2765 /* 0xda */ x86emuOp2_illegal_op
,
2766 /* 0xdb */ x86emuOp2_illegal_op
,
2767 /* 0xdc */ x86emuOp2_illegal_op
,
2768 /* 0xdd */ x86emuOp2_illegal_op
,
2769 /* 0xde */ x86emuOp2_illegal_op
,
2770 /* 0xdf */ x86emuOp2_illegal_op
,
2772 /* 0xe0 */ x86emuOp2_illegal_op
,
2773 /* 0xe1 */ x86emuOp2_illegal_op
,
2774 /* 0xe2 */ x86emuOp2_illegal_op
,
2775 /* 0xe3 */ x86emuOp2_illegal_op
,
2776 /* 0xe4 */ x86emuOp2_illegal_op
,
2777 /* 0xe5 */ x86emuOp2_illegal_op
,
2778 /* 0xe6 */ x86emuOp2_illegal_op
,
2779 /* 0xe7 */ x86emuOp2_illegal_op
,
2780 /* 0xe8 */ x86emuOp2_illegal_op
,
2781 /* 0xe9 */ x86emuOp2_illegal_op
,
2782 /* 0xea */ x86emuOp2_illegal_op
,
2783 /* 0xeb */ x86emuOp2_illegal_op
,
2784 /* 0xec */ x86emuOp2_illegal_op
,
2785 /* 0xed */ x86emuOp2_illegal_op
,
2786 /* 0xee */ x86emuOp2_illegal_op
,
2787 /* 0xef */ x86emuOp2_illegal_op
,
2789 /* 0xf0 */ x86emuOp2_illegal_op
,
2790 /* 0xf1 */ x86emuOp2_illegal_op
,
2791 /* 0xf2 */ x86emuOp2_illegal_op
,
2792 /* 0xf3 */ x86emuOp2_illegal_op
,
2793 /* 0xf4 */ x86emuOp2_illegal_op
,
2794 /* 0xf5 */ x86emuOp2_illegal_op
,
2795 /* 0xf6 */ x86emuOp2_illegal_op
,
2796 /* 0xf7 */ x86emuOp2_illegal_op
,
2797 /* 0xf8 */ x86emuOp2_illegal_op
,
2798 /* 0xf9 */ x86emuOp2_illegal_op
,
2799 /* 0xfa */ x86emuOp2_illegal_op
,
2800 /* 0xfb */ x86emuOp2_illegal_op
,
2801 /* 0xfc */ x86emuOp2_illegal_op
,
2802 /* 0xfd */ x86emuOp2_illegal_op
,
2803 /* 0xfe */ x86emuOp2_illegal_op
,
2804 /* 0xff */ x86emuOp2_illegal_op
,