2 * OpenRISC virtual CPU header.
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #ifndef OPENRISC_CPU_H
21 #define OPENRISC_CPU_H
23 #include "exec/cpu-defs.h"
26 /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
29 #define TYPE_OPENRISC_CPU "or1k-cpu"
31 #define OPENRISC_CPU_CLASS(klass) \
32 OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
33 #define OPENRISC_CPU(obj) \
34 OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
35 #define OPENRISC_CPU_GET_CLASS(obj) \
36 OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)
40 * @parent_realize: The parent class' realize handler.
41 * @parent_reset: The parent class' reset handler.
43 * A OpenRISC CPU model.
45 typedef struct OpenRISCCPUClass
{
47 CPUClass parent_class
;
50 DeviceRealize parent_realize
;
51 void (*parent_reset
)(CPUState
*cpu
);
54 #define TARGET_INSN_START_EXTRA_WORDS 1
58 MMU_SUPERVISOR_IDX
= 1,
62 #define SET_FP_CAUSE(reg, v) do {\
63 (reg) = ((reg) & ~(0x3f << 12)) | \
66 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
67 #define UPDATE_FP_FLAGS(reg, v) do {\
68 (reg) |= ((v & 0x1f) << 2);\
71 /* Version Register */
72 #define SPR_VR 0xFFFF003F
77 /* Unit presece register */
90 UPR_CUP
= (255 << 24),
93 /* CPU configure register */
95 CPUCFGR_NSGF
= (15 << 0),
96 CPUCFGR_CGF
= (1 << 4),
97 CPUCFGR_OB32S
= (1 << 5),
98 CPUCFGR_OB64S
= (1 << 6),
99 CPUCFGR_OF32S
= (1 << 7),
100 CPUCFGR_OF64S
= (1 << 8),
101 CPUCFGR_OV64S
= (1 << 9),
102 /* CPUCFGR_ND = (1 << 10), */
103 /* CPUCFGR_AVRP = (1 << 11), */
104 CPUCFGR_EVBARP
= (1 << 12),
105 /* CPUCFGR_ISRP = (1 << 13), */
106 /* CPUCFGR_AECSRP = (1 << 14), */
109 /* DMMU configure register */
111 DMMUCFGR_NTW
= (3 << 0),
112 DMMUCFGR_NTS
= (7 << 2),
113 DMMUCFGR_NAE
= (7 << 5),
114 DMMUCFGR_CRI
= (1 << 8),
115 DMMUCFGR_PRI
= (1 << 9),
116 DMMUCFGR_TEIRI
= (1 << 10),
117 DMMUCFGR_HTR
= (1 << 11),
120 /* IMMU configure register */
122 IMMUCFGR_NTW
= (3 << 0),
123 IMMUCFGR_NTS
= (7 << 2),
124 IMMUCFGR_NAE
= (7 << 5),
125 IMMUCFGR_CRI
= (1 << 8),
126 IMMUCFGR_PRI
= (1 << 9),
127 IMMUCFGR_TEIRI
= (1 << 10),
128 IMMUCFGR_HTR
= (1 << 11),
131 /* Power management register */
140 /* Float point control status register */
144 FPCSR_OVF
= (1 << 3),
145 FPCSR_UNF
= (1 << 4),
146 FPCSR_SNF
= (1 << 5),
147 FPCSR_QNF
= (1 << 6),
149 FPCSR_IXF
= (1 << 8),
150 FPCSR_IVF
= (1 << 9),
151 FPCSR_INF
= (1 << 10),
152 FPCSR_DZF
= (1 << 11),
155 /* Exceptions indices */
174 /* Supervisor register */
192 SR_SUMRA
= (1 << 16),
196 /* Tick Timer Mode Register */
198 TTMR_TP
= (0xfffffff),
206 TIMER_NONE
= (0 << 30),
207 TIMER_INTR
= (1 << 30),
208 TIMER_SHOT
= (2 << 30),
209 TIMER_CONT
= (3 << 30),
215 TLB_MASK
= TLB_SIZE
- 1,
229 typedef struct OpenRISCTLBEntry
{
234 #ifndef CONFIG_USER_ONLY
235 typedef struct CPUOpenRISCTLBContext
{
236 OpenRISCTLBEntry itlb
[TLB_SIZE
];
237 OpenRISCTLBEntry dtlb
[TLB_SIZE
];
239 int (*cpu_openrisc_map_address_code
)(struct OpenRISCCPU
*cpu
,
242 target_ulong address
, int rw
);
243 int (*cpu_openrisc_map_address_data
)(struct OpenRISCCPU
*cpu
,
246 target_ulong address
, int rw
);
247 } CPUOpenRISCTLBContext
;
250 typedef struct CPUOpenRISCState
{
251 target_ulong shadow_gpr
[16][32]; /* Shadow registers */
253 target_ulong pc
; /* Program counter */
254 target_ulong ppc
; /* Prev PC */
255 target_ulong jmp_pc
; /* Jump PC */
257 uint64_t mac
; /* Multiply registers MACHI:MACLO */
259 target_ulong epcr
; /* Exception PC register */
260 target_ulong eear
; /* Exception EA register */
262 target_ulong sr_f
; /* the SR_F bit, values 0, 1. */
263 target_ulong sr_cy
; /* the SR_CY bit, values 0, 1. */
264 target_long sr_ov
; /* the SR_OV bit (in the sign bit only) */
265 uint32_t sr
; /* Supervisor register, without SR_{F,CY,OV} */
266 uint32_t vr
; /* Version register */
267 uint32_t upr
; /* Unit presence register */
268 uint32_t dmmucfgr
; /* DMMU configure register */
269 uint32_t immucfgr
; /* IMMU configure register */
270 uint32_t esr
; /* Exception supervisor register */
271 uint32_t evbar
; /* Exception vector base address register */
272 uint32_t pmr
; /* Power Management Register */
273 uint32_t fpcsr
; /* Float register */
274 float_status fp_status
;
276 target_ulong lock_addr
;
277 target_ulong lock_value
;
279 uint32_t dflag
; /* In delay slot (boolean) */
281 #ifndef CONFIG_USER_ONLY
282 CPUOpenRISCTLBContext tlb
;
285 /* Fields up to this point are cleared by a CPU reset */
286 struct {} end_reset_fields
;
288 /* Fields from here on are preserved across CPU reset. */
289 uint32_t cpucfgr
; /* CPU configure register */
291 #ifndef CONFIG_USER_ONLY
293 uint32_t ttmr
; /* Timer tick mode register */
296 uint32_t picmr
; /* Interrupt mask register */
297 uint32_t picsr
; /* Interrupt contrl register*/
299 void *irq
[32]; /* Interrupt irq input */
304 * @env: #CPUOpenRISCState
308 typedef struct OpenRISCCPU
{
313 CPUNegativeOffsetState neg
;
314 CPUOpenRISCState env
;
318 void cpu_openrisc_list(void);
319 void openrisc_cpu_do_interrupt(CPUState
*cpu
);
320 bool openrisc_cpu_exec_interrupt(CPUState
*cpu
, int int_req
);
321 void openrisc_cpu_dump_state(CPUState
*cpu
, FILE *f
, int flags
);
322 hwaddr
openrisc_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
323 int openrisc_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
324 int openrisc_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
325 void openrisc_translate_init(void);
326 bool openrisc_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
327 MMUAccessType access_type
, int mmu_idx
,
328 bool probe
, uintptr_t retaddr
);
329 int cpu_openrisc_signal_handler(int host_signum
, void *pinfo
, void *puc
);
330 int print_insn_or1k(bfd_vma addr
, disassemble_info
*info
);
332 #define cpu_list cpu_openrisc_list
333 #define cpu_signal_handler cpu_openrisc_signal_handler
335 #ifndef CONFIG_USER_ONLY
336 extern const VMStateDescription vmstate_openrisc_cpu
;
338 /* hw/openrisc_pic.c */
339 void cpu_openrisc_pic_init(OpenRISCCPU
*cpu
);
341 /* hw/openrisc_timer.c */
342 void cpu_openrisc_clock_init(OpenRISCCPU
*cpu
);
343 uint32_t cpu_openrisc_count_get(OpenRISCCPU
*cpu
);
344 void cpu_openrisc_count_set(OpenRISCCPU
*cpu
, uint32_t val
);
345 void cpu_openrisc_count_update(OpenRISCCPU
*cpu
);
346 void cpu_openrisc_timer_update(OpenRISCCPU
*cpu
);
347 void cpu_openrisc_count_start(OpenRISCCPU
*cpu
);
348 void cpu_openrisc_count_stop(OpenRISCCPU
*cpu
);
351 #define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU
352 #define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX
353 #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU
355 typedef CPUOpenRISCState CPUArchState
;
356 typedef OpenRISCCPU ArchCPU
;
358 #include "exec/cpu-all.h"
360 #define TB_FLAGS_SM SR_SM
361 #define TB_FLAGS_DME SR_DME
362 #define TB_FLAGS_IME SR_IME
363 #define TB_FLAGS_OVE SR_OVE
364 #define TB_FLAGS_DFLAG 2 /* reuse SR_TEE */
365 #define TB_FLAGS_R0_0 4 /* reuse SR_IEE */
367 static inline uint32_t cpu_get_gpr(const CPUOpenRISCState
*env
, int i
)
369 return env
->shadow_gpr
[0][i
];
372 static inline void cpu_set_gpr(CPUOpenRISCState
*env
, int i
, uint32_t val
)
374 env
->shadow_gpr
[0][i
] = val
;
377 static inline void cpu_get_tb_cpu_state(CPUOpenRISCState
*env
,
379 target_ulong
*cs_base
, uint32_t *flags
)
383 *flags
= (env
->dflag
? TB_FLAGS_DFLAG
: 0)
384 | (cpu_get_gpr(env
, 0) ? 0 : TB_FLAGS_R0_0
)
385 | (env
->sr
& (SR_SM
| SR_DME
| SR_IME
| SR_OVE
));
388 static inline int cpu_mmu_index(CPUOpenRISCState
*env
, bool ifetch
)
390 int ret
= MMU_NOMMU_IDX
; /* mmu is disabled */
392 if (env
->sr
& (ifetch
? SR_IME
: SR_DME
)) {
393 /* The mmu is enabled; test supervisor state. */
394 ret
= env
->sr
& SR_SM
? MMU_SUPERVISOR_IDX
: MMU_USER_IDX
;
400 static inline uint32_t cpu_get_sr(const CPUOpenRISCState
*env
)
405 + (env
->sr_ov
< 0) * SR_OV
);
408 static inline void cpu_set_sr(CPUOpenRISCState
*env
, uint32_t val
)
410 env
->sr_f
= (val
& SR_F
) != 0;
411 env
->sr_cy
= (val
& SR_CY
) != 0;
412 env
->sr_ov
= (val
& SR_OV
? -1 : 0);
413 env
->sr
= (val
& ~(SR_F
| SR_CY
| SR_OV
)) | SR_FO
;
416 #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
418 #endif /* OPENRISC_CPU_H */