2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
27 #include "tcg-op-gvec.h"
28 #include "qemu/host-utils.h"
29 #include "exec/cpu_ldst.h"
31 #include "exec/helper-proto.h"
32 #include "exec/helper-gen.h"
34 #include "trace-tcg.h"
35 #include "exec/translator.h"
37 #include "qemu/atomic128.h"
40 #define CPU_SINGLE_STEP 0x1
41 #define CPU_BRANCH_STEP 0x2
42 #define GDBSTUB_SINGLE_STEP 0x4
44 /* Include definitions for instructions classes and implementations flags */
45 //#define PPC_DEBUG_DISAS
46 //#define DO_PPC_STATISTICS
48 #ifdef PPC_DEBUG_DISAS
49 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
51 # define LOG_DISAS(...) do { } while (0)
53 /*****************************************************************************/
54 /* Code translation helpers */
56 /* global register indexes */
57 static char cpu_reg_names
[10*3 + 22*4 /* GPR */
58 + 10*4 + 22*5 /* SPE GPRh */
60 static TCGv cpu_gpr
[32];
61 static TCGv cpu_gprh
[32];
62 static TCGv_i32 cpu_crf
[8];
67 #if defined(TARGET_PPC64)
70 static TCGv cpu_xer
, cpu_so
, cpu_ov
, cpu_ca
, cpu_ov32
, cpu_ca32
;
71 static TCGv cpu_reserve
;
72 static TCGv cpu_reserve_val
;
73 static TCGv cpu_fpscr
;
74 static TCGv_i32 cpu_access_type
;
76 #include "exec/gen-icount.h"
78 void ppc_translate_init(void)
82 size_t cpu_reg_names_size
;
85 cpu_reg_names_size
= sizeof(cpu_reg_names
);
87 for (i
= 0; i
< 8; i
++) {
88 snprintf(p
, cpu_reg_names_size
, "crf%d", i
);
89 cpu_crf
[i
] = tcg_global_mem_new_i32(cpu_env
,
90 offsetof(CPUPPCState
, crf
[i
]), p
);
92 cpu_reg_names_size
-= 5;
95 for (i
= 0; i
< 32; i
++) {
96 snprintf(p
, cpu_reg_names_size
, "r%d", i
);
97 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
98 offsetof(CPUPPCState
, gpr
[i
]), p
);
99 p
+= (i
< 10) ? 3 : 4;
100 cpu_reg_names_size
-= (i
< 10) ? 3 : 4;
101 snprintf(p
, cpu_reg_names_size
, "r%dH", i
);
102 cpu_gprh
[i
] = tcg_global_mem_new(cpu_env
,
103 offsetof(CPUPPCState
, gprh
[i
]), p
);
104 p
+= (i
< 10) ? 4 : 5;
105 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
108 cpu_nip
= tcg_global_mem_new(cpu_env
,
109 offsetof(CPUPPCState
, nip
), "nip");
111 cpu_msr
= tcg_global_mem_new(cpu_env
,
112 offsetof(CPUPPCState
, msr
), "msr");
114 cpu_ctr
= tcg_global_mem_new(cpu_env
,
115 offsetof(CPUPPCState
, ctr
), "ctr");
117 cpu_lr
= tcg_global_mem_new(cpu_env
,
118 offsetof(CPUPPCState
, lr
), "lr");
120 #if defined(TARGET_PPC64)
121 cpu_cfar
= tcg_global_mem_new(cpu_env
,
122 offsetof(CPUPPCState
, cfar
), "cfar");
125 cpu_xer
= tcg_global_mem_new(cpu_env
,
126 offsetof(CPUPPCState
, xer
), "xer");
127 cpu_so
= tcg_global_mem_new(cpu_env
,
128 offsetof(CPUPPCState
, so
), "SO");
129 cpu_ov
= tcg_global_mem_new(cpu_env
,
130 offsetof(CPUPPCState
, ov
), "OV");
131 cpu_ca
= tcg_global_mem_new(cpu_env
,
132 offsetof(CPUPPCState
, ca
), "CA");
133 cpu_ov32
= tcg_global_mem_new(cpu_env
,
134 offsetof(CPUPPCState
, ov32
), "OV32");
135 cpu_ca32
= tcg_global_mem_new(cpu_env
,
136 offsetof(CPUPPCState
, ca32
), "CA32");
138 cpu_reserve
= tcg_global_mem_new(cpu_env
,
139 offsetof(CPUPPCState
, reserve_addr
),
141 cpu_reserve_val
= tcg_global_mem_new(cpu_env
,
142 offsetof(CPUPPCState
, reserve_val
),
145 cpu_fpscr
= tcg_global_mem_new(cpu_env
,
146 offsetof(CPUPPCState
, fpscr
), "fpscr");
148 cpu_access_type
= tcg_global_mem_new_i32(cpu_env
,
149 offsetof(CPUPPCState
, access_type
), "access_type");
152 /* internal defines */
153 struct DisasContext
{
154 DisasContextBase base
;
157 /* Routine used to access memory */
158 bool pr
, hv
, dr
, le_mode
;
160 bool need_access_type
;
163 /* Translation flags */
164 TCGMemOp default_tcg_memop_mask
;
165 #if defined(TARGET_PPC64)
170 bool altivec_enabled
;
175 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
176 int singlestep_enabled
;
178 uint64_t insns_flags
;
179 uint64_t insns_flags2
;
182 /* Return true iff byteswap is needed in a scalar memop */
183 static inline bool need_byteswap(const DisasContext
*ctx
)
185 #if defined(TARGET_WORDS_BIGENDIAN)
188 return !ctx
->le_mode
;
192 /* True when active word size < size of target_long. */
194 # define NARROW_MODE(C) (!(C)->sf_mode)
196 # define NARROW_MODE(C) 0
199 struct opc_handler_t
{
200 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
202 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
204 /* instruction type */
206 /* extended instruction type */
209 void (*handler
)(DisasContext
*ctx
);
210 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
213 #if defined(DO_PPC_STATISTICS)
218 /* SPR load/store helpers */
219 static inline void gen_load_spr(TCGv t
, int reg
)
221 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
224 static inline void gen_store_spr(int reg
, TCGv t
)
226 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
229 static inline void gen_set_access_type(DisasContext
*ctx
, int access_type
)
231 if (ctx
->need_access_type
&& ctx
->access_type
!= access_type
) {
232 tcg_gen_movi_i32(cpu_access_type
, access_type
);
233 ctx
->access_type
= access_type
;
237 static inline void gen_update_nip(DisasContext
*ctx
, target_ulong nip
)
239 if (NARROW_MODE(ctx
)) {
242 tcg_gen_movi_tl(cpu_nip
, nip
);
245 static void gen_exception_err(DisasContext
*ctx
, uint32_t excp
, uint32_t error
)
249 /* These are all synchronous exceptions, we set the PC back to
250 * the faulting instruction
252 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
253 gen_update_nip(ctx
, ctx
->base
.pc_next
- 4);
255 t0
= tcg_const_i32(excp
);
256 t1
= tcg_const_i32(error
);
257 gen_helper_raise_exception_err(cpu_env
, t0
, t1
);
258 tcg_temp_free_i32(t0
);
259 tcg_temp_free_i32(t1
);
260 ctx
->exception
= (excp
);
263 static void gen_exception(DisasContext
*ctx
, uint32_t excp
)
267 /* These are all synchronous exceptions, we set the PC back to
268 * the faulting instruction
270 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
271 gen_update_nip(ctx
, ctx
->base
.pc_next
- 4);
273 t0
= tcg_const_i32(excp
);
274 gen_helper_raise_exception(cpu_env
, t0
);
275 tcg_temp_free_i32(t0
);
276 ctx
->exception
= (excp
);
279 static void gen_exception_nip(DisasContext
*ctx
, uint32_t excp
,
284 gen_update_nip(ctx
, nip
);
285 t0
= tcg_const_i32(excp
);
286 gen_helper_raise_exception(cpu_env
, t0
);
287 tcg_temp_free_i32(t0
);
288 ctx
->exception
= (excp
);
292 * Tells the caller what is the appropriate exception to generate and prepares
293 * SPR registers for this exception.
295 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or
296 * POWERPC_EXCP_DEBUG (on BookE).
298 static uint32_t gen_prep_dbgex(DisasContext
*ctx
)
300 if (ctx
->flags
& POWERPC_FLAG_DE
) {
301 target_ulong dbsr
= 0;
302 if (ctx
->singlestep_enabled
& CPU_SINGLE_STEP
) {
305 /* Must have been branch */
308 TCGv t0
= tcg_temp_new();
309 gen_load_spr(t0
, SPR_BOOKE_DBSR
);
310 tcg_gen_ori_tl(t0
, t0
, dbsr
);
311 gen_store_spr(SPR_BOOKE_DBSR
, t0
);
313 return POWERPC_EXCP_DEBUG
;
315 return POWERPC_EXCP_TRACE
;
319 static void gen_debug_exception(DisasContext
*ctx
)
323 /* These are all synchronous exceptions, we set the PC back to
324 * the faulting instruction
326 if ((ctx
->exception
!= POWERPC_EXCP_BRANCH
) &&
327 (ctx
->exception
!= POWERPC_EXCP_SYNC
)) {
328 gen_update_nip(ctx
, ctx
->base
.pc_next
);
330 t0
= tcg_const_i32(EXCP_DEBUG
);
331 gen_helper_raise_exception(cpu_env
, t0
);
332 tcg_temp_free_i32(t0
);
335 static inline void gen_inval_exception(DisasContext
*ctx
, uint32_t error
)
337 /* Will be converted to program check if needed */
338 gen_exception_err(ctx
, POWERPC_EXCP_HV_EMU
, POWERPC_EXCP_INVAL
| error
);
341 static inline void gen_priv_exception(DisasContext
*ctx
, uint32_t error
)
343 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_PRIV
| error
);
346 static inline void gen_hvpriv_exception(DisasContext
*ctx
, uint32_t error
)
348 /* Will be converted to program check if needed */
349 gen_exception_err(ctx
, POWERPC_EXCP_HV_EMU
, POWERPC_EXCP_PRIV
| error
);
352 /* Stop translation */
353 static inline void gen_stop_exception(DisasContext
*ctx
)
355 gen_update_nip(ctx
, ctx
->base
.pc_next
);
356 ctx
->exception
= POWERPC_EXCP_STOP
;
359 #ifndef CONFIG_USER_ONLY
360 /* No need to update nip here, as execution flow will change */
361 static inline void gen_sync_exception(DisasContext
*ctx
)
363 ctx
->exception
= POWERPC_EXCP_SYNC
;
367 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
368 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
370 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
371 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
373 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
374 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
376 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
377 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
379 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
380 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
382 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
383 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
385 typedef struct opcode_t
{
386 unsigned char opc1
, opc2
, opc3
, opc4
;
387 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
388 unsigned char pad
[4];
390 opc_handler_t handler
;
394 /* Helpers for priv. check */
397 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
400 #if defined(CONFIG_USER_ONLY)
401 #define CHK_HV GEN_PRIV
402 #define CHK_SV GEN_PRIV
403 #define CHK_HVRM GEN_PRIV
407 if (unlikely(ctx->pr || !ctx->hv)) { \
413 if (unlikely(ctx->pr)) { \
419 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
427 /*****************************************************************************/
428 /* PowerPC instructions table */
430 #if defined(DO_PPC_STATISTICS)
431 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
441 .handler = &gen_##name, \
442 .oname = stringify(name), \
444 .oname = stringify(name), \
446 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
457 .handler = &gen_##name, \
458 .oname = stringify(name), \
460 .oname = stringify(name), \
462 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
472 .handler = &gen_##name, \
477 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
487 .handler = &gen_##name, \
488 .oname = stringify(name), \
490 .oname = stringify(name), \
492 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
502 .handler = &gen_##name, \
508 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
518 .handler = &gen_##name, \
520 .oname = stringify(name), \
522 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
533 .handler = &gen_##name, \
535 .oname = stringify(name), \
537 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
547 .handler = &gen_##name, \
551 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
561 .handler = &gen_##name, \
563 .oname = stringify(name), \
565 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
575 .handler = &gen_##name, \
581 /* Invalid instruction */
582 static void gen_invalid(DisasContext
*ctx
)
584 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
587 static opc_handler_t invalid_handler
= {
588 .inval1
= 0xFFFFFFFF,
589 .inval2
= 0xFFFFFFFF,
592 .handler
= gen_invalid
,
595 /*** Integer comparison ***/
597 static inline void gen_op_cmp(TCGv arg0
, TCGv arg1
, int s
, int crf
)
599 TCGv t0
= tcg_temp_new();
600 TCGv t1
= tcg_temp_new();
601 TCGv_i32 t
= tcg_temp_new_i32();
603 tcg_gen_movi_tl(t0
, CRF_EQ
);
604 tcg_gen_movi_tl(t1
, CRF_LT
);
605 tcg_gen_movcond_tl((s
? TCG_COND_LT
: TCG_COND_LTU
), t0
, arg0
, arg1
, t1
, t0
);
606 tcg_gen_movi_tl(t1
, CRF_GT
);
607 tcg_gen_movcond_tl((s
? TCG_COND_GT
: TCG_COND_GTU
), t0
, arg0
, arg1
, t1
, t0
);
609 tcg_gen_trunc_tl_i32(t
, t0
);
610 tcg_gen_trunc_tl_i32(cpu_crf
[crf
], cpu_so
);
611 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t
);
615 tcg_temp_free_i32(t
);
618 static inline void gen_op_cmpi(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
620 TCGv t0
= tcg_const_tl(arg1
);
621 gen_op_cmp(arg0
, t0
, s
, crf
);
625 static inline void gen_op_cmp32(TCGv arg0
, TCGv arg1
, int s
, int crf
)
631 tcg_gen_ext32s_tl(t0
, arg0
);
632 tcg_gen_ext32s_tl(t1
, arg1
);
634 tcg_gen_ext32u_tl(t0
, arg0
);
635 tcg_gen_ext32u_tl(t1
, arg1
);
637 gen_op_cmp(t0
, t1
, s
, crf
);
642 static inline void gen_op_cmpi32(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
644 TCGv t0
= tcg_const_tl(arg1
);
645 gen_op_cmp32(arg0
, t0
, s
, crf
);
649 static inline void gen_set_Rc0(DisasContext
*ctx
, TCGv reg
)
651 if (NARROW_MODE(ctx
)) {
652 gen_op_cmpi32(reg
, 0, 1, 0);
654 gen_op_cmpi(reg
, 0, 1, 0);
659 static void gen_cmp(DisasContext
*ctx
)
661 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
662 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
663 1, crfD(ctx
->opcode
));
665 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
666 1, crfD(ctx
->opcode
));
671 static void gen_cmpi(DisasContext
*ctx
)
673 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
674 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
675 1, crfD(ctx
->opcode
));
677 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
678 1, crfD(ctx
->opcode
));
683 static void gen_cmpl(DisasContext
*ctx
)
685 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
686 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
687 0, crfD(ctx
->opcode
));
689 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
690 0, crfD(ctx
->opcode
));
695 static void gen_cmpli(DisasContext
*ctx
)
697 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
698 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
699 0, crfD(ctx
->opcode
));
701 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
702 0, crfD(ctx
->opcode
));
706 /* cmprb - range comparison: isupper, isaplha, islower*/
707 static void gen_cmprb(DisasContext
*ctx
)
709 TCGv_i32 src1
= tcg_temp_new_i32();
710 TCGv_i32 src2
= tcg_temp_new_i32();
711 TCGv_i32 src2lo
= tcg_temp_new_i32();
712 TCGv_i32 src2hi
= tcg_temp_new_i32();
713 TCGv_i32 crf
= cpu_crf
[crfD(ctx
->opcode
)];
715 tcg_gen_trunc_tl_i32(src1
, cpu_gpr
[rA(ctx
->opcode
)]);
716 tcg_gen_trunc_tl_i32(src2
, cpu_gpr
[rB(ctx
->opcode
)]);
718 tcg_gen_andi_i32(src1
, src1
, 0xFF);
719 tcg_gen_ext8u_i32(src2lo
, src2
);
720 tcg_gen_shri_i32(src2
, src2
, 8);
721 tcg_gen_ext8u_i32(src2hi
, src2
);
723 tcg_gen_setcond_i32(TCG_COND_LEU
, src2lo
, src2lo
, src1
);
724 tcg_gen_setcond_i32(TCG_COND_LEU
, src2hi
, src1
, src2hi
);
725 tcg_gen_and_i32(crf
, src2lo
, src2hi
);
727 if (ctx
->opcode
& 0x00200000) {
728 tcg_gen_shri_i32(src2
, src2
, 8);
729 tcg_gen_ext8u_i32(src2lo
, src2
);
730 tcg_gen_shri_i32(src2
, src2
, 8);
731 tcg_gen_ext8u_i32(src2hi
, src2
);
732 tcg_gen_setcond_i32(TCG_COND_LEU
, src2lo
, src2lo
, src1
);
733 tcg_gen_setcond_i32(TCG_COND_LEU
, src2hi
, src1
, src2hi
);
734 tcg_gen_and_i32(src2lo
, src2lo
, src2hi
);
735 tcg_gen_or_i32(crf
, crf
, src2lo
);
737 tcg_gen_shli_i32(crf
, crf
, CRF_GT_BIT
);
738 tcg_temp_free_i32(src1
);
739 tcg_temp_free_i32(src2
);
740 tcg_temp_free_i32(src2lo
);
741 tcg_temp_free_i32(src2hi
);
744 #if defined(TARGET_PPC64)
746 static void gen_cmpeqb(DisasContext
*ctx
)
748 gen_helper_cmpeqb(cpu_crf
[crfD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
749 cpu_gpr
[rB(ctx
->opcode
)]);
753 /* isel (PowerPC 2.03 specification) */
754 static void gen_isel(DisasContext
*ctx
)
756 uint32_t bi
= rC(ctx
->opcode
);
757 uint32_t mask
= 0x08 >> (bi
& 0x03);
758 TCGv t0
= tcg_temp_new();
761 tcg_gen_extu_i32_tl(t0
, cpu_crf
[bi
>> 2]);
762 tcg_gen_andi_tl(t0
, t0
, mask
);
764 zr
= tcg_const_tl(0);
765 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr
[rD(ctx
->opcode
)], t0
, zr
,
766 rA(ctx
->opcode
) ? cpu_gpr
[rA(ctx
->opcode
)] : zr
,
767 cpu_gpr
[rB(ctx
->opcode
)]);
772 /* cmpb: PowerPC 2.05 specification */
773 static void gen_cmpb(DisasContext
*ctx
)
775 gen_helper_cmpb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
776 cpu_gpr
[rB(ctx
->opcode
)]);
779 /*** Integer arithmetic ***/
781 static inline void gen_op_arith_compute_ov(DisasContext
*ctx
, TCGv arg0
,
782 TCGv arg1
, TCGv arg2
, int sub
)
784 TCGv t0
= tcg_temp_new();
786 tcg_gen_xor_tl(cpu_ov
, arg0
, arg2
);
787 tcg_gen_xor_tl(t0
, arg1
, arg2
);
789 tcg_gen_and_tl(cpu_ov
, cpu_ov
, t0
);
791 tcg_gen_andc_tl(cpu_ov
, cpu_ov
, t0
);
794 if (NARROW_MODE(ctx
)) {
795 tcg_gen_extract_tl(cpu_ov
, cpu_ov
, 31, 1);
796 if (is_isa300(ctx
)) {
797 tcg_gen_mov_tl(cpu_ov32
, cpu_ov
);
800 if (is_isa300(ctx
)) {
801 tcg_gen_extract_tl(cpu_ov32
, cpu_ov
, 31, 1);
803 tcg_gen_extract_tl(cpu_ov
, cpu_ov
, TARGET_LONG_BITS
- 1, 1);
805 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
808 static inline void gen_op_arith_compute_ca32(DisasContext
*ctx
,
809 TCGv res
, TCGv arg0
, TCGv arg1
,
814 if (!is_isa300(ctx
)) {
820 tcg_gen_eqv_tl(t0
, arg0
, arg1
);
822 tcg_gen_xor_tl(t0
, arg0
, arg1
);
824 tcg_gen_xor_tl(t0
, t0
, res
);
825 tcg_gen_extract_tl(ca32
, t0
, 32, 1);
829 /* Common add function */
830 static inline void gen_op_arith_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
831 TCGv arg2
, TCGv ca
, TCGv ca32
,
832 bool add_ca
, bool compute_ca
,
833 bool compute_ov
, bool compute_rc0
)
837 if (compute_ca
|| compute_ov
) {
842 if (NARROW_MODE(ctx
)) {
843 /* Caution: a non-obvious corner case of the spec is that we
844 must produce the *entire* 64-bit addition, but produce the
845 carry into bit 32. */
846 TCGv t1
= tcg_temp_new();
847 tcg_gen_xor_tl(t1
, arg1
, arg2
); /* add without carry */
848 tcg_gen_add_tl(t0
, arg1
, arg2
);
850 tcg_gen_add_tl(t0
, t0
, ca
);
852 tcg_gen_xor_tl(ca
, t0
, t1
); /* bits changed w/ carry */
854 tcg_gen_extract_tl(ca
, ca
, 32, 1);
855 if (is_isa300(ctx
)) {
856 tcg_gen_mov_tl(ca32
, ca
);
859 TCGv zero
= tcg_const_tl(0);
861 tcg_gen_add2_tl(t0
, ca
, arg1
, zero
, ca
, zero
);
862 tcg_gen_add2_tl(t0
, ca
, t0
, ca
, arg2
, zero
);
864 tcg_gen_add2_tl(t0
, ca
, arg1
, zero
, arg2
, zero
);
866 gen_op_arith_compute_ca32(ctx
, t0
, arg1
, arg2
, ca32
, 0);
870 tcg_gen_add_tl(t0
, arg1
, arg2
);
872 tcg_gen_add_tl(t0
, t0
, ca
);
877 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 0);
879 if (unlikely(compute_rc0
)) {
880 gen_set_Rc0(ctx
, t0
);
884 tcg_gen_mov_tl(ret
, t0
);
888 /* Add functions with two operands */
889 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \
890 static void glue(gen_, name)(DisasContext *ctx) \
892 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
893 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
895 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
897 /* Add functions with one operand and one immediate */
898 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \
899 add_ca, compute_ca, compute_ov) \
900 static void glue(gen_, name)(DisasContext *ctx) \
902 TCGv t0 = tcg_const_tl(const_val); \
903 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
904 cpu_gpr[rA(ctx->opcode)], t0, \
906 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
910 /* add add. addo addo. */
911 GEN_INT_ARITH_ADD(add
, 0x08, cpu_ca
, 0, 0, 0)
912 GEN_INT_ARITH_ADD(addo
, 0x18, cpu_ca
, 0, 0, 1)
913 /* addc addc. addco addco. */
914 GEN_INT_ARITH_ADD(addc
, 0x00, cpu_ca
, 0, 1, 0)
915 GEN_INT_ARITH_ADD(addco
, 0x10, cpu_ca
, 0, 1, 1)
916 /* adde adde. addeo addeo. */
917 GEN_INT_ARITH_ADD(adde
, 0x04, cpu_ca
, 1, 1, 0)
918 GEN_INT_ARITH_ADD(addeo
, 0x14, cpu_ca
, 1, 1, 1)
919 /* addme addme. addmeo addmeo. */
920 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, cpu_ca
, 1, 1, 0)
921 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, cpu_ca
, 1, 1, 1)
923 GEN_INT_ARITH_ADD(addex
, 0x05, cpu_ov
, 1, 1, 0);
924 /* addze addze. addzeo addzeo.*/
925 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, cpu_ca
, 1, 1, 0)
926 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, cpu_ca
, 1, 1, 1)
928 static void gen_addi(DisasContext
*ctx
)
930 target_long simm
= SIMM(ctx
->opcode
);
932 if (rA(ctx
->opcode
) == 0) {
934 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
);
936 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
937 cpu_gpr
[rA(ctx
->opcode
)], simm
);
941 static inline void gen_op_addic(DisasContext
*ctx
, bool compute_rc0
)
943 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
944 gen_op_arith_add(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
945 c
, cpu_ca
, cpu_ca32
, 0, 1, 0, compute_rc0
);
949 static void gen_addic(DisasContext
*ctx
)
951 gen_op_addic(ctx
, 0);
954 static void gen_addic_(DisasContext
*ctx
)
956 gen_op_addic(ctx
, 1);
960 static void gen_addis(DisasContext
*ctx
)
962 target_long simm
= SIMM(ctx
->opcode
);
964 if (rA(ctx
->opcode
) == 0) {
966 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
<< 16);
968 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
969 cpu_gpr
[rA(ctx
->opcode
)], simm
<< 16);
974 static void gen_addpcis(DisasContext
*ctx
)
976 target_long d
= DX(ctx
->opcode
);
978 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], ctx
->base
.pc_next
+ (d
<< 16));
981 static inline void gen_op_arith_divw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
982 TCGv arg2
, int sign
, int compute_ov
)
984 TCGv_i32 t0
= tcg_temp_new_i32();
985 TCGv_i32 t1
= tcg_temp_new_i32();
986 TCGv_i32 t2
= tcg_temp_new_i32();
987 TCGv_i32 t3
= tcg_temp_new_i32();
989 tcg_gen_trunc_tl_i32(t0
, arg1
);
990 tcg_gen_trunc_tl_i32(t1
, arg2
);
992 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
993 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, -1);
994 tcg_gen_and_i32(t2
, t2
, t3
);
995 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, 0);
996 tcg_gen_or_i32(t2
, t2
, t3
);
997 tcg_gen_movi_i32(t3
, 0);
998 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
999 tcg_gen_div_i32(t3
, t0
, t1
);
1000 tcg_gen_extu_i32_tl(ret
, t3
);
1002 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t1
, 0);
1003 tcg_gen_movi_i32(t3
, 0);
1004 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1005 tcg_gen_divu_i32(t3
, t0
, t1
);
1006 tcg_gen_extu_i32_tl(ret
, t3
);
1009 tcg_gen_extu_i32_tl(cpu_ov
, t2
);
1010 if (is_isa300(ctx
)) {
1011 tcg_gen_extu_i32_tl(cpu_ov32
, t2
);
1013 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1015 tcg_temp_free_i32(t0
);
1016 tcg_temp_free_i32(t1
);
1017 tcg_temp_free_i32(t2
);
1018 tcg_temp_free_i32(t3
);
1020 if (unlikely(Rc(ctx
->opcode
) != 0))
1021 gen_set_Rc0(ctx
, ret
);
1024 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1025 static void glue(gen_, name)(DisasContext *ctx) \
1027 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1028 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1029 sign, compute_ov); \
1031 /* divwu divwu. divwuo divwuo. */
1032 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0);
1033 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1);
1034 /* divw divw. divwo divwo. */
1035 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0);
1036 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1);
1038 /* div[wd]eu[o][.] */
1039 #define GEN_DIVE(name, hlpr, compute_ov) \
1040 static void gen_##name(DisasContext *ctx) \
1042 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1043 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1044 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1045 tcg_temp_free_i32(t0); \
1046 if (unlikely(Rc(ctx->opcode) != 0)) { \
1047 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1051 GEN_DIVE(divweu
, divweu
, 0);
1052 GEN_DIVE(divweuo
, divweu
, 1);
1053 GEN_DIVE(divwe
, divwe
, 0);
1054 GEN_DIVE(divweo
, divwe
, 1);
1056 #if defined(TARGET_PPC64)
1057 static inline void gen_op_arith_divd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1058 TCGv arg2
, int sign
, int compute_ov
)
1060 TCGv_i64 t0
= tcg_temp_new_i64();
1061 TCGv_i64 t1
= tcg_temp_new_i64();
1062 TCGv_i64 t2
= tcg_temp_new_i64();
1063 TCGv_i64 t3
= tcg_temp_new_i64();
1065 tcg_gen_mov_i64(t0
, arg1
);
1066 tcg_gen_mov_i64(t1
, arg2
);
1068 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t0
, INT64_MIN
);
1069 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, -1);
1070 tcg_gen_and_i64(t2
, t2
, t3
);
1071 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, 0);
1072 tcg_gen_or_i64(t2
, t2
, t3
);
1073 tcg_gen_movi_i64(t3
, 0);
1074 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1075 tcg_gen_div_i64(ret
, t0
, t1
);
1077 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t1
, 0);
1078 tcg_gen_movi_i64(t3
, 0);
1079 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1080 tcg_gen_divu_i64(ret
, t0
, t1
);
1083 tcg_gen_mov_tl(cpu_ov
, t2
);
1084 if (is_isa300(ctx
)) {
1085 tcg_gen_mov_tl(cpu_ov32
, t2
);
1087 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1089 tcg_temp_free_i64(t0
);
1090 tcg_temp_free_i64(t1
);
1091 tcg_temp_free_i64(t2
);
1092 tcg_temp_free_i64(t3
);
1094 if (unlikely(Rc(ctx
->opcode
) != 0))
1095 gen_set_Rc0(ctx
, ret
);
1098 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1099 static void glue(gen_, name)(DisasContext *ctx) \
1101 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1102 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1103 sign, compute_ov); \
1105 /* divdu divdu. divduo divduo. */
1106 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0);
1107 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1);
1108 /* divd divd. divdo divdo. */
1109 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0);
1110 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1);
1112 GEN_DIVE(divdeu
, divdeu
, 0);
1113 GEN_DIVE(divdeuo
, divdeu
, 1);
1114 GEN_DIVE(divde
, divde
, 0);
1115 GEN_DIVE(divdeo
, divde
, 1);
1118 static inline void gen_op_arith_modw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1119 TCGv arg2
, int sign
)
1121 TCGv_i32 t0
= tcg_temp_new_i32();
1122 TCGv_i32 t1
= tcg_temp_new_i32();
1124 tcg_gen_trunc_tl_i32(t0
, arg1
);
1125 tcg_gen_trunc_tl_i32(t1
, arg2
);
1127 TCGv_i32 t2
= tcg_temp_new_i32();
1128 TCGv_i32 t3
= tcg_temp_new_i32();
1129 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
1130 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, -1);
1131 tcg_gen_and_i32(t2
, t2
, t3
);
1132 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, 0);
1133 tcg_gen_or_i32(t2
, t2
, t3
);
1134 tcg_gen_movi_i32(t3
, 0);
1135 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1136 tcg_gen_rem_i32(t3
, t0
, t1
);
1137 tcg_gen_ext_i32_tl(ret
, t3
);
1138 tcg_temp_free_i32(t2
);
1139 tcg_temp_free_i32(t3
);
1141 TCGv_i32 t2
= tcg_const_i32(1);
1142 TCGv_i32 t3
= tcg_const_i32(0);
1143 tcg_gen_movcond_i32(TCG_COND_EQ
, t1
, t1
, t3
, t2
, t1
);
1144 tcg_gen_remu_i32(t3
, t0
, t1
);
1145 tcg_gen_extu_i32_tl(ret
, t3
);
1146 tcg_temp_free_i32(t2
);
1147 tcg_temp_free_i32(t3
);
1149 tcg_temp_free_i32(t0
);
1150 tcg_temp_free_i32(t1
);
1153 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1154 static void glue(gen_, name)(DisasContext *ctx) \
1156 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1157 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1161 GEN_INT_ARITH_MODW(moduw
, 0x08, 0);
1162 GEN_INT_ARITH_MODW(modsw
, 0x18, 1);
1164 #if defined(TARGET_PPC64)
1165 static inline void gen_op_arith_modd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1166 TCGv arg2
, int sign
)
1168 TCGv_i64 t0
= tcg_temp_new_i64();
1169 TCGv_i64 t1
= tcg_temp_new_i64();
1171 tcg_gen_mov_i64(t0
, arg1
);
1172 tcg_gen_mov_i64(t1
, arg2
);
1174 TCGv_i64 t2
= tcg_temp_new_i64();
1175 TCGv_i64 t3
= tcg_temp_new_i64();
1176 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t0
, INT64_MIN
);
1177 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, -1);
1178 tcg_gen_and_i64(t2
, t2
, t3
);
1179 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, 0);
1180 tcg_gen_or_i64(t2
, t2
, t3
);
1181 tcg_gen_movi_i64(t3
, 0);
1182 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1183 tcg_gen_rem_i64(ret
, t0
, t1
);
1184 tcg_temp_free_i64(t2
);
1185 tcg_temp_free_i64(t3
);
1187 TCGv_i64 t2
= tcg_const_i64(1);
1188 TCGv_i64 t3
= tcg_const_i64(0);
1189 tcg_gen_movcond_i64(TCG_COND_EQ
, t1
, t1
, t3
, t2
, t1
);
1190 tcg_gen_remu_i64(ret
, t0
, t1
);
1191 tcg_temp_free_i64(t2
);
1192 tcg_temp_free_i64(t3
);
1194 tcg_temp_free_i64(t0
);
1195 tcg_temp_free_i64(t1
);
1198 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1199 static void glue(gen_, name)(DisasContext *ctx) \
1201 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1202 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1206 GEN_INT_ARITH_MODD(modud
, 0x08, 0);
1207 GEN_INT_ARITH_MODD(modsd
, 0x18, 1);
1211 static void gen_mulhw(DisasContext
*ctx
)
1213 TCGv_i32 t0
= tcg_temp_new_i32();
1214 TCGv_i32 t1
= tcg_temp_new_i32();
1216 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1217 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1218 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1219 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1220 tcg_temp_free_i32(t0
);
1221 tcg_temp_free_i32(t1
);
1222 if (unlikely(Rc(ctx
->opcode
) != 0))
1223 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1226 /* mulhwu mulhwu. */
1227 static void gen_mulhwu(DisasContext
*ctx
)
1229 TCGv_i32 t0
= tcg_temp_new_i32();
1230 TCGv_i32 t1
= tcg_temp_new_i32();
1232 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1233 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1234 tcg_gen_mulu2_i32(t0
, t1
, t0
, t1
);
1235 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1236 tcg_temp_free_i32(t0
);
1237 tcg_temp_free_i32(t1
);
1238 if (unlikely(Rc(ctx
->opcode
) != 0))
1239 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1243 static void gen_mullw(DisasContext
*ctx
)
1245 #if defined(TARGET_PPC64)
1247 t0
= tcg_temp_new_i64();
1248 t1
= tcg_temp_new_i64();
1249 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1250 tcg_gen_ext32s_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1251 tcg_gen_mul_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1255 tcg_gen_mul_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1256 cpu_gpr
[rB(ctx
->opcode
)]);
1258 if (unlikely(Rc(ctx
->opcode
) != 0))
1259 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1262 /* mullwo mullwo. */
1263 static void gen_mullwo(DisasContext
*ctx
)
1265 TCGv_i32 t0
= tcg_temp_new_i32();
1266 TCGv_i32 t1
= tcg_temp_new_i32();
1268 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1269 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1270 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1271 #if defined(TARGET_PPC64)
1272 tcg_gen_concat_i32_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1274 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1277 tcg_gen_sari_i32(t0
, t0
, 31);
1278 tcg_gen_setcond_i32(TCG_COND_NE
, t0
, t0
, t1
);
1279 tcg_gen_extu_i32_tl(cpu_ov
, t0
);
1280 if (is_isa300(ctx
)) {
1281 tcg_gen_mov_tl(cpu_ov32
, cpu_ov
);
1283 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1285 tcg_temp_free_i32(t0
);
1286 tcg_temp_free_i32(t1
);
1287 if (unlikely(Rc(ctx
->opcode
) != 0))
1288 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1292 static void gen_mulli(DisasContext
*ctx
)
1294 tcg_gen_muli_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1298 #if defined(TARGET_PPC64)
1300 static void gen_mulhd(DisasContext
*ctx
)
1302 TCGv lo
= tcg_temp_new();
1303 tcg_gen_muls2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1304 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1306 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1307 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1311 /* mulhdu mulhdu. */
1312 static void gen_mulhdu(DisasContext
*ctx
)
1314 TCGv lo
= tcg_temp_new();
1315 tcg_gen_mulu2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1316 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1318 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1319 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1324 static void gen_mulld(DisasContext
*ctx
)
1326 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1327 cpu_gpr
[rB(ctx
->opcode
)]);
1328 if (unlikely(Rc(ctx
->opcode
) != 0))
1329 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1332 /* mulldo mulldo. */
1333 static void gen_mulldo(DisasContext
*ctx
)
1335 TCGv_i64 t0
= tcg_temp_new_i64();
1336 TCGv_i64 t1
= tcg_temp_new_i64();
1338 tcg_gen_muls2_i64(t0
, t1
, cpu_gpr
[rA(ctx
->opcode
)],
1339 cpu_gpr
[rB(ctx
->opcode
)]);
1340 tcg_gen_mov_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1342 tcg_gen_sari_i64(t0
, t0
, 63);
1343 tcg_gen_setcond_i64(TCG_COND_NE
, cpu_ov
, t0
, t1
);
1344 if (is_isa300(ctx
)) {
1345 tcg_gen_mov_tl(cpu_ov32
, cpu_ov
);
1347 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1349 tcg_temp_free_i64(t0
);
1350 tcg_temp_free_i64(t1
);
1352 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1353 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1358 /* Common subf function */
1359 static inline void gen_op_arith_subf(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1360 TCGv arg2
, bool add_ca
, bool compute_ca
,
1361 bool compute_ov
, bool compute_rc0
)
1365 if (compute_ca
|| compute_ov
) {
1366 t0
= tcg_temp_new();
1370 /* dest = ~arg1 + arg2 [+ ca]. */
1371 if (NARROW_MODE(ctx
)) {
1372 /* Caution: a non-obvious corner case of the spec is that we
1373 must produce the *entire* 64-bit addition, but produce the
1374 carry into bit 32. */
1375 TCGv inv1
= tcg_temp_new();
1376 TCGv t1
= tcg_temp_new();
1377 tcg_gen_not_tl(inv1
, arg1
);
1379 tcg_gen_add_tl(t0
, arg2
, cpu_ca
);
1381 tcg_gen_addi_tl(t0
, arg2
, 1);
1383 tcg_gen_xor_tl(t1
, arg2
, inv1
); /* add without carry */
1384 tcg_gen_add_tl(t0
, t0
, inv1
);
1385 tcg_temp_free(inv1
);
1386 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changes w/ carry */
1388 tcg_gen_extract_tl(cpu_ca
, cpu_ca
, 32, 1);
1389 if (is_isa300(ctx
)) {
1390 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
1392 } else if (add_ca
) {
1393 TCGv zero
, inv1
= tcg_temp_new();
1394 tcg_gen_not_tl(inv1
, arg1
);
1395 zero
= tcg_const_tl(0);
1396 tcg_gen_add2_tl(t0
, cpu_ca
, arg2
, zero
, cpu_ca
, zero
);
1397 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, inv1
, zero
);
1398 gen_op_arith_compute_ca32(ctx
, t0
, inv1
, arg2
, cpu_ca32
, 0);
1399 tcg_temp_free(zero
);
1400 tcg_temp_free(inv1
);
1402 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_ca
, arg2
, arg1
);
1403 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1404 gen_op_arith_compute_ca32(ctx
, t0
, arg1
, arg2
, cpu_ca32
, 1);
1406 } else if (add_ca
) {
1407 /* Since we're ignoring carry-out, we can simplify the
1408 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1409 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1410 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
1411 tcg_gen_subi_tl(t0
, t0
, 1);
1413 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1417 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 1);
1419 if (unlikely(compute_rc0
)) {
1420 gen_set_Rc0(ctx
, t0
);
1424 tcg_gen_mov_tl(ret
, t0
);
1428 /* Sub functions with Two operands functions */
1429 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1430 static void glue(gen_, name)(DisasContext *ctx) \
1432 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1433 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1434 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1436 /* Sub functions with one operand and one immediate */
1437 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1438 add_ca, compute_ca, compute_ov) \
1439 static void glue(gen_, name)(DisasContext *ctx) \
1441 TCGv t0 = tcg_const_tl(const_val); \
1442 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1443 cpu_gpr[rA(ctx->opcode)], t0, \
1444 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1445 tcg_temp_free(t0); \
1447 /* subf subf. subfo subfo. */
1448 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
1449 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
1450 /* subfc subfc. subfco subfco. */
1451 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
1452 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
1453 /* subfe subfe. subfeo subfo. */
1454 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
1455 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
1456 /* subfme subfme. subfmeo subfmeo. */
1457 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
1458 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
1459 /* subfze subfze. subfzeo subfzeo.*/
1460 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
1461 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
1464 static void gen_subfic(DisasContext
*ctx
)
1466 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
1467 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1472 /* neg neg. nego nego. */
1473 static inline void gen_op_arith_neg(DisasContext
*ctx
, bool compute_ov
)
1475 TCGv zero
= tcg_const_tl(0);
1476 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1477 zero
, 0, 0, compute_ov
, Rc(ctx
->opcode
));
1478 tcg_temp_free(zero
);
1481 static void gen_neg(DisasContext
*ctx
)
1483 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
1484 if (unlikely(Rc(ctx
->opcode
))) {
1485 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1489 static void gen_nego(DisasContext
*ctx
)
1491 gen_op_arith_neg(ctx
, 1);
1494 /*** Integer logical ***/
1495 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1496 static void glue(gen_, name)(DisasContext *ctx) \
1498 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1499 cpu_gpr[rB(ctx->opcode)]); \
1500 if (unlikely(Rc(ctx->opcode) != 0)) \
1501 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1504 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1505 static void glue(gen_, name)(DisasContext *ctx) \
1507 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1508 if (unlikely(Rc(ctx->opcode) != 0)) \
1509 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1513 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
);
1515 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
);
1518 static void gen_andi_(DisasContext
*ctx
)
1520 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
));
1521 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1525 static void gen_andis_(DisasContext
*ctx
)
1527 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], UIMM(ctx
->opcode
) << 16);
1528 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1532 static void gen_cntlzw(DisasContext
*ctx
)
1534 TCGv_i32 t
= tcg_temp_new_i32();
1536 tcg_gen_trunc_tl_i32(t
, cpu_gpr
[rS(ctx
->opcode
)]);
1537 tcg_gen_clzi_i32(t
, t
, 32);
1538 tcg_gen_extu_i32_tl(cpu_gpr
[rA(ctx
->opcode
)], t
);
1539 tcg_temp_free_i32(t
);
1541 if (unlikely(Rc(ctx
->opcode
) != 0))
1542 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1546 static void gen_cnttzw(DisasContext
*ctx
)
1548 TCGv_i32 t
= tcg_temp_new_i32();
1550 tcg_gen_trunc_tl_i32(t
, cpu_gpr
[rS(ctx
->opcode
)]);
1551 tcg_gen_ctzi_i32(t
, t
, 32);
1552 tcg_gen_extu_i32_tl(cpu_gpr
[rA(ctx
->opcode
)], t
);
1553 tcg_temp_free_i32(t
);
1555 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1556 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1561 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
);
1562 /* extsb & extsb. */
1563 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
);
1564 /* extsh & extsh. */
1565 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
);
1567 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
);
1569 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
);
1571 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1572 static void gen_pause(DisasContext
*ctx
)
1574 TCGv_i32 t0
= tcg_const_i32(0);
1575 tcg_gen_st_i32(t0
, cpu_env
,
1576 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
1577 tcg_temp_free_i32(t0
);
1579 /* Stop translation, this gives other CPUs a chance to run */
1580 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
1582 #endif /* defined(TARGET_PPC64) */
1585 static void gen_or(DisasContext
*ctx
)
1589 rs
= rS(ctx
->opcode
);
1590 ra
= rA(ctx
->opcode
);
1591 rb
= rB(ctx
->opcode
);
1592 /* Optimisation for mr. ri case */
1593 if (rs
!= ra
|| rs
!= rb
) {
1595 tcg_gen_or_tl(cpu_gpr
[ra
], cpu_gpr
[rs
], cpu_gpr
[rb
]);
1597 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rs
]);
1598 if (unlikely(Rc(ctx
->opcode
) != 0))
1599 gen_set_Rc0(ctx
, cpu_gpr
[ra
]);
1600 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1601 gen_set_Rc0(ctx
, cpu_gpr
[rs
]);
1602 #if defined(TARGET_PPC64)
1603 } else if (rs
!= 0) { /* 0 is nop */
1608 /* Set process priority to low */
1612 /* Set process priority to medium-low */
1616 /* Set process priority to normal */
1619 #if !defined(CONFIG_USER_ONLY)
1622 /* Set process priority to very low */
1628 /* Set process priority to medium-hight */
1634 /* Set process priority to high */
1639 if (ctx
->hv
&& !ctx
->pr
) {
1640 /* Set process priority to very high */
1649 TCGv t0
= tcg_temp_new();
1650 gen_load_spr(t0
, SPR_PPR
);
1651 tcg_gen_andi_tl(t0
, t0
, ~0x001C000000000000ULL
);
1652 tcg_gen_ori_tl(t0
, t0
, ((uint64_t)prio
) << 50);
1653 gen_store_spr(SPR_PPR
, t0
);
1656 #if !defined(CONFIG_USER_ONLY)
1657 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1658 * CPU and the kernel hangs. This applies to all encodings other
1659 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1660 * and all currently undefined.
1668 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
);
1671 static void gen_xor(DisasContext
*ctx
)
1673 /* Optimisation for "set to zero" case */
1674 if (rS(ctx
->opcode
) != rB(ctx
->opcode
))
1675 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1677 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1678 if (unlikely(Rc(ctx
->opcode
) != 0))
1679 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1683 static void gen_ori(DisasContext
*ctx
)
1685 target_ulong uimm
= UIMM(ctx
->opcode
);
1687 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1690 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1694 static void gen_oris(DisasContext
*ctx
)
1696 target_ulong uimm
= UIMM(ctx
->opcode
);
1698 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1702 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1706 static void gen_xori(DisasContext
*ctx
)
1708 target_ulong uimm
= UIMM(ctx
->opcode
);
1710 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1714 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1718 static void gen_xoris(DisasContext
*ctx
)
1720 target_ulong uimm
= UIMM(ctx
->opcode
);
1722 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1726 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
<< 16);
1729 /* popcntb : PowerPC 2.03 specification */
1730 static void gen_popcntb(DisasContext
*ctx
)
1732 gen_helper_popcntb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1735 static void gen_popcntw(DisasContext
*ctx
)
1737 #if defined(TARGET_PPC64)
1738 gen_helper_popcntw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1740 tcg_gen_ctpop_i32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1744 #if defined(TARGET_PPC64)
1745 /* popcntd: PowerPC 2.06 specification */
1746 static void gen_popcntd(DisasContext
*ctx
)
1748 tcg_gen_ctpop_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1752 /* prtyw: PowerPC 2.05 specification */
1753 static void gen_prtyw(DisasContext
*ctx
)
1755 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1756 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1757 TCGv t0
= tcg_temp_new();
1758 tcg_gen_shri_tl(t0
, rs
, 16);
1759 tcg_gen_xor_tl(ra
, rs
, t0
);
1760 tcg_gen_shri_tl(t0
, ra
, 8);
1761 tcg_gen_xor_tl(ra
, ra
, t0
);
1762 tcg_gen_andi_tl(ra
, ra
, (target_ulong
)0x100000001ULL
);
1766 #if defined(TARGET_PPC64)
1767 /* prtyd: PowerPC 2.05 specification */
1768 static void gen_prtyd(DisasContext
*ctx
)
1770 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1771 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1772 TCGv t0
= tcg_temp_new();
1773 tcg_gen_shri_tl(t0
, rs
, 32);
1774 tcg_gen_xor_tl(ra
, rs
, t0
);
1775 tcg_gen_shri_tl(t0
, ra
, 16);
1776 tcg_gen_xor_tl(ra
, ra
, t0
);
1777 tcg_gen_shri_tl(t0
, ra
, 8);
1778 tcg_gen_xor_tl(ra
, ra
, t0
);
1779 tcg_gen_andi_tl(ra
, ra
, 1);
1784 #if defined(TARGET_PPC64)
1786 static void gen_bpermd(DisasContext
*ctx
)
1788 gen_helper_bpermd(cpu_gpr
[rA(ctx
->opcode
)],
1789 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1793 #if defined(TARGET_PPC64)
1794 /* extsw & extsw. */
1795 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
);
1798 static void gen_cntlzd(DisasContext
*ctx
)
1800 tcg_gen_clzi_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], 64);
1801 if (unlikely(Rc(ctx
->opcode
) != 0))
1802 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1806 static void gen_cnttzd(DisasContext
*ctx
)
1808 tcg_gen_ctzi_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], 64);
1809 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1810 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1815 static void gen_darn(DisasContext
*ctx
)
1817 int l
= L(ctx
->opcode
);
1820 gen_helper_darn32(cpu_gpr
[rD(ctx
->opcode
)]);
1821 } else if (l
<= 2) {
1822 /* Return 64-bit random for both CRN and RRN */
1823 gen_helper_darn64(cpu_gpr
[rD(ctx
->opcode
)]);
1825 tcg_gen_movi_i64(cpu_gpr
[rD(ctx
->opcode
)], -1);
1830 /*** Integer rotate ***/
1832 /* rlwimi & rlwimi. */
1833 static void gen_rlwimi(DisasContext
*ctx
)
1835 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1836 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1837 uint32_t sh
= SH(ctx
->opcode
);
1838 uint32_t mb
= MB(ctx
->opcode
);
1839 uint32_t me
= ME(ctx
->opcode
);
1841 if (sh
== (31-me
) && mb
<= me
) {
1842 tcg_gen_deposit_tl(t_ra
, t_ra
, t_rs
, sh
, me
- mb
+ 1);
1847 #if defined(TARGET_PPC64)
1851 mask
= MASK(mb
, me
);
1853 t1
= tcg_temp_new();
1854 if (mask
<= 0xffffffffu
) {
1855 TCGv_i32 t0
= tcg_temp_new_i32();
1856 tcg_gen_trunc_tl_i32(t0
, t_rs
);
1857 tcg_gen_rotli_i32(t0
, t0
, sh
);
1858 tcg_gen_extu_i32_tl(t1
, t0
);
1859 tcg_temp_free_i32(t0
);
1861 #if defined(TARGET_PPC64)
1862 tcg_gen_deposit_i64(t1
, t_rs
, t_rs
, 32, 32);
1863 tcg_gen_rotli_i64(t1
, t1
, sh
);
1865 g_assert_not_reached();
1869 tcg_gen_andi_tl(t1
, t1
, mask
);
1870 tcg_gen_andi_tl(t_ra
, t_ra
, ~mask
);
1871 tcg_gen_or_tl(t_ra
, t_ra
, t1
);
1874 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1875 gen_set_Rc0(ctx
, t_ra
);
1879 /* rlwinm & rlwinm. */
1880 static void gen_rlwinm(DisasContext
*ctx
)
1882 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1883 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1884 int sh
= SH(ctx
->opcode
);
1885 int mb
= MB(ctx
->opcode
);
1886 int me
= ME(ctx
->opcode
);
1887 int len
= me
- mb
+ 1;
1888 int rsh
= (32 - sh
) & 31;
1890 if (sh
!= 0 && len
> 0 && me
== (31 - sh
)) {
1891 tcg_gen_deposit_z_tl(t_ra
, t_rs
, sh
, len
);
1892 } else if (me
== 31 && rsh
+ len
<= 32) {
1893 tcg_gen_extract_tl(t_ra
, t_rs
, rsh
, len
);
1896 #if defined(TARGET_PPC64)
1900 mask
= MASK(mb
, me
);
1902 tcg_gen_andi_tl(t_ra
, t_rs
, mask
);
1903 } else if (mask
<= 0xffffffffu
) {
1904 TCGv_i32 t0
= tcg_temp_new_i32();
1905 tcg_gen_trunc_tl_i32(t0
, t_rs
);
1906 tcg_gen_rotli_i32(t0
, t0
, sh
);
1907 tcg_gen_andi_i32(t0
, t0
, mask
);
1908 tcg_gen_extu_i32_tl(t_ra
, t0
);
1909 tcg_temp_free_i32(t0
);
1911 #if defined(TARGET_PPC64)
1912 tcg_gen_deposit_i64(t_ra
, t_rs
, t_rs
, 32, 32);
1913 tcg_gen_rotli_i64(t_ra
, t_ra
, sh
);
1914 tcg_gen_andi_i64(t_ra
, t_ra
, mask
);
1916 g_assert_not_reached();
1920 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1921 gen_set_Rc0(ctx
, t_ra
);
1925 /* rlwnm & rlwnm. */
1926 static void gen_rlwnm(DisasContext
*ctx
)
1928 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1929 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1930 TCGv t_rb
= cpu_gpr
[rB(ctx
->opcode
)];
1931 uint32_t mb
= MB(ctx
->opcode
);
1932 uint32_t me
= ME(ctx
->opcode
);
1935 #if defined(TARGET_PPC64)
1939 mask
= MASK(mb
, me
);
1941 if (mask
<= 0xffffffffu
) {
1942 TCGv_i32 t0
= tcg_temp_new_i32();
1943 TCGv_i32 t1
= tcg_temp_new_i32();
1944 tcg_gen_trunc_tl_i32(t0
, t_rb
);
1945 tcg_gen_trunc_tl_i32(t1
, t_rs
);
1946 tcg_gen_andi_i32(t0
, t0
, 0x1f);
1947 tcg_gen_rotl_i32(t1
, t1
, t0
);
1948 tcg_gen_extu_i32_tl(t_ra
, t1
);
1949 tcg_temp_free_i32(t0
);
1950 tcg_temp_free_i32(t1
);
1952 #if defined(TARGET_PPC64)
1953 TCGv_i64 t0
= tcg_temp_new_i64();
1954 tcg_gen_andi_i64(t0
, t_rb
, 0x1f);
1955 tcg_gen_deposit_i64(t_ra
, t_rs
, t_rs
, 32, 32);
1956 tcg_gen_rotl_i64(t_ra
, t_ra
, t0
);
1957 tcg_temp_free_i64(t0
);
1959 g_assert_not_reached();
1963 tcg_gen_andi_tl(t_ra
, t_ra
, mask
);
1965 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1966 gen_set_Rc0(ctx
, t_ra
);
1970 #if defined(TARGET_PPC64)
1971 #define GEN_PPC64_R2(name, opc1, opc2) \
1972 static void glue(gen_, name##0)(DisasContext *ctx) \
1974 gen_##name(ctx, 0); \
1977 static void glue(gen_, name##1)(DisasContext *ctx) \
1979 gen_##name(ctx, 1); \
1981 #define GEN_PPC64_R4(name, opc1, opc2) \
1982 static void glue(gen_, name##0)(DisasContext *ctx) \
1984 gen_##name(ctx, 0, 0); \
1987 static void glue(gen_, name##1)(DisasContext *ctx) \
1989 gen_##name(ctx, 0, 1); \
1992 static void glue(gen_, name##2)(DisasContext *ctx) \
1994 gen_##name(ctx, 1, 0); \
1997 static void glue(gen_, name##3)(DisasContext *ctx) \
1999 gen_##name(ctx, 1, 1); \
2002 static void gen_rldinm(DisasContext
*ctx
, int mb
, int me
, int sh
)
2004 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2005 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2006 int len
= me
- mb
+ 1;
2007 int rsh
= (64 - sh
) & 63;
2009 if (sh
!= 0 && len
> 0 && me
== (63 - sh
)) {
2010 tcg_gen_deposit_z_tl(t_ra
, t_rs
, sh
, len
);
2011 } else if (me
== 63 && rsh
+ len
<= 64) {
2012 tcg_gen_extract_tl(t_ra
, t_rs
, rsh
, len
);
2014 tcg_gen_rotli_tl(t_ra
, t_rs
, sh
);
2015 tcg_gen_andi_tl(t_ra
, t_ra
, MASK(mb
, me
));
2017 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2018 gen_set_Rc0(ctx
, t_ra
);
2022 /* rldicl - rldicl. */
2023 static inline void gen_rldicl(DisasContext
*ctx
, int mbn
, int shn
)
2027 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2028 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2029 gen_rldinm(ctx
, mb
, 63, sh
);
2031 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
2033 /* rldicr - rldicr. */
2034 static inline void gen_rldicr(DisasContext
*ctx
, int men
, int shn
)
2038 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2039 me
= MB(ctx
->opcode
) | (men
<< 5);
2040 gen_rldinm(ctx
, 0, me
, sh
);
2042 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
2044 /* rldic - rldic. */
2045 static inline void gen_rldic(DisasContext
*ctx
, int mbn
, int shn
)
2049 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2050 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2051 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
2053 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
2055 static void gen_rldnm(DisasContext
*ctx
, int mb
, int me
)
2057 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2058 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2059 TCGv t_rb
= cpu_gpr
[rB(ctx
->opcode
)];
2062 t0
= tcg_temp_new();
2063 tcg_gen_andi_tl(t0
, t_rb
, 0x3f);
2064 tcg_gen_rotl_tl(t_ra
, t_rs
, t0
);
2067 tcg_gen_andi_tl(t_ra
, t_ra
, MASK(mb
, me
));
2068 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2069 gen_set_Rc0(ctx
, t_ra
);
2073 /* rldcl - rldcl. */
2074 static inline void gen_rldcl(DisasContext
*ctx
, int mbn
)
2078 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2079 gen_rldnm(ctx
, mb
, 63);
2081 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
2083 /* rldcr - rldcr. */
2084 static inline void gen_rldcr(DisasContext
*ctx
, int men
)
2088 me
= MB(ctx
->opcode
) | (men
<< 5);
2089 gen_rldnm(ctx
, 0, me
);
2091 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
2093 /* rldimi - rldimi. */
2094 static void gen_rldimi(DisasContext
*ctx
, int mbn
, int shn
)
2096 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2097 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2098 uint32_t sh
= SH(ctx
->opcode
) | (shn
<< 5);
2099 uint32_t mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2100 uint32_t me
= 63 - sh
;
2103 tcg_gen_deposit_tl(t_ra
, t_ra
, t_rs
, sh
, me
- mb
+ 1);
2105 target_ulong mask
= MASK(mb
, me
);
2106 TCGv t1
= tcg_temp_new();
2108 tcg_gen_rotli_tl(t1
, t_rs
, sh
);
2109 tcg_gen_andi_tl(t1
, t1
, mask
);
2110 tcg_gen_andi_tl(t_ra
, t_ra
, ~mask
);
2111 tcg_gen_or_tl(t_ra
, t_ra
, t1
);
2114 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2115 gen_set_Rc0(ctx
, t_ra
);
2118 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
2121 /*** Integer shift ***/
2124 static void gen_slw(DisasContext
*ctx
)
2128 t0
= tcg_temp_new();
2129 /* AND rS with a mask that is 0 when rB >= 0x20 */
2130 #if defined(TARGET_PPC64)
2131 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
2132 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2134 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
2135 tcg_gen_sari_tl(t0
, t0
, 0x1f);
2137 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2138 t1
= tcg_temp_new();
2139 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
2140 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2143 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
2144 if (unlikely(Rc(ctx
->opcode
) != 0))
2145 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2149 static void gen_sraw(DisasContext
*ctx
)
2151 gen_helper_sraw(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
2152 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2153 if (unlikely(Rc(ctx
->opcode
) != 0))
2154 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2157 /* srawi & srawi. */
2158 static void gen_srawi(DisasContext
*ctx
)
2160 int sh
= SH(ctx
->opcode
);
2161 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2162 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2164 tcg_gen_ext32s_tl(dst
, src
);
2165 tcg_gen_movi_tl(cpu_ca
, 0);
2166 if (is_isa300(ctx
)) {
2167 tcg_gen_movi_tl(cpu_ca32
, 0);
2171 tcg_gen_ext32s_tl(dst
, src
);
2172 tcg_gen_andi_tl(cpu_ca
, dst
, (1ULL << sh
) - 1);
2173 t0
= tcg_temp_new();
2174 tcg_gen_sari_tl(t0
, dst
, TARGET_LONG_BITS
- 1);
2175 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
2177 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
2178 if (is_isa300(ctx
)) {
2179 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
2181 tcg_gen_sari_tl(dst
, dst
, sh
);
2183 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2184 gen_set_Rc0(ctx
, dst
);
2189 static void gen_srw(DisasContext
*ctx
)
2193 t0
= tcg_temp_new();
2194 /* AND rS with a mask that is 0 when rB >= 0x20 */
2195 #if defined(TARGET_PPC64)
2196 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
2197 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2199 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
2200 tcg_gen_sari_tl(t0
, t0
, 0x1f);
2202 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2203 tcg_gen_ext32u_tl(t0
, t0
);
2204 t1
= tcg_temp_new();
2205 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
2206 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2209 if (unlikely(Rc(ctx
->opcode
) != 0))
2210 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2213 #if defined(TARGET_PPC64)
2215 static void gen_sld(DisasContext
*ctx
)
2219 t0
= tcg_temp_new();
2220 /* AND rS with a mask that is 0 when rB >= 0x40 */
2221 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2222 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2223 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2224 t1
= tcg_temp_new();
2225 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2226 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2229 if (unlikely(Rc(ctx
->opcode
) != 0))
2230 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2234 static void gen_srad(DisasContext
*ctx
)
2236 gen_helper_srad(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
2237 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2238 if (unlikely(Rc(ctx
->opcode
) != 0))
2239 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2241 /* sradi & sradi. */
2242 static inline void gen_sradi(DisasContext
*ctx
, int n
)
2244 int sh
= SH(ctx
->opcode
) + (n
<< 5);
2245 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2246 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2248 tcg_gen_mov_tl(dst
, src
);
2249 tcg_gen_movi_tl(cpu_ca
, 0);
2250 if (is_isa300(ctx
)) {
2251 tcg_gen_movi_tl(cpu_ca32
, 0);
2255 tcg_gen_andi_tl(cpu_ca
, src
, (1ULL << sh
) - 1);
2256 t0
= tcg_temp_new();
2257 tcg_gen_sari_tl(t0
, src
, TARGET_LONG_BITS
- 1);
2258 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
2260 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
2261 if (is_isa300(ctx
)) {
2262 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
2264 tcg_gen_sari_tl(dst
, src
, sh
);
2266 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2267 gen_set_Rc0(ctx
, dst
);
2271 static void gen_sradi0(DisasContext
*ctx
)
2276 static void gen_sradi1(DisasContext
*ctx
)
2281 /* extswsli & extswsli. */
2282 static inline void gen_extswsli(DisasContext
*ctx
, int n
)
2284 int sh
= SH(ctx
->opcode
) + (n
<< 5);
2285 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2286 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2288 tcg_gen_ext32s_tl(dst
, src
);
2289 tcg_gen_shli_tl(dst
, dst
, sh
);
2290 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2291 gen_set_Rc0(ctx
, dst
);
2295 static void gen_extswsli0(DisasContext
*ctx
)
2297 gen_extswsli(ctx
, 0);
2300 static void gen_extswsli1(DisasContext
*ctx
)
2302 gen_extswsli(ctx
, 1);
2306 static void gen_srd(DisasContext
*ctx
)
2310 t0
= tcg_temp_new();
2311 /* AND rS with a mask that is 0 when rB >= 0x40 */
2312 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2313 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2314 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2315 t1
= tcg_temp_new();
2316 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2317 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2320 if (unlikely(Rc(ctx
->opcode
) != 0))
2321 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2325 /*** Addressing modes ***/
2326 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2327 static inline void gen_addr_imm_index(DisasContext
*ctx
, TCGv EA
,
2330 target_long simm
= SIMM(ctx
->opcode
);
2333 if (rA(ctx
->opcode
) == 0) {
2334 if (NARROW_MODE(ctx
)) {
2335 simm
= (uint32_t)simm
;
2337 tcg_gen_movi_tl(EA
, simm
);
2338 } else if (likely(simm
!= 0)) {
2339 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], simm
);
2340 if (NARROW_MODE(ctx
)) {
2341 tcg_gen_ext32u_tl(EA
, EA
);
2344 if (NARROW_MODE(ctx
)) {
2345 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2347 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2352 static inline void gen_addr_reg_index(DisasContext
*ctx
, TCGv EA
)
2354 if (rA(ctx
->opcode
) == 0) {
2355 if (NARROW_MODE(ctx
)) {
2356 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2358 tcg_gen_mov_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2361 tcg_gen_add_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2362 if (NARROW_MODE(ctx
)) {
2363 tcg_gen_ext32u_tl(EA
, EA
);
2368 static inline void gen_addr_register(DisasContext
*ctx
, TCGv EA
)
2370 if (rA(ctx
->opcode
) == 0) {
2371 tcg_gen_movi_tl(EA
, 0);
2372 } else if (NARROW_MODE(ctx
)) {
2373 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2375 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2379 static inline void gen_addr_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
2382 tcg_gen_addi_tl(ret
, arg1
, val
);
2383 if (NARROW_MODE(ctx
)) {
2384 tcg_gen_ext32u_tl(ret
, ret
);
2388 static inline void gen_align_no_le(DisasContext
*ctx
)
2390 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
,
2391 (ctx
->opcode
& 0x03FF0000) | POWERPC_EXCP_ALIGN_LE
);
2394 /*** Integer load ***/
2395 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2396 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2398 #define GEN_QEMU_LOAD_TL(ldop, op) \
2399 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2403 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2406 GEN_QEMU_LOAD_TL(ld8u
, DEF_MEMOP(MO_UB
))
2407 GEN_QEMU_LOAD_TL(ld16u
, DEF_MEMOP(MO_UW
))
2408 GEN_QEMU_LOAD_TL(ld16s
, DEF_MEMOP(MO_SW
))
2409 GEN_QEMU_LOAD_TL(ld32u
, DEF_MEMOP(MO_UL
))
2410 GEN_QEMU_LOAD_TL(ld32s
, DEF_MEMOP(MO_SL
))
2412 GEN_QEMU_LOAD_TL(ld16ur
, BSWAP_MEMOP(MO_UW
))
2413 GEN_QEMU_LOAD_TL(ld32ur
, BSWAP_MEMOP(MO_UL
))
2415 #define GEN_QEMU_LOAD_64(ldop, op) \
2416 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2420 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2423 GEN_QEMU_LOAD_64(ld8u
, DEF_MEMOP(MO_UB
))
2424 GEN_QEMU_LOAD_64(ld16u
, DEF_MEMOP(MO_UW
))
2425 GEN_QEMU_LOAD_64(ld32u
, DEF_MEMOP(MO_UL
))
2426 GEN_QEMU_LOAD_64(ld32s
, DEF_MEMOP(MO_SL
))
2427 GEN_QEMU_LOAD_64(ld64
, DEF_MEMOP(MO_Q
))
2429 #if defined(TARGET_PPC64)
2430 GEN_QEMU_LOAD_64(ld64ur
, BSWAP_MEMOP(MO_Q
))
2433 #define GEN_QEMU_STORE_TL(stop, op) \
2434 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2438 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2441 GEN_QEMU_STORE_TL(st8
, DEF_MEMOP(MO_UB
))
2442 GEN_QEMU_STORE_TL(st16
, DEF_MEMOP(MO_UW
))
2443 GEN_QEMU_STORE_TL(st32
, DEF_MEMOP(MO_UL
))
2445 GEN_QEMU_STORE_TL(st16r
, BSWAP_MEMOP(MO_UW
))
2446 GEN_QEMU_STORE_TL(st32r
, BSWAP_MEMOP(MO_UL
))
2448 #define GEN_QEMU_STORE_64(stop, op) \
2449 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2453 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2456 GEN_QEMU_STORE_64(st8
, DEF_MEMOP(MO_UB
))
2457 GEN_QEMU_STORE_64(st16
, DEF_MEMOP(MO_UW
))
2458 GEN_QEMU_STORE_64(st32
, DEF_MEMOP(MO_UL
))
2459 GEN_QEMU_STORE_64(st64
, DEF_MEMOP(MO_Q
))
2461 #if defined(TARGET_PPC64)
2462 GEN_QEMU_STORE_64(st64r
, BSWAP_MEMOP(MO_Q
))
2465 #define GEN_LD(name, ldop, opc, type) \
2466 static void glue(gen_, name)(DisasContext *ctx) \
2469 gen_set_access_type(ctx, ACCESS_INT); \
2470 EA = tcg_temp_new(); \
2471 gen_addr_imm_index(ctx, EA, 0); \
2472 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2473 tcg_temp_free(EA); \
2476 #define GEN_LDU(name, ldop, opc, type) \
2477 static void glue(gen_, name##u)(DisasContext *ctx) \
2480 if (unlikely(rA(ctx->opcode) == 0 || \
2481 rA(ctx->opcode) == rD(ctx->opcode))) { \
2482 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2485 gen_set_access_type(ctx, ACCESS_INT); \
2486 EA = tcg_temp_new(); \
2487 if (type == PPC_64B) \
2488 gen_addr_imm_index(ctx, EA, 0x03); \
2490 gen_addr_imm_index(ctx, EA, 0); \
2491 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2492 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2493 tcg_temp_free(EA); \
2496 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2497 static void glue(gen_, name##ux)(DisasContext *ctx) \
2500 if (unlikely(rA(ctx->opcode) == 0 || \
2501 rA(ctx->opcode) == rD(ctx->opcode))) { \
2502 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2505 gen_set_access_type(ctx, ACCESS_INT); \
2506 EA = tcg_temp_new(); \
2507 gen_addr_reg_index(ctx, EA); \
2508 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2509 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2510 tcg_temp_free(EA); \
2513 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2514 static void glue(gen_, name##x)(DisasContext *ctx) \
2518 gen_set_access_type(ctx, ACCESS_INT); \
2519 EA = tcg_temp_new(); \
2520 gen_addr_reg_index(ctx, EA); \
2521 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2522 tcg_temp_free(EA); \
2525 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2526 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2528 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2529 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2531 #define GEN_LDS(name, ldop, op, type) \
2532 GEN_LD(name, ldop, op | 0x20, type); \
2533 GEN_LDU(name, ldop, op | 0x21, type); \
2534 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2535 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2537 /* lbz lbzu lbzux lbzx */
2538 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
);
2539 /* lha lhau lhaux lhax */
2540 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
);
2541 /* lhz lhzu lhzux lhzx */
2542 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
);
2543 /* lwz lwzu lwzux lwzx */
2544 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
);
2546 #define GEN_LDEPX(name, ldop, opc2, opc3) \
2547 static void glue(gen_, name##epx)(DisasContext *ctx) \
2551 gen_set_access_type(ctx, ACCESS_INT); \
2552 EA = tcg_temp_new(); \
2553 gen_addr_reg_index(ctx, EA); \
2554 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\
2555 tcg_temp_free(EA); \
2558 GEN_LDEPX(lb
, DEF_MEMOP(MO_UB
), 0x1F, 0x02)
2559 GEN_LDEPX(lh
, DEF_MEMOP(MO_UW
), 0x1F, 0x08)
2560 GEN_LDEPX(lw
, DEF_MEMOP(MO_UL
), 0x1F, 0x00)
2561 #if defined(TARGET_PPC64)
2562 GEN_LDEPX(ld
, DEF_MEMOP(MO_Q
), 0x1D, 0x00)
2565 #if defined(TARGET_PPC64)
2567 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
);
2569 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
);
2571 GEN_LDUX(ld
, ld64_i64
, 0x15, 0x01, PPC_64B
);
2573 GEN_LDX(ld
, ld64_i64
, 0x15, 0x00, PPC_64B
);
2575 /* CI load/store variants */
2576 GEN_LDX_HVRM(ldcix
, ld64_i64
, 0x15, 0x1b, PPC_CILDST
)
2577 GEN_LDX_HVRM(lwzcix
, ld32u
, 0x15, 0x15, PPC_CILDST
)
2578 GEN_LDX_HVRM(lhzcix
, ld16u
, 0x15, 0x19, PPC_CILDST
)
2579 GEN_LDX_HVRM(lbzcix
, ld8u
, 0x15, 0x1a, PPC_CILDST
)
2581 static void gen_ld(DisasContext
*ctx
)
2584 if (Rc(ctx
->opcode
)) {
2585 if (unlikely(rA(ctx
->opcode
) == 0 ||
2586 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2587 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2591 gen_set_access_type(ctx
, ACCESS_INT
);
2592 EA
= tcg_temp_new();
2593 gen_addr_imm_index(ctx
, EA
, 0x03);
2594 if (ctx
->opcode
& 0x02) {
2595 /* lwa (lwau is undefined) */
2596 gen_qemu_ld32s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2599 gen_qemu_ld64_i64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2601 if (Rc(ctx
->opcode
))
2602 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2607 static void gen_lq(DisasContext
*ctx
)
2612 /* lq is a legal user mode instruction starting in ISA 2.07 */
2613 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2614 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2616 if (!legal_in_user_mode
&& ctx
->pr
) {
2617 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2621 if (!le_is_supported
&& ctx
->le_mode
) {
2622 gen_align_no_le(ctx
);
2625 ra
= rA(ctx
->opcode
);
2626 rd
= rD(ctx
->opcode
);
2627 if (unlikely((rd
& 1) || rd
== ra
)) {
2628 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2632 gen_set_access_type(ctx
, ACCESS_INT
);
2633 EA
= tcg_temp_new();
2634 gen_addr_imm_index(ctx
, EA
, 0x0F);
2636 /* Note that the low part is always in RD+1, even in LE mode. */
2637 lo
= cpu_gpr
[rd
+ 1];
2640 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
2641 if (HAVE_ATOMIC128
) {
2642 TCGv_i32 oi
= tcg_temp_new_i32();
2644 tcg_gen_movi_i32(oi
, make_memop_idx(MO_LEQ
, ctx
->mem_idx
));
2645 gen_helper_lq_le_parallel(lo
, cpu_env
, EA
, oi
);
2647 tcg_gen_movi_i32(oi
, make_memop_idx(MO_BEQ
, ctx
->mem_idx
));
2648 gen_helper_lq_be_parallel(lo
, cpu_env
, EA
, oi
);
2650 tcg_temp_free_i32(oi
);
2651 tcg_gen_ld_i64(hi
, cpu_env
, offsetof(CPUPPCState
, retxh
));
2653 /* Restart with exclusive lock. */
2654 gen_helper_exit_atomic(cpu_env
);
2655 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2657 } else if (ctx
->le_mode
) {
2658 tcg_gen_qemu_ld_i64(lo
, EA
, ctx
->mem_idx
, MO_LEQ
);
2659 gen_addr_add(ctx
, EA
, EA
, 8);
2660 tcg_gen_qemu_ld_i64(hi
, EA
, ctx
->mem_idx
, MO_LEQ
);
2662 tcg_gen_qemu_ld_i64(hi
, EA
, ctx
->mem_idx
, MO_BEQ
);
2663 gen_addr_add(ctx
, EA
, EA
, 8);
2664 tcg_gen_qemu_ld_i64(lo
, EA
, ctx
->mem_idx
, MO_BEQ
);
2670 /*** Integer store ***/
2671 #define GEN_ST(name, stop, opc, type) \
2672 static void glue(gen_, name)(DisasContext *ctx) \
2675 gen_set_access_type(ctx, ACCESS_INT); \
2676 EA = tcg_temp_new(); \
2677 gen_addr_imm_index(ctx, EA, 0); \
2678 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2679 tcg_temp_free(EA); \
2682 #define GEN_STU(name, stop, opc, type) \
2683 static void glue(gen_, stop##u)(DisasContext *ctx) \
2686 if (unlikely(rA(ctx->opcode) == 0)) { \
2687 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2690 gen_set_access_type(ctx, ACCESS_INT); \
2691 EA = tcg_temp_new(); \
2692 if (type == PPC_64B) \
2693 gen_addr_imm_index(ctx, EA, 0x03); \
2695 gen_addr_imm_index(ctx, EA, 0); \
2696 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2697 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2698 tcg_temp_free(EA); \
2701 #define GEN_STUX(name, stop, opc2, opc3, type) \
2702 static void glue(gen_, name##ux)(DisasContext *ctx) \
2705 if (unlikely(rA(ctx->opcode) == 0)) { \
2706 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2709 gen_set_access_type(ctx, ACCESS_INT); \
2710 EA = tcg_temp_new(); \
2711 gen_addr_reg_index(ctx, EA); \
2712 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2713 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2714 tcg_temp_free(EA); \
2717 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2718 static void glue(gen_, name##x)(DisasContext *ctx) \
2722 gen_set_access_type(ctx, ACCESS_INT); \
2723 EA = tcg_temp_new(); \
2724 gen_addr_reg_index(ctx, EA); \
2725 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2726 tcg_temp_free(EA); \
2728 #define GEN_STX(name, stop, opc2, opc3, type) \
2729 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2731 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2732 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2734 #define GEN_STS(name, stop, op, type) \
2735 GEN_ST(name, stop, op | 0x20, type); \
2736 GEN_STU(name, stop, op | 0x21, type); \
2737 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2738 GEN_STX(name, stop, 0x17, op | 0x00, type)
2740 /* stb stbu stbux stbx */
2741 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
);
2742 /* sth sthu sthux sthx */
2743 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
);
2744 /* stw stwu stwux stwx */
2745 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
);
2747 #define GEN_STEPX(name, stop, opc2, opc3) \
2748 static void glue(gen_, name##epx)(DisasContext *ctx) \
2752 gen_set_access_type(ctx, ACCESS_INT); \
2753 EA = tcg_temp_new(); \
2754 gen_addr_reg_index(ctx, EA); \
2755 tcg_gen_qemu_st_tl( \
2756 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \
2757 tcg_temp_free(EA); \
2760 GEN_STEPX(stb
, DEF_MEMOP(MO_UB
), 0x1F, 0x06)
2761 GEN_STEPX(sth
, DEF_MEMOP(MO_UW
), 0x1F, 0x0C)
2762 GEN_STEPX(stw
, DEF_MEMOP(MO_UL
), 0x1F, 0x04)
2763 #if defined(TARGET_PPC64)
2764 GEN_STEPX(std
, DEF_MEMOP(MO_Q
), 0x1d, 0x04)
2767 #if defined(TARGET_PPC64)
2768 GEN_STUX(std
, st64_i64
, 0x15, 0x05, PPC_64B
);
2769 GEN_STX(std
, st64_i64
, 0x15, 0x04, PPC_64B
);
2770 GEN_STX_HVRM(stdcix
, st64_i64
, 0x15, 0x1f, PPC_CILDST
)
2771 GEN_STX_HVRM(stwcix
, st32
, 0x15, 0x1c, PPC_CILDST
)
2772 GEN_STX_HVRM(sthcix
, st16
, 0x15, 0x1d, PPC_CILDST
)
2773 GEN_STX_HVRM(stbcix
, st8
, 0x15, 0x1e, PPC_CILDST
)
2775 static void gen_std(DisasContext
*ctx
)
2780 rs
= rS(ctx
->opcode
);
2781 if ((ctx
->opcode
& 0x3) == 0x2) { /* stq */
2782 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2783 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2786 if (!(ctx
->insns_flags
& PPC_64BX
)) {
2787 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2790 if (!legal_in_user_mode
&& ctx
->pr
) {
2791 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2795 if (!le_is_supported
&& ctx
->le_mode
) {
2796 gen_align_no_le(ctx
);
2800 if (unlikely(rs
& 1)) {
2801 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2804 gen_set_access_type(ctx
, ACCESS_INT
);
2805 EA
= tcg_temp_new();
2806 gen_addr_imm_index(ctx
, EA
, 0x03);
2808 /* Note that the low part is always in RS+1, even in LE mode. */
2809 lo
= cpu_gpr
[rs
+ 1];
2812 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
2813 if (HAVE_ATOMIC128
) {
2814 TCGv_i32 oi
= tcg_temp_new_i32();
2816 tcg_gen_movi_i32(oi
, make_memop_idx(MO_LEQ
, ctx
->mem_idx
));
2817 gen_helper_stq_le_parallel(cpu_env
, EA
, lo
, hi
, oi
);
2819 tcg_gen_movi_i32(oi
, make_memop_idx(MO_BEQ
, ctx
->mem_idx
));
2820 gen_helper_stq_be_parallel(cpu_env
, EA
, lo
, hi
, oi
);
2822 tcg_temp_free_i32(oi
);
2824 /* Restart with exclusive lock. */
2825 gen_helper_exit_atomic(cpu_env
);
2826 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2828 } else if (ctx
->le_mode
) {
2829 tcg_gen_qemu_st_i64(lo
, EA
, ctx
->mem_idx
, MO_LEQ
);
2830 gen_addr_add(ctx
, EA
, EA
, 8);
2831 tcg_gen_qemu_st_i64(hi
, EA
, ctx
->mem_idx
, MO_LEQ
);
2833 tcg_gen_qemu_st_i64(hi
, EA
, ctx
->mem_idx
, MO_BEQ
);
2834 gen_addr_add(ctx
, EA
, EA
, 8);
2835 tcg_gen_qemu_st_i64(lo
, EA
, ctx
->mem_idx
, MO_BEQ
);
2840 if (Rc(ctx
->opcode
)) {
2841 if (unlikely(rA(ctx
->opcode
) == 0)) {
2842 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2846 gen_set_access_type(ctx
, ACCESS_INT
);
2847 EA
= tcg_temp_new();
2848 gen_addr_imm_index(ctx
, EA
, 0x03);
2849 gen_qemu_st64_i64(ctx
, cpu_gpr
[rs
], EA
);
2850 if (Rc(ctx
->opcode
))
2851 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2856 /*** Integer load and store with byte reverse ***/
2859 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
);
2862 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
);
2864 #if defined(TARGET_PPC64)
2866 GEN_LDX_E(ldbr
, ld64ur_i64
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
, CHK_NONE
);
2868 GEN_STX_E(stdbr
, st64r_i64
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
, CHK_NONE
);
2869 #endif /* TARGET_PPC64 */
2872 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
);
2874 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
);
2876 /*** Integer load and store multiple ***/
2879 static void gen_lmw(DisasContext
*ctx
)
2885 gen_align_no_le(ctx
);
2888 gen_set_access_type(ctx
, ACCESS_INT
);
2889 t0
= tcg_temp_new();
2890 t1
= tcg_const_i32(rD(ctx
->opcode
));
2891 gen_addr_imm_index(ctx
, t0
, 0);
2892 gen_helper_lmw(cpu_env
, t0
, t1
);
2894 tcg_temp_free_i32(t1
);
2898 static void gen_stmw(DisasContext
*ctx
)
2904 gen_align_no_le(ctx
);
2907 gen_set_access_type(ctx
, ACCESS_INT
);
2908 t0
= tcg_temp_new();
2909 t1
= tcg_const_i32(rS(ctx
->opcode
));
2910 gen_addr_imm_index(ctx
, t0
, 0);
2911 gen_helper_stmw(cpu_env
, t0
, t1
);
2913 tcg_temp_free_i32(t1
);
2916 /*** Integer load and store strings ***/
2919 /* PowerPC32 specification says we must generate an exception if
2920 * rA is in the range of registers to be loaded.
2921 * In an other hand, IBM says this is valid, but rA won't be loaded.
2922 * For now, I'll follow the spec...
2924 static void gen_lswi(DisasContext
*ctx
)
2928 int nb
= NB(ctx
->opcode
);
2929 int start
= rD(ctx
->opcode
);
2930 int ra
= rA(ctx
->opcode
);
2934 gen_align_no_le(ctx
);
2939 nr
= DIV_ROUND_UP(nb
, 4);
2940 if (unlikely(lsw_reg_in_range(start
, nr
, ra
))) {
2941 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
2944 gen_set_access_type(ctx
, ACCESS_INT
);
2945 t0
= tcg_temp_new();
2946 gen_addr_register(ctx
, t0
);
2947 t1
= tcg_const_i32(nb
);
2948 t2
= tcg_const_i32(start
);
2949 gen_helper_lsw(cpu_env
, t0
, t1
, t2
);
2951 tcg_temp_free_i32(t1
);
2952 tcg_temp_free_i32(t2
);
2956 static void gen_lswx(DisasContext
*ctx
)
2959 TCGv_i32 t1
, t2
, t3
;
2962 gen_align_no_le(ctx
);
2965 gen_set_access_type(ctx
, ACCESS_INT
);
2966 t0
= tcg_temp_new();
2967 gen_addr_reg_index(ctx
, t0
);
2968 t1
= tcg_const_i32(rD(ctx
->opcode
));
2969 t2
= tcg_const_i32(rA(ctx
->opcode
));
2970 t3
= tcg_const_i32(rB(ctx
->opcode
));
2971 gen_helper_lswx(cpu_env
, t0
, t1
, t2
, t3
);
2973 tcg_temp_free_i32(t1
);
2974 tcg_temp_free_i32(t2
);
2975 tcg_temp_free_i32(t3
);
2979 static void gen_stswi(DisasContext
*ctx
)
2983 int nb
= NB(ctx
->opcode
);
2986 gen_align_no_le(ctx
);
2989 gen_set_access_type(ctx
, ACCESS_INT
);
2990 t0
= tcg_temp_new();
2991 gen_addr_register(ctx
, t0
);
2994 t1
= tcg_const_i32(nb
);
2995 t2
= tcg_const_i32(rS(ctx
->opcode
));
2996 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
2998 tcg_temp_free_i32(t1
);
2999 tcg_temp_free_i32(t2
);
3003 static void gen_stswx(DisasContext
*ctx
)
3009 gen_align_no_le(ctx
);
3012 gen_set_access_type(ctx
, ACCESS_INT
);
3013 t0
= tcg_temp_new();
3014 gen_addr_reg_index(ctx
, t0
);
3015 t1
= tcg_temp_new_i32();
3016 tcg_gen_trunc_tl_i32(t1
, cpu_xer
);
3017 tcg_gen_andi_i32(t1
, t1
, 0x7F);
3018 t2
= tcg_const_i32(rS(ctx
->opcode
));
3019 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
3021 tcg_temp_free_i32(t1
);
3022 tcg_temp_free_i32(t2
);
3025 /*** Memory synchronisation ***/
3027 static void gen_eieio(DisasContext
*ctx
)
3029 TCGBar bar
= TCG_MO_LD_ST
;
3032 * POWER9 has a eieio instruction variant using bit 6 as a hint to
3033 * tell the CPU it is a store-forwarding barrier.
3035 if (ctx
->opcode
& 0x2000000) {
3037 * ISA says that "Reserved fields in instructions are ignored
3038 * by the processor". So ignore the bit 6 on non-POWER9 CPU but
3039 * as this is not an instruction software should be using,
3040 * complain to the user.
3042 if (!(ctx
->insns_flags2
& PPC2_ISA300
)) {
3043 qemu_log_mask(LOG_GUEST_ERROR
, "invalid eieio using bit 6 at @"
3044 TARGET_FMT_lx
"\n", ctx
->base
.pc_next
- 4);
3050 tcg_gen_mb(bar
| TCG_BAR_SC
);
3053 #if !defined(CONFIG_USER_ONLY)
3054 static inline void gen_check_tlb_flush(DisasContext
*ctx
, bool global
)
3059 if (!ctx
->lazy_tlb_flush
) {
3062 l
= gen_new_label();
3063 t
= tcg_temp_new_i32();
3064 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
3065 tcg_gen_brcondi_i32(TCG_COND_EQ
, t
, 0, l
);
3067 gen_helper_check_tlb_flush_global(cpu_env
);
3069 gen_helper_check_tlb_flush_local(cpu_env
);
3072 tcg_temp_free_i32(t
);
3075 static inline void gen_check_tlb_flush(DisasContext
*ctx
, bool global
) { }
3079 static void gen_isync(DisasContext
*ctx
)
3082 * We need to check for a pending TLB flush. This can only happen in
3083 * kernel mode however so check MSR_PR
3086 gen_check_tlb_flush(ctx
, false);
3088 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
3089 gen_stop_exception(ctx
);
3092 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3094 static void gen_load_locked(DisasContext
*ctx
, TCGMemOp memop
)
3096 TCGv gpr
= cpu_gpr
[rD(ctx
->opcode
)];
3097 TCGv t0
= tcg_temp_new();
3099 gen_set_access_type(ctx
, ACCESS_RES
);
3100 gen_addr_reg_index(ctx
, t0
);
3101 tcg_gen_qemu_ld_tl(gpr
, t0
, ctx
->mem_idx
, memop
| MO_ALIGN
);
3102 tcg_gen_mov_tl(cpu_reserve
, t0
);
3103 tcg_gen_mov_tl(cpu_reserve_val
, gpr
);
3104 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3108 #define LARX(name, memop) \
3109 static void gen_##name(DisasContext *ctx) \
3111 gen_load_locked(ctx, memop); \
3115 LARX(lbarx
, DEF_MEMOP(MO_UB
))
3116 LARX(lharx
, DEF_MEMOP(MO_UW
))
3117 LARX(lwarx
, DEF_MEMOP(MO_UL
))
3119 static void gen_fetch_inc_conditional(DisasContext
*ctx
, TCGMemOp memop
,
3120 TCGv EA
, TCGCond cond
, int addend
)
3122 TCGv t
= tcg_temp_new();
3123 TCGv t2
= tcg_temp_new();
3124 TCGv u
= tcg_temp_new();
3126 tcg_gen_qemu_ld_tl(t
, EA
, ctx
->mem_idx
, memop
);
3127 tcg_gen_addi_tl(t2
, EA
, MEMOP_GET_SIZE(memop
));
3128 tcg_gen_qemu_ld_tl(t2
, t2
, ctx
->mem_idx
, memop
);
3129 tcg_gen_addi_tl(u
, t
, addend
);
3131 /* E.g. for fetch and increment bounded... */
3132 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */
3133 tcg_gen_movcond_tl(cond
, u
, t
, t2
, u
, t
);
3134 tcg_gen_qemu_st_tl(u
, EA
, ctx
->mem_idx
, memop
);
3136 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
3137 tcg_gen_movi_tl(u
, 1 << (MEMOP_GET_SIZE(memop
) * 8 - 1));
3138 tcg_gen_movcond_tl(cond
, cpu_gpr
[rD(ctx
->opcode
)], t
, t2
, t
, u
);
3145 static void gen_ld_atomic(DisasContext
*ctx
, TCGMemOp memop
)
3147 uint32_t gpr_FC
= FC(ctx
->opcode
);
3148 TCGv EA
= tcg_temp_new();
3149 int rt
= rD(ctx
->opcode
);
3153 gen_addr_register(ctx
, EA
);
3155 src
= cpu_gpr
[(rt
+ 1) & 31];
3157 need_serial
= false;
3160 case 0: /* Fetch and add */
3161 tcg_gen_atomic_fetch_add_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3163 case 1: /* Fetch and xor */
3164 tcg_gen_atomic_fetch_xor_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3166 case 2: /* Fetch and or */
3167 tcg_gen_atomic_fetch_or_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3169 case 3: /* Fetch and 'and' */
3170 tcg_gen_atomic_fetch_and_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3172 case 4: /* Fetch and max unsigned */
3173 tcg_gen_atomic_fetch_umax_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3175 case 5: /* Fetch and max signed */
3176 tcg_gen_atomic_fetch_smax_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3178 case 6: /* Fetch and min unsigned */
3179 tcg_gen_atomic_fetch_umin_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3181 case 7: /* Fetch and min signed */
3182 tcg_gen_atomic_fetch_smin_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3185 tcg_gen_atomic_xchg_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3188 case 16: /* Compare and swap not equal */
3189 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3192 TCGv t0
= tcg_temp_new();
3193 TCGv t1
= tcg_temp_new();
3195 tcg_gen_qemu_ld_tl(t0
, EA
, ctx
->mem_idx
, memop
);
3196 if ((memop
& MO_SIZE
) == MO_64
|| TARGET_LONG_BITS
== 32) {
3197 tcg_gen_mov_tl(t1
, src
);
3199 tcg_gen_ext32u_tl(t1
, src
);
3201 tcg_gen_movcond_tl(TCG_COND_NE
, t1
, t0
, t1
,
3202 cpu_gpr
[(rt
+ 2) & 31], t0
);
3203 tcg_gen_qemu_st_tl(t1
, EA
, ctx
->mem_idx
, memop
);
3204 tcg_gen_mov_tl(dst
, t0
);
3211 case 24: /* Fetch and increment bounded */
3212 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3215 gen_fetch_inc_conditional(ctx
, memop
, EA
, TCG_COND_NE
, 1);
3218 case 25: /* Fetch and increment equal */
3219 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3222 gen_fetch_inc_conditional(ctx
, memop
, EA
, TCG_COND_EQ
, 1);
3225 case 28: /* Fetch and decrement bounded */
3226 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3229 gen_fetch_inc_conditional(ctx
, memop
, EA
, TCG_COND_NE
, -1);
3234 /* invoke data storage error handler */
3235 gen_exception_err(ctx
, POWERPC_EXCP_DSI
, POWERPC_EXCP_INVAL
);
3240 /* Restart with exclusive lock. */
3241 gen_helper_exit_atomic(cpu_env
);
3242 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3246 static void gen_lwat(DisasContext
*ctx
)
3248 gen_ld_atomic(ctx
, DEF_MEMOP(MO_UL
));
3252 static void gen_ldat(DisasContext
*ctx
)
3254 gen_ld_atomic(ctx
, DEF_MEMOP(MO_Q
));
3258 static void gen_st_atomic(DisasContext
*ctx
, TCGMemOp memop
)
3260 uint32_t gpr_FC
= FC(ctx
->opcode
);
3261 TCGv EA
= tcg_temp_new();
3264 gen_addr_register(ctx
, EA
);
3265 src
= cpu_gpr
[rD(ctx
->opcode
)];
3266 discard
= tcg_temp_new();
3270 case 0: /* add and Store */
3271 tcg_gen_atomic_add_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3273 case 1: /* xor and Store */
3274 tcg_gen_atomic_xor_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3276 case 2: /* Or and Store */
3277 tcg_gen_atomic_or_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3279 case 3: /* 'and' and Store */
3280 tcg_gen_atomic_and_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3282 case 4: /* Store max unsigned */
3283 tcg_gen_atomic_umax_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3285 case 5: /* Store max signed */
3286 tcg_gen_atomic_smax_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3288 case 6: /* Store min unsigned */
3289 tcg_gen_atomic_umin_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3291 case 7: /* Store min signed */
3292 tcg_gen_atomic_smin_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3294 case 24: /* Store twin */
3295 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3296 /* Restart with exclusive lock. */
3297 gen_helper_exit_atomic(cpu_env
);
3298 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3300 TCGv t
= tcg_temp_new();
3301 TCGv t2
= tcg_temp_new();
3302 TCGv s
= tcg_temp_new();
3303 TCGv s2
= tcg_temp_new();
3304 TCGv ea_plus_s
= tcg_temp_new();
3306 tcg_gen_qemu_ld_tl(t
, EA
, ctx
->mem_idx
, memop
);
3307 tcg_gen_addi_tl(ea_plus_s
, EA
, MEMOP_GET_SIZE(memop
));
3308 tcg_gen_qemu_ld_tl(t2
, ea_plus_s
, ctx
->mem_idx
, memop
);
3309 tcg_gen_movcond_tl(TCG_COND_EQ
, s
, t
, t2
, src
, t
);
3310 tcg_gen_movcond_tl(TCG_COND_EQ
, s2
, t
, t2
, src
, t2
);
3311 tcg_gen_qemu_st_tl(s
, EA
, ctx
->mem_idx
, memop
);
3312 tcg_gen_qemu_st_tl(s2
, ea_plus_s
, ctx
->mem_idx
, memop
);
3314 tcg_temp_free(ea_plus_s
);
3322 /* invoke data storage error handler */
3323 gen_exception_err(ctx
, POWERPC_EXCP_DSI
, POWERPC_EXCP_INVAL
);
3325 tcg_temp_free(discard
);
3329 static void gen_stwat(DisasContext
*ctx
)
3331 gen_st_atomic(ctx
, DEF_MEMOP(MO_UL
));
3335 static void gen_stdat(DisasContext
*ctx
)
3337 gen_st_atomic(ctx
, DEF_MEMOP(MO_Q
));
3341 static void gen_conditional_store(DisasContext
*ctx
, TCGMemOp memop
)
3343 TCGLabel
*l1
= gen_new_label();
3344 TCGLabel
*l2
= gen_new_label();
3345 TCGv t0
= tcg_temp_new();
3346 int reg
= rS(ctx
->opcode
);
3348 gen_set_access_type(ctx
, ACCESS_RES
);
3349 gen_addr_reg_index(ctx
, t0
);
3350 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, cpu_reserve
, l1
);
3353 t0
= tcg_temp_new();
3354 tcg_gen_atomic_cmpxchg_tl(t0
, cpu_reserve
, cpu_reserve_val
,
3355 cpu_gpr
[reg
], ctx
->mem_idx
,
3356 DEF_MEMOP(memop
) | MO_ALIGN
);
3357 tcg_gen_setcond_tl(TCG_COND_EQ
, t0
, t0
, cpu_reserve_val
);
3358 tcg_gen_shli_tl(t0
, t0
, CRF_EQ_BIT
);
3359 tcg_gen_or_tl(t0
, t0
, cpu_so
);
3360 tcg_gen_trunc_tl_i32(cpu_crf
[0], t0
);
3366 /* Address mismatch implies failure. But we still need to provide the
3367 memory barrier semantics of the instruction. */
3368 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3369 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3372 tcg_gen_movi_tl(cpu_reserve
, -1);
3375 #define STCX(name, memop) \
3376 static void gen_##name(DisasContext *ctx) \
3378 gen_conditional_store(ctx, memop); \
3381 STCX(stbcx_
, DEF_MEMOP(MO_UB
))
3382 STCX(sthcx_
, DEF_MEMOP(MO_UW
))
3383 STCX(stwcx_
, DEF_MEMOP(MO_UL
))
3385 #if defined(TARGET_PPC64)
3387 LARX(ldarx
, DEF_MEMOP(MO_Q
))
3389 STCX(stdcx_
, DEF_MEMOP(MO_Q
))
3392 static void gen_lqarx(DisasContext
*ctx
)
3394 int rd
= rD(ctx
->opcode
);
3397 if (unlikely((rd
& 1) || (rd
== rA(ctx
->opcode
)) ||
3398 (rd
== rB(ctx
->opcode
)))) {
3399 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3403 gen_set_access_type(ctx
, ACCESS_RES
);
3404 EA
= tcg_temp_new();
3405 gen_addr_reg_index(ctx
, EA
);
3407 /* Note that the low part is always in RD+1, even in LE mode. */
3408 lo
= cpu_gpr
[rd
+ 1];
3411 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3412 if (HAVE_ATOMIC128
) {
3413 TCGv_i32 oi
= tcg_temp_new_i32();
3415 tcg_gen_movi_i32(oi
, make_memop_idx(MO_LEQ
| MO_ALIGN_16
,
3417 gen_helper_lq_le_parallel(lo
, cpu_env
, EA
, oi
);
3419 tcg_gen_movi_i32(oi
, make_memop_idx(MO_BEQ
| MO_ALIGN_16
,
3421 gen_helper_lq_be_parallel(lo
, cpu_env
, EA
, oi
);
3423 tcg_temp_free_i32(oi
);
3424 tcg_gen_ld_i64(hi
, cpu_env
, offsetof(CPUPPCState
, retxh
));
3426 /* Restart with exclusive lock. */
3427 gen_helper_exit_atomic(cpu_env
);
3428 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3432 } else if (ctx
->le_mode
) {
3433 tcg_gen_qemu_ld_i64(lo
, EA
, ctx
->mem_idx
, MO_LEQ
| MO_ALIGN_16
);
3434 tcg_gen_mov_tl(cpu_reserve
, EA
);
3435 gen_addr_add(ctx
, EA
, EA
, 8);
3436 tcg_gen_qemu_ld_i64(hi
, EA
, ctx
->mem_idx
, MO_LEQ
);
3438 tcg_gen_qemu_ld_i64(hi
, EA
, ctx
->mem_idx
, MO_BEQ
| MO_ALIGN_16
);
3439 tcg_gen_mov_tl(cpu_reserve
, EA
);
3440 gen_addr_add(ctx
, EA
, EA
, 8);
3441 tcg_gen_qemu_ld_i64(lo
, EA
, ctx
->mem_idx
, MO_BEQ
);
3445 tcg_gen_st_tl(hi
, cpu_env
, offsetof(CPUPPCState
, reserve_val
));
3446 tcg_gen_st_tl(lo
, cpu_env
, offsetof(CPUPPCState
, reserve_val2
));
3450 static void gen_stqcx_(DisasContext
*ctx
)
3452 int rs
= rS(ctx
->opcode
);
3455 if (unlikely(rs
& 1)) {
3456 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3460 gen_set_access_type(ctx
, ACCESS_RES
);
3461 EA
= tcg_temp_new();
3462 gen_addr_reg_index(ctx
, EA
);
3464 /* Note that the low part is always in RS+1, even in LE mode. */
3465 lo
= cpu_gpr
[rs
+ 1];
3468 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3469 if (HAVE_CMPXCHG128
) {
3470 TCGv_i32 oi
= tcg_const_i32(DEF_MEMOP(MO_Q
) | MO_ALIGN_16
);
3472 gen_helper_stqcx_le_parallel(cpu_crf
[0], cpu_env
,
3475 gen_helper_stqcx_be_parallel(cpu_crf
[0], cpu_env
,
3478 tcg_temp_free_i32(oi
);
3480 /* Restart with exclusive lock. */
3481 gen_helper_exit_atomic(cpu_env
);
3482 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3486 TCGLabel
*lab_fail
= gen_new_label();
3487 TCGLabel
*lab_over
= gen_new_label();
3488 TCGv_i64 t0
= tcg_temp_new_i64();
3489 TCGv_i64 t1
= tcg_temp_new_i64();
3491 tcg_gen_brcond_tl(TCG_COND_NE
, EA
, cpu_reserve
, lab_fail
);
3494 gen_qemu_ld64_i64(ctx
, t0
, cpu_reserve
);
3495 tcg_gen_ld_i64(t1
, cpu_env
, (ctx
->le_mode
3496 ? offsetof(CPUPPCState
, reserve_val2
)
3497 : offsetof(CPUPPCState
, reserve_val
)));
3498 tcg_gen_brcond_i64(TCG_COND_NE
, t0
, t1
, lab_fail
);
3500 tcg_gen_addi_i64(t0
, cpu_reserve
, 8);
3501 gen_qemu_ld64_i64(ctx
, t0
, t0
);
3502 tcg_gen_ld_i64(t1
, cpu_env
, (ctx
->le_mode
3503 ? offsetof(CPUPPCState
, reserve_val
)
3504 : offsetof(CPUPPCState
, reserve_val2
)));
3505 tcg_gen_brcond_i64(TCG_COND_NE
, t0
, t1
, lab_fail
);
3508 gen_qemu_st64_i64(ctx
, ctx
->le_mode
? lo
: hi
, cpu_reserve
);
3509 tcg_gen_addi_i64(t0
, cpu_reserve
, 8);
3510 gen_qemu_st64_i64(ctx
, ctx
->le_mode
? hi
: lo
, t0
);
3512 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3513 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], CRF_EQ
);
3514 tcg_gen_br(lab_over
);
3516 gen_set_label(lab_fail
);
3517 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3519 gen_set_label(lab_over
);
3520 tcg_gen_movi_tl(cpu_reserve
, -1);
3521 tcg_temp_free_i64(t0
);
3522 tcg_temp_free_i64(t1
);
3525 #endif /* defined(TARGET_PPC64) */
3528 static void gen_sync(DisasContext
*ctx
)
3530 uint32_t l
= (ctx
->opcode
>> 21) & 3;
3533 * We may need to check for a pending TLB flush.
3535 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3537 * Additionally, this can only happen in kernel mode however so
3538 * check MSR_PR as well.
3540 if (((l
== 2) || !(ctx
->insns_flags
& PPC_64B
)) && !ctx
->pr
) {
3541 gen_check_tlb_flush(ctx
, true);
3543 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
3547 static void gen_wait(DisasContext
*ctx
)
3549 TCGv_i32 t0
= tcg_const_i32(1);
3550 tcg_gen_st_i32(t0
, cpu_env
,
3551 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
3552 tcg_temp_free_i32(t0
);
3553 /* Stop translation, as the CPU is supposed to sleep from now */
3554 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
3557 #if defined(TARGET_PPC64)
3558 static void gen_doze(DisasContext
*ctx
)
3560 #if defined(CONFIG_USER_ONLY)
3566 t
= tcg_const_i32(PPC_PM_DOZE
);
3567 gen_helper_pminsn(cpu_env
, t
);
3568 tcg_temp_free_i32(t
);
3569 /* Stop translation, as the CPU is supposed to sleep from now */
3570 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
3571 #endif /* defined(CONFIG_USER_ONLY) */
3574 static void gen_nap(DisasContext
*ctx
)
3576 #if defined(CONFIG_USER_ONLY)
3582 t
= tcg_const_i32(PPC_PM_NAP
);
3583 gen_helper_pminsn(cpu_env
, t
);
3584 tcg_temp_free_i32(t
);
3585 /* Stop translation, as the CPU is supposed to sleep from now */
3586 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
3587 #endif /* defined(CONFIG_USER_ONLY) */
3590 static void gen_stop(DisasContext
*ctx
)
3592 #if defined(CONFIG_USER_ONLY)
3598 t
= tcg_const_i32(PPC_PM_STOP
);
3599 gen_helper_pminsn(cpu_env
, t
);
3600 tcg_temp_free_i32(t
);
3601 /* Stop translation, as the CPU is supposed to sleep from now */
3602 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
3603 #endif /* defined(CONFIG_USER_ONLY) */
3606 static void gen_sleep(DisasContext
*ctx
)
3608 #if defined(CONFIG_USER_ONLY)
3614 t
= tcg_const_i32(PPC_PM_SLEEP
);
3615 gen_helper_pminsn(cpu_env
, t
);
3616 tcg_temp_free_i32(t
);
3617 /* Stop translation, as the CPU is supposed to sleep from now */
3618 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
3619 #endif /* defined(CONFIG_USER_ONLY) */
3622 static void gen_rvwinkle(DisasContext
*ctx
)
3624 #if defined(CONFIG_USER_ONLY)
3630 t
= tcg_const_i32(PPC_PM_RVWINKLE
);
3631 gen_helper_pminsn(cpu_env
, t
);
3632 tcg_temp_free_i32(t
);
3633 /* Stop translation, as the CPU is supposed to sleep from now */
3634 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
3635 #endif /* defined(CONFIG_USER_ONLY) */
3637 #endif /* #if defined(TARGET_PPC64) */
3639 static inline void gen_update_cfar(DisasContext
*ctx
, target_ulong nip
)
3641 #if defined(TARGET_PPC64)
3643 tcg_gen_movi_tl(cpu_cfar
, nip
);
3647 static inline bool use_goto_tb(DisasContext
*ctx
, target_ulong dest
)
3649 if (unlikely(ctx
->singlestep_enabled
)) {
3653 #ifndef CONFIG_USER_ONLY
3654 return (ctx
->base
.tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
3660 static void gen_lookup_and_goto_ptr(DisasContext
*ctx
)
3662 int sse
= ctx
->singlestep_enabled
;
3663 if (unlikely(sse
)) {
3664 if (sse
& GDBSTUB_SINGLE_STEP
) {
3665 gen_debug_exception(ctx
);
3666 } else if (sse
& (CPU_SINGLE_STEP
| CPU_BRANCH_STEP
)) {
3667 uint32_t excp
= gen_prep_dbgex(ctx
);
3668 gen_exception(ctx
, excp
);
3670 tcg_gen_exit_tb(NULL
, 0);
3672 tcg_gen_lookup_and_goto_ptr();
3677 static void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
3679 if (NARROW_MODE(ctx
)) {
3680 dest
= (uint32_t) dest
;
3682 if (use_goto_tb(ctx
, dest
)) {
3684 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3685 tcg_gen_exit_tb(ctx
->base
.tb
, n
);
3687 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3688 gen_lookup_and_goto_ptr(ctx
);
3692 static inline void gen_setlr(DisasContext
*ctx
, target_ulong nip
)
3694 if (NARROW_MODE(ctx
)) {
3695 nip
= (uint32_t)nip
;
3697 tcg_gen_movi_tl(cpu_lr
, nip
);
3701 static void gen_b(DisasContext
*ctx
)
3703 target_ulong li
, target
;
3705 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3706 /* sign extend LI */
3707 li
= LI(ctx
->opcode
);
3708 li
= (li
^ 0x02000000) - 0x02000000;
3709 if (likely(AA(ctx
->opcode
) == 0)) {
3710 target
= ctx
->base
.pc_next
+ li
- 4;
3714 if (LK(ctx
->opcode
)) {
3715 gen_setlr(ctx
, ctx
->base
.pc_next
);
3717 gen_update_cfar(ctx
, ctx
->base
.pc_next
- 4);
3718 gen_goto_tb(ctx
, 0, target
);
3726 static void gen_bcond(DisasContext
*ctx
, int type
)
3728 uint32_t bo
= BO(ctx
->opcode
);
3731 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3733 if (type
== BCOND_LR
|| type
== BCOND_CTR
|| type
== BCOND_TAR
) {
3734 target
= tcg_temp_local_new();
3735 if (type
== BCOND_CTR
)
3736 tcg_gen_mov_tl(target
, cpu_ctr
);
3737 else if (type
== BCOND_TAR
)
3738 gen_load_spr(target
, SPR_TAR
);
3740 tcg_gen_mov_tl(target
, cpu_lr
);
3744 if (LK(ctx
->opcode
))
3745 gen_setlr(ctx
, ctx
->base
.pc_next
);
3746 l1
= gen_new_label();
3747 if ((bo
& 0x4) == 0) {
3748 /* Decrement and test CTR */
3749 TCGv temp
= tcg_temp_new();
3751 if (type
== BCOND_CTR
) {
3753 * All ISAs up to v3 describe this form of bcctr as invalid but
3754 * some processors, ie. 64-bit server processors compliant with
3755 * arch 2.x, do implement a "test and decrement" logic instead,
3756 * as described in their respective UMs.
3758 if (unlikely(!is_book3s_arch2x(ctx
))) {
3759 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3760 tcg_temp_free(temp
);
3761 tcg_temp_free(target
);
3765 if (NARROW_MODE(ctx
)) {
3766 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
3768 tcg_gen_mov_tl(temp
, cpu_ctr
);
3771 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
3773 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
3775 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
3777 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
3778 if (NARROW_MODE(ctx
)) {
3779 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
3781 tcg_gen_mov_tl(temp
, cpu_ctr
);
3784 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
3786 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
3789 tcg_temp_free(temp
);
3791 if ((bo
& 0x10) == 0) {
3793 uint32_t bi
= BI(ctx
->opcode
);
3794 uint32_t mask
= 0x08 >> (bi
& 0x03);
3795 TCGv_i32 temp
= tcg_temp_new_i32();
3798 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3799 tcg_gen_brcondi_i32(TCG_COND_EQ
, temp
, 0, l1
);
3801 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3802 tcg_gen_brcondi_i32(TCG_COND_NE
, temp
, 0, l1
);
3804 tcg_temp_free_i32(temp
);
3806 gen_update_cfar(ctx
, ctx
->base
.pc_next
- 4);
3807 if (type
== BCOND_IM
) {
3808 target_ulong li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
3809 if (likely(AA(ctx
->opcode
) == 0)) {
3810 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
+ li
- 4);
3812 gen_goto_tb(ctx
, 0, li
);
3815 if (NARROW_MODE(ctx
)) {
3816 tcg_gen_andi_tl(cpu_nip
, target
, (uint32_t)~3);
3818 tcg_gen_andi_tl(cpu_nip
, target
, ~3);
3820 gen_lookup_and_goto_ptr(ctx
);
3821 tcg_temp_free(target
);
3823 if ((bo
& 0x14) != 0x14) {
3824 /* fallthrough case */
3826 gen_goto_tb(ctx
, 1, ctx
->base
.pc_next
);
3830 static void gen_bc(DisasContext
*ctx
)
3832 gen_bcond(ctx
, BCOND_IM
);
3835 static void gen_bcctr(DisasContext
*ctx
)
3837 gen_bcond(ctx
, BCOND_CTR
);
3840 static void gen_bclr(DisasContext
*ctx
)
3842 gen_bcond(ctx
, BCOND_LR
);
3845 static void gen_bctar(DisasContext
*ctx
)
3847 gen_bcond(ctx
, BCOND_TAR
);
3850 /*** Condition register logical ***/
3851 #define GEN_CRLOGIC(name, tcg_op, opc) \
3852 static void glue(gen_, name)(DisasContext *ctx) \
3857 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3858 t0 = tcg_temp_new_i32(); \
3860 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3862 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3864 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3865 t1 = tcg_temp_new_i32(); \
3866 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3868 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3870 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3872 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3873 tcg_op(t0, t0, t1); \
3874 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3875 tcg_gen_andi_i32(t0, t0, bitmask); \
3876 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3877 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3878 tcg_temp_free_i32(t0); \
3879 tcg_temp_free_i32(t1); \
3883 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08);
3885 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04);
3887 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09);
3889 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07);
3891 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01);
3893 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E);
3895 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D);
3897 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06);
3900 static void gen_mcrf(DisasContext
*ctx
)
3902 tcg_gen_mov_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfS(ctx
->opcode
)]);
3905 /*** System linkage ***/
3907 /* rfi (supervisor only) */
3908 static void gen_rfi(DisasContext
*ctx
)
3910 #if defined(CONFIG_USER_ONLY)
3913 /* This instruction doesn't exist anymore on 64-bit server
3914 * processors compliant with arch 2.x
3916 if (is_book3s_arch2x(ctx
)) {
3917 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3920 /* Restore CPU state */
3922 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
3925 gen_update_cfar(ctx
, ctx
->base
.pc_next
- 4);
3926 gen_helper_rfi(cpu_env
);
3927 gen_sync_exception(ctx
);
3928 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
3934 #if defined(TARGET_PPC64)
3935 static void gen_rfid(DisasContext
*ctx
)
3937 #if defined(CONFIG_USER_ONLY)
3940 /* Restore CPU state */
3942 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
3945 gen_update_cfar(ctx
, ctx
->base
.pc_next
- 4);
3946 gen_helper_rfid(cpu_env
);
3947 gen_sync_exception(ctx
);
3948 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
3954 static void gen_hrfid(DisasContext
*ctx
)
3956 #if defined(CONFIG_USER_ONLY)
3959 /* Restore CPU state */
3961 gen_helper_hrfid(cpu_env
);
3962 gen_sync_exception(ctx
);
3968 #if defined(CONFIG_USER_ONLY)
3969 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3971 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3973 static void gen_sc(DisasContext
*ctx
)
3977 lev
= (ctx
->opcode
>> 5) & 0x7F;
3978 gen_exception_err(ctx
, POWERPC_SYSCALL
, lev
);
3983 /* Check for unconditional traps (always or never) */
3984 static bool check_unconditional_trap(DisasContext
*ctx
)
3987 if (TO(ctx
->opcode
) == 0) {
3991 if (TO(ctx
->opcode
) == 31) {
3992 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_TRAP
);
3999 static void gen_tw(DisasContext
*ctx
)
4003 if (check_unconditional_trap(ctx
)) {
4006 t0
= tcg_const_i32(TO(ctx
->opcode
));
4007 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
4009 tcg_temp_free_i32(t0
);
4013 static void gen_twi(DisasContext
*ctx
)
4018 if (check_unconditional_trap(ctx
)) {
4021 t0
= tcg_const_tl(SIMM(ctx
->opcode
));
4022 t1
= tcg_const_i32(TO(ctx
->opcode
));
4023 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4025 tcg_temp_free_i32(t1
);
4028 #if defined(TARGET_PPC64)
4030 static void gen_td(DisasContext
*ctx
)
4034 if (check_unconditional_trap(ctx
)) {
4037 t0
= tcg_const_i32(TO(ctx
->opcode
));
4038 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
4040 tcg_temp_free_i32(t0
);
4044 static void gen_tdi(DisasContext
*ctx
)
4049 if (check_unconditional_trap(ctx
)) {
4052 t0
= tcg_const_tl(SIMM(ctx
->opcode
));
4053 t1
= tcg_const_i32(TO(ctx
->opcode
));
4054 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4056 tcg_temp_free_i32(t1
);
4060 /*** Processor control ***/
4062 static void gen_read_xer(DisasContext
*ctx
, TCGv dst
)
4064 TCGv t0
= tcg_temp_new();
4065 TCGv t1
= tcg_temp_new();
4066 TCGv t2
= tcg_temp_new();
4067 tcg_gen_mov_tl(dst
, cpu_xer
);
4068 tcg_gen_shli_tl(t0
, cpu_so
, XER_SO
);
4069 tcg_gen_shli_tl(t1
, cpu_ov
, XER_OV
);
4070 tcg_gen_shli_tl(t2
, cpu_ca
, XER_CA
);
4071 tcg_gen_or_tl(t0
, t0
, t1
);
4072 tcg_gen_or_tl(dst
, dst
, t2
);
4073 tcg_gen_or_tl(dst
, dst
, t0
);
4074 if (is_isa300(ctx
)) {
4075 tcg_gen_shli_tl(t0
, cpu_ov32
, XER_OV32
);
4076 tcg_gen_or_tl(dst
, dst
, t0
);
4077 tcg_gen_shli_tl(t0
, cpu_ca32
, XER_CA32
);
4078 tcg_gen_or_tl(dst
, dst
, t0
);
4085 static void gen_write_xer(TCGv src
)
4087 /* Write all flags, while reading back check for isa300 */
4088 tcg_gen_andi_tl(cpu_xer
, src
,
4090 (1u << XER_OV
) | (1u << XER_OV32
) |
4091 (1u << XER_CA
) | (1u << XER_CA32
)));
4092 tcg_gen_extract_tl(cpu_ov32
, src
, XER_OV32
, 1);
4093 tcg_gen_extract_tl(cpu_ca32
, src
, XER_CA32
, 1);
4094 tcg_gen_extract_tl(cpu_so
, src
, XER_SO
, 1);
4095 tcg_gen_extract_tl(cpu_ov
, src
, XER_OV
, 1);
4096 tcg_gen_extract_tl(cpu_ca
, src
, XER_CA
, 1);
4100 static void gen_mcrxr(DisasContext
*ctx
)
4102 TCGv_i32 t0
= tcg_temp_new_i32();
4103 TCGv_i32 t1
= tcg_temp_new_i32();
4104 TCGv_i32 dst
= cpu_crf
[crfD(ctx
->opcode
)];
4106 tcg_gen_trunc_tl_i32(t0
, cpu_so
);
4107 tcg_gen_trunc_tl_i32(t1
, cpu_ov
);
4108 tcg_gen_trunc_tl_i32(dst
, cpu_ca
);
4109 tcg_gen_shli_i32(t0
, t0
, 3);
4110 tcg_gen_shli_i32(t1
, t1
, 2);
4111 tcg_gen_shli_i32(dst
, dst
, 1);
4112 tcg_gen_or_i32(dst
, dst
, t0
);
4113 tcg_gen_or_i32(dst
, dst
, t1
);
4114 tcg_temp_free_i32(t0
);
4115 tcg_temp_free_i32(t1
);
4117 tcg_gen_movi_tl(cpu_so
, 0);
4118 tcg_gen_movi_tl(cpu_ov
, 0);
4119 tcg_gen_movi_tl(cpu_ca
, 0);
4124 static void gen_mcrxrx(DisasContext
*ctx
)
4126 TCGv t0
= tcg_temp_new();
4127 TCGv t1
= tcg_temp_new();
4128 TCGv_i32 dst
= cpu_crf
[crfD(ctx
->opcode
)];
4130 /* copy OV and OV32 */
4131 tcg_gen_shli_tl(t0
, cpu_ov
, 1);
4132 tcg_gen_or_tl(t0
, t0
, cpu_ov32
);
4133 tcg_gen_shli_tl(t0
, t0
, 2);
4134 /* copy CA and CA32 */
4135 tcg_gen_shli_tl(t1
, cpu_ca
, 1);
4136 tcg_gen_or_tl(t1
, t1
, cpu_ca32
);
4137 tcg_gen_or_tl(t0
, t0
, t1
);
4138 tcg_gen_trunc_tl_i32(dst
, t0
);
4145 static void gen_mfcr(DisasContext
*ctx
)
4149 if (likely(ctx
->opcode
& 0x00100000)) {
4150 crm
= CRM(ctx
->opcode
);
4151 if (likely(crm
&& ((crm
& (crm
- 1)) == 0))) {
4153 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_crf
[7 - crn
]);
4154 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)],
4155 cpu_gpr
[rD(ctx
->opcode
)], crn
* 4);
4158 TCGv_i32 t0
= tcg_temp_new_i32();
4159 tcg_gen_mov_i32(t0
, cpu_crf
[0]);
4160 tcg_gen_shli_i32(t0
, t0
, 4);
4161 tcg_gen_or_i32(t0
, t0
, cpu_crf
[1]);
4162 tcg_gen_shli_i32(t0
, t0
, 4);
4163 tcg_gen_or_i32(t0
, t0
, cpu_crf
[2]);
4164 tcg_gen_shli_i32(t0
, t0
, 4);
4165 tcg_gen_or_i32(t0
, t0
, cpu_crf
[3]);
4166 tcg_gen_shli_i32(t0
, t0
, 4);
4167 tcg_gen_or_i32(t0
, t0
, cpu_crf
[4]);
4168 tcg_gen_shli_i32(t0
, t0
, 4);
4169 tcg_gen_or_i32(t0
, t0
, cpu_crf
[5]);
4170 tcg_gen_shli_i32(t0
, t0
, 4);
4171 tcg_gen_or_i32(t0
, t0
, cpu_crf
[6]);
4172 tcg_gen_shli_i32(t0
, t0
, 4);
4173 tcg_gen_or_i32(t0
, t0
, cpu_crf
[7]);
4174 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4175 tcg_temp_free_i32(t0
);
4180 static void gen_mfmsr(DisasContext
*ctx
)
4183 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_msr
);
4186 static void spr_noaccess(DisasContext
*ctx
, int gprn
, int sprn
)
4189 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
4190 printf("ERROR: try to access SPR %d !\n", sprn
);
4193 #define SPR_NOACCESS (&spr_noaccess)
4196 static inline void gen_op_mfspr(DisasContext
*ctx
)
4198 void (*read_cb
)(DisasContext
*ctx
, int gprn
, int sprn
);
4199 uint32_t sprn
= SPR(ctx
->opcode
);
4201 #if defined(CONFIG_USER_ONLY)
4202 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
4205 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
4206 } else if (ctx
->hv
) {
4207 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
4209 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
4212 if (likely(read_cb
!= NULL
)) {
4213 if (likely(read_cb
!= SPR_NOACCESS
)) {
4214 (*read_cb
)(ctx
, rD(ctx
->opcode
), sprn
);
4216 /* Privilege exception */
4217 /* This is a hack to avoid warnings when running Linux:
4218 * this OS breaks the PowerPC virtualisation model,
4219 * allowing userland application to read the PVR
4221 if (sprn
!= SPR_PVR
) {
4222 qemu_log_mask(LOG_GUEST_ERROR
, "Trying to read privileged spr "
4223 "%d (0x%03x) at " TARGET_FMT_lx
"\n", sprn
, sprn
,
4224 ctx
->base
.pc_next
- 4);
4226 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4229 /* ISA 2.07 defines these as no-ops */
4230 if ((ctx
->insns_flags2
& PPC2_ISA207S
) &&
4231 (sprn
>= 808 && sprn
<= 811)) {
4236 qemu_log_mask(LOG_GUEST_ERROR
,
4237 "Trying to read invalid spr %d (0x%03x) at "
4238 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->base
.pc_next
- 4);
4240 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4241 * it can generate a priv, a hv emu or a no-op
4245 gen_priv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4248 if (ctx
->pr
|| sprn
== 0 || sprn
== 4 || sprn
== 5 || sprn
== 6) {
4249 gen_hvpriv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4255 static void gen_mfspr(DisasContext
*ctx
)
4261 static void gen_mftb(DisasContext
*ctx
)
4267 static void gen_mtcrf(DisasContext
*ctx
)
4271 crm
= CRM(ctx
->opcode
);
4272 if (likely((ctx
->opcode
& 0x00100000))) {
4273 if (crm
&& ((crm
& (crm
- 1)) == 0)) {
4274 TCGv_i32 temp
= tcg_temp_new_i32();
4276 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
4277 tcg_gen_shri_i32(temp
, temp
, crn
* 4);
4278 tcg_gen_andi_i32(cpu_crf
[7 - crn
], temp
, 0xf);
4279 tcg_temp_free_i32(temp
);
4282 TCGv_i32 temp
= tcg_temp_new_i32();
4283 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
4284 for (crn
= 0 ; crn
< 8 ; crn
++) {
4285 if (crm
& (1 << crn
)) {
4286 tcg_gen_shri_i32(cpu_crf
[7 - crn
], temp
, crn
* 4);
4287 tcg_gen_andi_i32(cpu_crf
[7 - crn
], cpu_crf
[7 - crn
], 0xf);
4290 tcg_temp_free_i32(temp
);
4295 #if defined(TARGET_PPC64)
4296 static void gen_mtmsrd(DisasContext
*ctx
)
4300 #if !defined(CONFIG_USER_ONLY)
4301 if (ctx
->opcode
& 0x00010000) {
4302 /* Special form that does not need any synchronisation */
4303 TCGv t0
= tcg_temp_new();
4304 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
4305 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(target_ulong
)((1 << MSR_RI
) | (1 << MSR_EE
)));
4306 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
4309 /* XXX: we need to update nip before the store
4310 * if we enter power saving mode, we will exit the loop
4311 * directly from ppc_store_msr
4313 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
4316 gen_update_nip(ctx
, ctx
->base
.pc_next
);
4317 gen_helper_store_msr(cpu_env
, cpu_gpr
[rS(ctx
->opcode
)]);
4318 /* Must stop the translation as machine state (may have) changed */
4319 /* Note that mtmsr is not always defined as context-synchronizing */
4320 gen_stop_exception(ctx
);
4321 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
4325 #endif /* !defined(CONFIG_USER_ONLY) */
4327 #endif /* defined(TARGET_PPC64) */
4329 static void gen_mtmsr(DisasContext
*ctx
)
4333 #if !defined(CONFIG_USER_ONLY)
4334 if (ctx
->opcode
& 0x00010000) {
4335 /* Special form that does not need any synchronisation */
4336 TCGv t0
= tcg_temp_new();
4337 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], (1 << MSR_RI
) | (1 << MSR_EE
));
4338 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(target_ulong
)((1 << MSR_RI
) | (1 << MSR_EE
)));
4339 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
4342 TCGv msr
= tcg_temp_new();
4344 /* XXX: we need to update nip before the store
4345 * if we enter power saving mode, we will exit the loop
4346 * directly from ppc_store_msr
4348 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
4351 gen_update_nip(ctx
, ctx
->base
.pc_next
);
4352 #if defined(TARGET_PPC64)
4353 tcg_gen_deposit_tl(msr
, cpu_msr
, cpu_gpr
[rS(ctx
->opcode
)], 0, 32);
4355 tcg_gen_mov_tl(msr
, cpu_gpr
[rS(ctx
->opcode
)]);
4357 gen_helper_store_msr(cpu_env
, msr
);
4358 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
4362 /* Must stop the translation as machine state (may have) changed */
4363 /* Note that mtmsr is not always defined as context-synchronizing */
4364 gen_stop_exception(ctx
);
4370 static void gen_mtspr(DisasContext
*ctx
)
4372 void (*write_cb
)(DisasContext
*ctx
, int sprn
, int gprn
);
4373 uint32_t sprn
= SPR(ctx
->opcode
);
4375 #if defined(CONFIG_USER_ONLY)
4376 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4379 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4380 } else if (ctx
->hv
) {
4381 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
4383 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
4386 if (likely(write_cb
!= NULL
)) {
4387 if (likely(write_cb
!= SPR_NOACCESS
)) {
4388 (*write_cb
)(ctx
, sprn
, rS(ctx
->opcode
));
4390 /* Privilege exception */
4391 qemu_log_mask(LOG_GUEST_ERROR
, "Trying to write privileged spr "
4392 "%d (0x%03x) at " TARGET_FMT_lx
"\n", sprn
, sprn
,
4393 ctx
->base
.pc_next
- 4);
4394 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4397 /* ISA 2.07 defines these as no-ops */
4398 if ((ctx
->insns_flags2
& PPC2_ISA207S
) &&
4399 (sprn
>= 808 && sprn
<= 811)) {
4405 qemu_log_mask(LOG_GUEST_ERROR
,
4406 "Trying to write invalid spr %d (0x%03x) at "
4407 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->base
.pc_next
- 4);
4410 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
4411 * it can generate a priv, a hv emu or a no-op
4415 gen_priv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4418 if (ctx
->pr
|| sprn
== 0) {
4419 gen_hvpriv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4425 #if defined(TARGET_PPC64)
4427 static void gen_setb(DisasContext
*ctx
)
4429 TCGv_i32 t0
= tcg_temp_new_i32();
4430 TCGv_i32 t8
= tcg_temp_new_i32();
4431 TCGv_i32 tm1
= tcg_temp_new_i32();
4432 int crf
= crfS(ctx
->opcode
);
4434 tcg_gen_setcondi_i32(TCG_COND_GEU
, t0
, cpu_crf
[crf
], 4);
4435 tcg_gen_movi_i32(t8
, 8);
4436 tcg_gen_movi_i32(tm1
, -1);
4437 tcg_gen_movcond_i32(TCG_COND_GEU
, t0
, cpu_crf
[crf
], t8
, tm1
, t0
);
4438 tcg_gen_ext_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4440 tcg_temp_free_i32(t0
);
4441 tcg_temp_free_i32(t8
);
4442 tcg_temp_free_i32(tm1
);
4446 /*** Cache management ***/
4449 static void gen_dcbf(DisasContext
*ctx
)
4451 /* XXX: specification says this is treated as a load by the MMU */
4453 gen_set_access_type(ctx
, ACCESS_CACHE
);
4454 t0
= tcg_temp_new();
4455 gen_addr_reg_index(ctx
, t0
);
4456 gen_qemu_ld8u(ctx
, t0
, t0
);
4460 /* dcbfep (external PID dcbf) */
4461 static void gen_dcbfep(DisasContext
*ctx
)
4463 /* XXX: specification says this is treated as a load by the MMU */
4466 gen_set_access_type(ctx
, ACCESS_CACHE
);
4467 t0
= tcg_temp_new();
4468 gen_addr_reg_index(ctx
, t0
);
4469 tcg_gen_qemu_ld_tl(t0
, t0
, PPC_TLB_EPID_LOAD
, DEF_MEMOP(MO_UB
));
4473 /* dcbi (Supervisor only) */
4474 static void gen_dcbi(DisasContext
*ctx
)
4476 #if defined(CONFIG_USER_ONLY)
4482 EA
= tcg_temp_new();
4483 gen_set_access_type(ctx
, ACCESS_CACHE
);
4484 gen_addr_reg_index(ctx
, EA
);
4485 val
= tcg_temp_new();
4486 /* XXX: specification says this should be treated as a store by the MMU */
4487 gen_qemu_ld8u(ctx
, val
, EA
);
4488 gen_qemu_st8(ctx
, val
, EA
);
4491 #endif /* defined(CONFIG_USER_ONLY) */
4495 static void gen_dcbst(DisasContext
*ctx
)
4497 /* XXX: specification say this is treated as a load by the MMU */
4499 gen_set_access_type(ctx
, ACCESS_CACHE
);
4500 t0
= tcg_temp_new();
4501 gen_addr_reg_index(ctx
, t0
);
4502 gen_qemu_ld8u(ctx
, t0
, t0
);
4506 /* dcbstep (dcbstep External PID version) */
4507 static void gen_dcbstep(DisasContext
*ctx
)
4509 /* XXX: specification say this is treated as a load by the MMU */
4511 gen_set_access_type(ctx
, ACCESS_CACHE
);
4512 t0
= tcg_temp_new();
4513 gen_addr_reg_index(ctx
, t0
);
4514 tcg_gen_qemu_ld_tl(t0
, t0
, PPC_TLB_EPID_LOAD
, DEF_MEMOP(MO_UB
));
4519 static void gen_dcbt(DisasContext
*ctx
)
4521 /* interpreted as no-op */
4522 /* XXX: specification say this is treated as a load by the MMU
4523 * but does not generate any exception
4528 static void gen_dcbtep(DisasContext
*ctx
)
4530 /* interpreted as no-op */
4531 /* XXX: specification say this is treated as a load by the MMU
4532 * but does not generate any exception
4537 static void gen_dcbtst(DisasContext
*ctx
)
4539 /* interpreted as no-op */
4540 /* XXX: specification say this is treated as a load by the MMU
4541 * but does not generate any exception
4546 static void gen_dcbtstep(DisasContext
*ctx
)
4548 /* interpreted as no-op */
4549 /* XXX: specification say this is treated as a load by the MMU
4550 * but does not generate any exception
4555 static void gen_dcbtls(DisasContext
*ctx
)
4557 /* Always fails locking the cache */
4558 TCGv t0
= tcg_temp_new();
4559 gen_load_spr(t0
, SPR_Exxx_L1CSR0
);
4560 tcg_gen_ori_tl(t0
, t0
, L1CSR0_CUL
);
4561 gen_store_spr(SPR_Exxx_L1CSR0
, t0
);
4566 static void gen_dcbz(DisasContext
*ctx
)
4571 gen_set_access_type(ctx
, ACCESS_CACHE
);
4572 tcgv_addr
= tcg_temp_new();
4573 tcgv_op
= tcg_const_i32(ctx
->opcode
& 0x03FF000);
4574 gen_addr_reg_index(ctx
, tcgv_addr
);
4575 gen_helper_dcbz(cpu_env
, tcgv_addr
, tcgv_op
);
4576 tcg_temp_free(tcgv_addr
);
4577 tcg_temp_free_i32(tcgv_op
);
4581 static void gen_dcbzep(DisasContext
*ctx
)
4586 gen_set_access_type(ctx
, ACCESS_CACHE
);
4587 tcgv_addr
= tcg_temp_new();
4588 tcgv_op
= tcg_const_i32(ctx
->opcode
& 0x03FF000);
4589 gen_addr_reg_index(ctx
, tcgv_addr
);
4590 gen_helper_dcbzep(cpu_env
, tcgv_addr
, tcgv_op
);
4591 tcg_temp_free(tcgv_addr
);
4592 tcg_temp_free_i32(tcgv_op
);
4596 static void gen_dst(DisasContext
*ctx
)
4598 if (rA(ctx
->opcode
) == 0) {
4599 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
4601 /* interpreted as no-op */
4606 static void gen_dstst(DisasContext
*ctx
)
4608 if (rA(ctx
->opcode
) == 0) {
4609 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
4611 /* interpreted as no-op */
4617 static void gen_dss(DisasContext
*ctx
)
4619 /* interpreted as no-op */
4623 static void gen_icbi(DisasContext
*ctx
)
4626 gen_set_access_type(ctx
, ACCESS_CACHE
);
4627 t0
= tcg_temp_new();
4628 gen_addr_reg_index(ctx
, t0
);
4629 gen_helper_icbi(cpu_env
, t0
);
4634 static void gen_icbiep(DisasContext
*ctx
)
4637 gen_set_access_type(ctx
, ACCESS_CACHE
);
4638 t0
= tcg_temp_new();
4639 gen_addr_reg_index(ctx
, t0
);
4640 gen_helper_icbiep(cpu_env
, t0
);
4646 static void gen_dcba(DisasContext
*ctx
)
4648 /* interpreted as no-op */
4649 /* XXX: specification say this is treated as a store by the MMU
4650 * but does not generate any exception
4654 /*** Segment register manipulation ***/
4655 /* Supervisor only: */
4658 static void gen_mfsr(DisasContext
*ctx
)
4660 #if defined(CONFIG_USER_ONLY)
4666 t0
= tcg_const_tl(SR(ctx
->opcode
));
4667 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4669 #endif /* defined(CONFIG_USER_ONLY) */
4673 static void gen_mfsrin(DisasContext
*ctx
)
4675 #if defined(CONFIG_USER_ONLY)
4681 t0
= tcg_temp_new();
4682 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4683 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4685 #endif /* defined(CONFIG_USER_ONLY) */
4689 static void gen_mtsr(DisasContext
*ctx
)
4691 #if defined(CONFIG_USER_ONLY)
4697 t0
= tcg_const_tl(SR(ctx
->opcode
));
4698 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4700 #endif /* defined(CONFIG_USER_ONLY) */
4704 static void gen_mtsrin(DisasContext
*ctx
)
4706 #if defined(CONFIG_USER_ONLY)
4712 t0
= tcg_temp_new();
4713 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4714 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rD(ctx
->opcode
)]);
4716 #endif /* defined(CONFIG_USER_ONLY) */
4719 #if defined(TARGET_PPC64)
4720 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4723 static void gen_mfsr_64b(DisasContext
*ctx
)
4725 #if defined(CONFIG_USER_ONLY)
4731 t0
= tcg_const_tl(SR(ctx
->opcode
));
4732 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4734 #endif /* defined(CONFIG_USER_ONLY) */
4738 static void gen_mfsrin_64b(DisasContext
*ctx
)
4740 #if defined(CONFIG_USER_ONLY)
4746 t0
= tcg_temp_new();
4747 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4748 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4750 #endif /* defined(CONFIG_USER_ONLY) */
4754 static void gen_mtsr_64b(DisasContext
*ctx
)
4756 #if defined(CONFIG_USER_ONLY)
4762 t0
= tcg_const_tl(SR(ctx
->opcode
));
4763 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4765 #endif /* defined(CONFIG_USER_ONLY) */
4769 static void gen_mtsrin_64b(DisasContext
*ctx
)
4771 #if defined(CONFIG_USER_ONLY)
4777 t0
= tcg_temp_new();
4778 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4779 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4781 #endif /* defined(CONFIG_USER_ONLY) */
4785 static void gen_slbmte(DisasContext
*ctx
)
4787 #if defined(CONFIG_USER_ONLY)
4792 gen_helper_store_slb(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)],
4793 cpu_gpr
[rS(ctx
->opcode
)]);
4794 #endif /* defined(CONFIG_USER_ONLY) */
4797 static void gen_slbmfee(DisasContext
*ctx
)
4799 #if defined(CONFIG_USER_ONLY)
4804 gen_helper_load_slb_esid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4805 cpu_gpr
[rB(ctx
->opcode
)]);
4806 #endif /* defined(CONFIG_USER_ONLY) */
4809 static void gen_slbmfev(DisasContext
*ctx
)
4811 #if defined(CONFIG_USER_ONLY)
4816 gen_helper_load_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4817 cpu_gpr
[rB(ctx
->opcode
)]);
4818 #endif /* defined(CONFIG_USER_ONLY) */
4821 static void gen_slbfee_(DisasContext
*ctx
)
4823 #if defined(CONFIG_USER_ONLY)
4824 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4828 if (unlikely(ctx
->pr
)) {
4829 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4832 gen_helper_find_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4833 cpu_gpr
[rB(ctx
->opcode
)]);
4834 l1
= gen_new_label();
4835 l2
= gen_new_label();
4836 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
4837 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rS(ctx
->opcode
)], -1, l1
);
4838 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], CRF_EQ
);
4841 tcg_gen_movi_tl(cpu_gpr
[rS(ctx
->opcode
)], 0);
4845 #endif /* defined(TARGET_PPC64) */
4847 /*** Lookaside buffer management ***/
4848 /* Optional & supervisor only: */
4851 static void gen_tlbia(DisasContext
*ctx
)
4853 #if defined(CONFIG_USER_ONLY)
4858 gen_helper_tlbia(cpu_env
);
4859 #endif /* defined(CONFIG_USER_ONLY) */
4863 static void gen_tlbiel(DisasContext
*ctx
)
4865 #if defined(CONFIG_USER_ONLY)
4870 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4871 #endif /* defined(CONFIG_USER_ONLY) */
4875 static void gen_tlbie(DisasContext
*ctx
)
4877 #if defined(CONFIG_USER_ONLY)
4883 CHK_SV
; /* If gtse is set then tlbie is supervisor privileged */
4885 CHK_HV
; /* Else hypervisor privileged */
4888 if (NARROW_MODE(ctx
)) {
4889 TCGv t0
= tcg_temp_new();
4890 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
4891 gen_helper_tlbie(cpu_env
, t0
);
4894 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4896 t1
= tcg_temp_new_i32();
4897 tcg_gen_ld_i32(t1
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
4898 tcg_gen_ori_i32(t1
, t1
, TLB_NEED_GLOBAL_FLUSH
);
4899 tcg_gen_st_i32(t1
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
4900 tcg_temp_free_i32(t1
);
4901 #endif /* defined(CONFIG_USER_ONLY) */
4905 static void gen_tlbsync(DisasContext
*ctx
)
4907 #if defined(CONFIG_USER_ONLY)
4912 CHK_SV
; /* If gtse is set then tlbsync is supervisor privileged */
4914 CHK_HV
; /* Else hypervisor privileged */
4917 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
4918 if (ctx
->insns_flags
& PPC_BOOKE
) {
4919 gen_check_tlb_flush(ctx
, true);
4921 #endif /* defined(CONFIG_USER_ONLY) */
4924 #if defined(TARGET_PPC64)
4926 static void gen_slbia(DisasContext
*ctx
)
4928 #if defined(CONFIG_USER_ONLY)
4933 gen_helper_slbia(cpu_env
);
4934 #endif /* defined(CONFIG_USER_ONLY) */
4938 static void gen_slbie(DisasContext
*ctx
)
4940 #if defined(CONFIG_USER_ONLY)
4945 gen_helper_slbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4946 #endif /* defined(CONFIG_USER_ONLY) */
4950 static void gen_slbieg(DisasContext
*ctx
)
4952 #if defined(CONFIG_USER_ONLY)
4957 gen_helper_slbieg(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4958 #endif /* defined(CONFIG_USER_ONLY) */
4962 static void gen_slbsync(DisasContext
*ctx
)
4964 #if defined(CONFIG_USER_ONLY)
4968 gen_check_tlb_flush(ctx
, true);
4969 #endif /* defined(CONFIG_USER_ONLY) */
4972 #endif /* defined(TARGET_PPC64) */
4974 /*** External control ***/
4978 static void gen_eciwx(DisasContext
*ctx
)
4981 /* Should check EAR[E] ! */
4982 gen_set_access_type(ctx
, ACCESS_EXT
);
4983 t0
= tcg_temp_new();
4984 gen_addr_reg_index(ctx
, t0
);
4985 tcg_gen_qemu_ld_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, ctx
->mem_idx
,
4986 DEF_MEMOP(MO_UL
| MO_ALIGN
));
4991 static void gen_ecowx(DisasContext
*ctx
)
4994 /* Should check EAR[E] ! */
4995 gen_set_access_type(ctx
, ACCESS_EXT
);
4996 t0
= tcg_temp_new();
4997 gen_addr_reg_index(ctx
, t0
);
4998 tcg_gen_qemu_st_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, ctx
->mem_idx
,
4999 DEF_MEMOP(MO_UL
| MO_ALIGN
));
5003 /* PowerPC 601 specific instructions */
5006 static void gen_abs(DisasContext
*ctx
)
5008 TCGLabel
*l1
= gen_new_label();
5009 TCGLabel
*l2
= gen_new_label();
5010 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
5011 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5014 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5016 if (unlikely(Rc(ctx
->opcode
) != 0))
5017 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5021 static void gen_abso(DisasContext
*ctx
)
5023 TCGLabel
*l1
= gen_new_label();
5024 TCGLabel
*l2
= gen_new_label();
5025 TCGLabel
*l3
= gen_new_label();
5026 /* Start with XER OV disabled, the most likely case */
5027 tcg_gen_movi_tl(cpu_ov
, 0);
5028 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l2
);
5029 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rA(ctx
->opcode
)], 0x80000000, l1
);
5030 tcg_gen_movi_tl(cpu_ov
, 1);
5031 tcg_gen_movi_tl(cpu_so
, 1);
5034 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5037 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5039 if (unlikely(Rc(ctx
->opcode
) != 0))
5040 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5044 static void gen_clcs(DisasContext
*ctx
)
5046 TCGv_i32 t0
= tcg_const_i32(rA(ctx
->opcode
));
5047 gen_helper_clcs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5048 tcg_temp_free_i32(t0
);
5049 /* Rc=1 sets CR0 to an undefined state */
5053 static void gen_div(DisasContext
*ctx
)
5055 gen_helper_div(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5056 cpu_gpr
[rB(ctx
->opcode
)]);
5057 if (unlikely(Rc(ctx
->opcode
) != 0))
5058 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5062 static void gen_divo(DisasContext
*ctx
)
5064 gen_helper_divo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5065 cpu_gpr
[rB(ctx
->opcode
)]);
5066 if (unlikely(Rc(ctx
->opcode
) != 0))
5067 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5071 static void gen_divs(DisasContext
*ctx
)
5073 gen_helper_divs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5074 cpu_gpr
[rB(ctx
->opcode
)]);
5075 if (unlikely(Rc(ctx
->opcode
) != 0))
5076 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5079 /* divso - divso. */
5080 static void gen_divso(DisasContext
*ctx
)
5082 gen_helper_divso(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5083 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5084 if (unlikely(Rc(ctx
->opcode
) != 0))
5085 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5089 static void gen_doz(DisasContext
*ctx
)
5091 TCGLabel
*l1
= gen_new_label();
5092 TCGLabel
*l2
= gen_new_label();
5093 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
5094 tcg_gen_sub_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5097 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5099 if (unlikely(Rc(ctx
->opcode
) != 0))
5100 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5104 static void gen_dozo(DisasContext
*ctx
)
5106 TCGLabel
*l1
= gen_new_label();
5107 TCGLabel
*l2
= gen_new_label();
5108 TCGv t0
= tcg_temp_new();
5109 TCGv t1
= tcg_temp_new();
5110 TCGv t2
= tcg_temp_new();
5111 /* Start with XER OV disabled, the most likely case */
5112 tcg_gen_movi_tl(cpu_ov
, 0);
5113 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], l1
);
5114 tcg_gen_sub_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5115 tcg_gen_xor_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5116 tcg_gen_xor_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], t0
);
5117 tcg_gen_andc_tl(t1
, t1
, t2
);
5118 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
5119 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
5120 tcg_gen_movi_tl(cpu_ov
, 1);
5121 tcg_gen_movi_tl(cpu_so
, 1);
5124 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5129 if (unlikely(Rc(ctx
->opcode
) != 0))
5130 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5134 static void gen_dozi(DisasContext
*ctx
)
5136 target_long simm
= SIMM(ctx
->opcode
);
5137 TCGLabel
*l1
= gen_new_label();
5138 TCGLabel
*l2
= gen_new_label();
5139 tcg_gen_brcondi_tl(TCG_COND_LT
, cpu_gpr
[rA(ctx
->opcode
)], simm
, l1
);
5140 tcg_gen_subfi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
, cpu_gpr
[rA(ctx
->opcode
)]);
5143 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5145 if (unlikely(Rc(ctx
->opcode
) != 0))
5146 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5149 /* lscbx - lscbx. */
5150 static void gen_lscbx(DisasContext
*ctx
)
5152 TCGv t0
= tcg_temp_new();
5153 TCGv_i32 t1
= tcg_const_i32(rD(ctx
->opcode
));
5154 TCGv_i32 t2
= tcg_const_i32(rA(ctx
->opcode
));
5155 TCGv_i32 t3
= tcg_const_i32(rB(ctx
->opcode
));
5157 gen_addr_reg_index(ctx
, t0
);
5158 gen_helper_lscbx(t0
, cpu_env
, t0
, t1
, t2
, t3
);
5159 tcg_temp_free_i32(t1
);
5160 tcg_temp_free_i32(t2
);
5161 tcg_temp_free_i32(t3
);
5162 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~0x7F);
5163 tcg_gen_or_tl(cpu_xer
, cpu_xer
, t0
);
5164 if (unlikely(Rc(ctx
->opcode
) != 0))
5165 gen_set_Rc0(ctx
, t0
);
5169 /* maskg - maskg. */
5170 static void gen_maskg(DisasContext
*ctx
)
5172 TCGLabel
*l1
= gen_new_label();
5173 TCGv t0
= tcg_temp_new();
5174 TCGv t1
= tcg_temp_new();
5175 TCGv t2
= tcg_temp_new();
5176 TCGv t3
= tcg_temp_new();
5177 tcg_gen_movi_tl(t3
, 0xFFFFFFFF);
5178 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5179 tcg_gen_andi_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 0x1F);
5180 tcg_gen_addi_tl(t2
, t0
, 1);
5181 tcg_gen_shr_tl(t2
, t3
, t2
);
5182 tcg_gen_shr_tl(t3
, t3
, t1
);
5183 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], t2
, t3
);
5184 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
5185 tcg_gen_neg_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5191 if (unlikely(Rc(ctx
->opcode
) != 0))
5192 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5195 /* maskir - maskir. */
5196 static void gen_maskir(DisasContext
*ctx
)
5198 TCGv t0
= tcg_temp_new();
5199 TCGv t1
= tcg_temp_new();
5200 tcg_gen_and_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5201 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5202 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5205 if (unlikely(Rc(ctx
->opcode
) != 0))
5206 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5210 static void gen_mul(DisasContext
*ctx
)
5212 TCGv_i64 t0
= tcg_temp_new_i64();
5213 TCGv_i64 t1
= tcg_temp_new_i64();
5214 TCGv t2
= tcg_temp_new();
5215 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
5216 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
5217 tcg_gen_mul_i64(t0
, t0
, t1
);
5218 tcg_gen_trunc_i64_tl(t2
, t0
);
5219 gen_store_spr(SPR_MQ
, t2
);
5220 tcg_gen_shri_i64(t1
, t0
, 32);
5221 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
5222 tcg_temp_free_i64(t0
);
5223 tcg_temp_free_i64(t1
);
5225 if (unlikely(Rc(ctx
->opcode
) != 0))
5226 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5230 static void gen_mulo(DisasContext
*ctx
)
5232 TCGLabel
*l1
= gen_new_label();
5233 TCGv_i64 t0
= tcg_temp_new_i64();
5234 TCGv_i64 t1
= tcg_temp_new_i64();
5235 TCGv t2
= tcg_temp_new();
5236 /* Start with XER OV disabled, the most likely case */
5237 tcg_gen_movi_tl(cpu_ov
, 0);
5238 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
5239 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
5240 tcg_gen_mul_i64(t0
, t0
, t1
);
5241 tcg_gen_trunc_i64_tl(t2
, t0
);
5242 gen_store_spr(SPR_MQ
, t2
);
5243 tcg_gen_shri_i64(t1
, t0
, 32);
5244 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
5245 tcg_gen_ext32s_i64(t1
, t0
);
5246 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
5247 tcg_gen_movi_tl(cpu_ov
, 1);
5248 tcg_gen_movi_tl(cpu_so
, 1);
5250 tcg_temp_free_i64(t0
);
5251 tcg_temp_free_i64(t1
);
5253 if (unlikely(Rc(ctx
->opcode
) != 0))
5254 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5258 static void gen_nabs(DisasContext
*ctx
)
5260 TCGLabel
*l1
= gen_new_label();
5261 TCGLabel
*l2
= gen_new_label();
5262 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
5263 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5266 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5268 if (unlikely(Rc(ctx
->opcode
) != 0))
5269 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5272 /* nabso - nabso. */
5273 static void gen_nabso(DisasContext
*ctx
)
5275 TCGLabel
*l1
= gen_new_label();
5276 TCGLabel
*l2
= gen_new_label();
5277 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
5278 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5281 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5283 /* nabs never overflows */
5284 tcg_gen_movi_tl(cpu_ov
, 0);
5285 if (unlikely(Rc(ctx
->opcode
) != 0))
5286 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5290 static void gen_rlmi(DisasContext
*ctx
)
5292 uint32_t mb
= MB(ctx
->opcode
);
5293 uint32_t me
= ME(ctx
->opcode
);
5294 TCGv t0
= tcg_temp_new();
5295 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5296 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5297 tcg_gen_andi_tl(t0
, t0
, MASK(mb
, me
));
5298 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], ~MASK(mb
, me
));
5299 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], t0
);
5301 if (unlikely(Rc(ctx
->opcode
) != 0))
5302 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5306 static void gen_rrib(DisasContext
*ctx
)
5308 TCGv t0
= tcg_temp_new();
5309 TCGv t1
= tcg_temp_new();
5310 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5311 tcg_gen_movi_tl(t1
, 0x80000000);
5312 tcg_gen_shr_tl(t1
, t1
, t0
);
5313 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5314 tcg_gen_and_tl(t0
, t0
, t1
);
5315 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], t1
);
5316 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5319 if (unlikely(Rc(ctx
->opcode
) != 0))
5320 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5324 static void gen_sle(DisasContext
*ctx
)
5326 TCGv t0
= tcg_temp_new();
5327 TCGv t1
= tcg_temp_new();
5328 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5329 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5330 tcg_gen_subfi_tl(t1
, 32, t1
);
5331 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5332 tcg_gen_or_tl(t1
, t0
, t1
);
5333 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5334 gen_store_spr(SPR_MQ
, t1
);
5337 if (unlikely(Rc(ctx
->opcode
) != 0))
5338 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5342 static void gen_sleq(DisasContext
*ctx
)
5344 TCGv t0
= tcg_temp_new();
5345 TCGv t1
= tcg_temp_new();
5346 TCGv t2
= tcg_temp_new();
5347 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5348 tcg_gen_movi_tl(t2
, 0xFFFFFFFF);
5349 tcg_gen_shl_tl(t2
, t2
, t0
);
5350 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5351 gen_load_spr(t1
, SPR_MQ
);
5352 gen_store_spr(SPR_MQ
, t0
);
5353 tcg_gen_and_tl(t0
, t0
, t2
);
5354 tcg_gen_andc_tl(t1
, t1
, t2
);
5355 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5359 if (unlikely(Rc(ctx
->opcode
) != 0))
5360 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5364 static void gen_sliq(DisasContext
*ctx
)
5366 int sh
= SH(ctx
->opcode
);
5367 TCGv t0
= tcg_temp_new();
5368 TCGv t1
= tcg_temp_new();
5369 tcg_gen_shli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5370 tcg_gen_shri_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5371 tcg_gen_or_tl(t1
, t0
, t1
);
5372 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5373 gen_store_spr(SPR_MQ
, t1
);
5376 if (unlikely(Rc(ctx
->opcode
) != 0))
5377 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5380 /* slliq - slliq. */
5381 static void gen_slliq(DisasContext
*ctx
)
5383 int sh
= SH(ctx
->opcode
);
5384 TCGv t0
= tcg_temp_new();
5385 TCGv t1
= tcg_temp_new();
5386 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5387 gen_load_spr(t1
, SPR_MQ
);
5388 gen_store_spr(SPR_MQ
, t0
);
5389 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
<< sh
));
5390 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
<< sh
));
5391 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5394 if (unlikely(Rc(ctx
->opcode
) != 0))
5395 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5399 static void gen_sllq(DisasContext
*ctx
)
5401 TCGLabel
*l1
= gen_new_label();
5402 TCGLabel
*l2
= gen_new_label();
5403 TCGv t0
= tcg_temp_local_new();
5404 TCGv t1
= tcg_temp_local_new();
5405 TCGv t2
= tcg_temp_local_new();
5406 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5407 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5408 tcg_gen_shl_tl(t1
, t1
, t2
);
5409 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5410 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5411 gen_load_spr(t0
, SPR_MQ
);
5412 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5415 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5416 gen_load_spr(t2
, SPR_MQ
);
5417 tcg_gen_andc_tl(t1
, t2
, t1
);
5418 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5423 if (unlikely(Rc(ctx
->opcode
) != 0))
5424 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5428 static void gen_slq(DisasContext
*ctx
)
5430 TCGLabel
*l1
= gen_new_label();
5431 TCGv t0
= tcg_temp_new();
5432 TCGv t1
= tcg_temp_new();
5433 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5434 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5435 tcg_gen_subfi_tl(t1
, 32, t1
);
5436 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5437 tcg_gen_or_tl(t1
, t0
, t1
);
5438 gen_store_spr(SPR_MQ
, t1
);
5439 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5440 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5441 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5442 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5446 if (unlikely(Rc(ctx
->opcode
) != 0))
5447 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5450 /* sraiq - sraiq. */
5451 static void gen_sraiq(DisasContext
*ctx
)
5453 int sh
= SH(ctx
->opcode
);
5454 TCGLabel
*l1
= gen_new_label();
5455 TCGv t0
= tcg_temp_new();
5456 TCGv t1
= tcg_temp_new();
5457 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5458 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5459 tcg_gen_or_tl(t0
, t0
, t1
);
5460 gen_store_spr(SPR_MQ
, t0
);
5461 tcg_gen_movi_tl(cpu_ca
, 0);
5462 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5463 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
5464 tcg_gen_movi_tl(cpu_ca
, 1);
5466 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
5469 if (unlikely(Rc(ctx
->opcode
) != 0))
5470 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5474 static void gen_sraq(DisasContext
*ctx
)
5476 TCGLabel
*l1
= gen_new_label();
5477 TCGLabel
*l2
= gen_new_label();
5478 TCGv t0
= tcg_temp_new();
5479 TCGv t1
= tcg_temp_local_new();
5480 TCGv t2
= tcg_temp_local_new();
5481 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5482 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5483 tcg_gen_sar_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5484 tcg_gen_subfi_tl(t2
, 32, t2
);
5485 tcg_gen_shl_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5486 tcg_gen_or_tl(t0
, t0
, t2
);
5487 gen_store_spr(SPR_MQ
, t0
);
5488 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5489 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l1
);
5490 tcg_gen_mov_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
5491 tcg_gen_sari_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 31);
5494 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
);
5495 tcg_gen_movi_tl(cpu_ca
, 0);
5496 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
5497 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l2
);
5498 tcg_gen_movi_tl(cpu_ca
, 1);
5502 if (unlikely(Rc(ctx
->opcode
) != 0))
5503 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5507 static void gen_sre(DisasContext
*ctx
)
5509 TCGv t0
= tcg_temp_new();
5510 TCGv t1
= tcg_temp_new();
5511 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5512 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5513 tcg_gen_subfi_tl(t1
, 32, t1
);
5514 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5515 tcg_gen_or_tl(t1
, t0
, t1
);
5516 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5517 gen_store_spr(SPR_MQ
, t1
);
5520 if (unlikely(Rc(ctx
->opcode
) != 0))
5521 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5525 static void gen_srea(DisasContext
*ctx
)
5527 TCGv t0
= tcg_temp_new();
5528 TCGv t1
= tcg_temp_new();
5529 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5530 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5531 gen_store_spr(SPR_MQ
, t0
);
5532 tcg_gen_sar_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t1
);
5535 if (unlikely(Rc(ctx
->opcode
) != 0))
5536 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5540 static void gen_sreq(DisasContext
*ctx
)
5542 TCGv t0
= tcg_temp_new();
5543 TCGv t1
= tcg_temp_new();
5544 TCGv t2
= tcg_temp_new();
5545 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5546 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5547 tcg_gen_shr_tl(t1
, t1
, t0
);
5548 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5549 gen_load_spr(t2
, SPR_MQ
);
5550 gen_store_spr(SPR_MQ
, t0
);
5551 tcg_gen_and_tl(t0
, t0
, t1
);
5552 tcg_gen_andc_tl(t2
, t2
, t1
);
5553 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5557 if (unlikely(Rc(ctx
->opcode
) != 0))
5558 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5562 static void gen_sriq(DisasContext
*ctx
)
5564 int sh
= SH(ctx
->opcode
);
5565 TCGv t0
= tcg_temp_new();
5566 TCGv t1
= tcg_temp_new();
5567 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5568 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5569 tcg_gen_or_tl(t1
, t0
, t1
);
5570 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5571 gen_store_spr(SPR_MQ
, t1
);
5574 if (unlikely(Rc(ctx
->opcode
) != 0))
5575 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5579 static void gen_srliq(DisasContext
*ctx
)
5581 int sh
= SH(ctx
->opcode
);
5582 TCGv t0
= tcg_temp_new();
5583 TCGv t1
= tcg_temp_new();
5584 tcg_gen_rotri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5585 gen_load_spr(t1
, SPR_MQ
);
5586 gen_store_spr(SPR_MQ
, t0
);
5587 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
>> sh
));
5588 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
>> sh
));
5589 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5592 if (unlikely(Rc(ctx
->opcode
) != 0))
5593 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5597 static void gen_srlq(DisasContext
*ctx
)
5599 TCGLabel
*l1
= gen_new_label();
5600 TCGLabel
*l2
= gen_new_label();
5601 TCGv t0
= tcg_temp_local_new();
5602 TCGv t1
= tcg_temp_local_new();
5603 TCGv t2
= tcg_temp_local_new();
5604 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5605 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5606 tcg_gen_shr_tl(t2
, t1
, t2
);
5607 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5608 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5609 gen_load_spr(t0
, SPR_MQ
);
5610 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5613 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5614 tcg_gen_and_tl(t0
, t0
, t2
);
5615 gen_load_spr(t1
, SPR_MQ
);
5616 tcg_gen_andc_tl(t1
, t1
, t2
);
5617 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5622 if (unlikely(Rc(ctx
->opcode
) != 0))
5623 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5627 static void gen_srq(DisasContext
*ctx
)
5629 TCGLabel
*l1
= gen_new_label();
5630 TCGv t0
= tcg_temp_new();
5631 TCGv t1
= tcg_temp_new();
5632 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5633 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5634 tcg_gen_subfi_tl(t1
, 32, t1
);
5635 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5636 tcg_gen_or_tl(t1
, t0
, t1
);
5637 gen_store_spr(SPR_MQ
, t1
);
5638 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5639 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5640 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5641 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5645 if (unlikely(Rc(ctx
->opcode
) != 0))
5646 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5649 /* PowerPC 602 specific instructions */
5652 static void gen_dsa(DisasContext
*ctx
)
5655 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5659 static void gen_esa(DisasContext
*ctx
)
5662 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5666 static void gen_mfrom(DisasContext
*ctx
)
5668 #if defined(CONFIG_USER_ONLY)
5672 gen_helper_602_mfrom(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5673 #endif /* defined(CONFIG_USER_ONLY) */
5676 /* 602 - 603 - G2 TLB management */
5679 static void gen_tlbld_6xx(DisasContext
*ctx
)
5681 #if defined(CONFIG_USER_ONLY)
5685 gen_helper_6xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5686 #endif /* defined(CONFIG_USER_ONLY) */
5690 static void gen_tlbli_6xx(DisasContext
*ctx
)
5692 #if defined(CONFIG_USER_ONLY)
5696 gen_helper_6xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5697 #endif /* defined(CONFIG_USER_ONLY) */
5700 /* 74xx TLB management */
5703 static void gen_tlbld_74xx(DisasContext
*ctx
)
5705 #if defined(CONFIG_USER_ONLY)
5709 gen_helper_74xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5710 #endif /* defined(CONFIG_USER_ONLY) */
5714 static void gen_tlbli_74xx(DisasContext
*ctx
)
5716 #if defined(CONFIG_USER_ONLY)
5720 gen_helper_74xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5721 #endif /* defined(CONFIG_USER_ONLY) */
5724 /* POWER instructions not in PowerPC 601 */
5727 static void gen_clf(DisasContext
*ctx
)
5729 /* Cache line flush: implemented as no-op */
5733 static void gen_cli(DisasContext
*ctx
)
5735 #if defined(CONFIG_USER_ONLY)
5738 /* Cache line invalidate: privileged and treated as no-op */
5740 #endif /* defined(CONFIG_USER_ONLY) */
5744 static void gen_dclst(DisasContext
*ctx
)
5746 /* Data cache line store: treated as no-op */
5749 static void gen_mfsri(DisasContext
*ctx
)
5751 #if defined(CONFIG_USER_ONLY)
5754 int ra
= rA(ctx
->opcode
);
5755 int rd
= rD(ctx
->opcode
);
5759 t0
= tcg_temp_new();
5760 gen_addr_reg_index(ctx
, t0
);
5761 tcg_gen_extract_tl(t0
, t0
, 28, 4);
5762 gen_helper_load_sr(cpu_gpr
[rd
], cpu_env
, t0
);
5764 if (ra
!= 0 && ra
!= rd
)
5765 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rd
]);
5766 #endif /* defined(CONFIG_USER_ONLY) */
5769 static void gen_rac(DisasContext
*ctx
)
5771 #if defined(CONFIG_USER_ONLY)
5777 t0
= tcg_temp_new();
5778 gen_addr_reg_index(ctx
, t0
);
5779 gen_helper_rac(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5781 #endif /* defined(CONFIG_USER_ONLY) */
5784 static void gen_rfsvc(DisasContext
*ctx
)
5786 #if defined(CONFIG_USER_ONLY)
5791 gen_helper_rfsvc(cpu_env
);
5792 gen_sync_exception(ctx
);
5793 #endif /* defined(CONFIG_USER_ONLY) */
5796 /* svc is not implemented for now */
5798 /* BookE specific instructions */
5800 /* XXX: not implemented on 440 ? */
5801 static void gen_mfapidi(DisasContext
*ctx
)
5804 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5807 /* XXX: not implemented on 440 ? */
5808 static void gen_tlbiva(DisasContext
*ctx
)
5810 #if defined(CONFIG_USER_ONLY)
5816 t0
= tcg_temp_new();
5817 gen_addr_reg_index(ctx
, t0
);
5818 gen_helper_tlbiva(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5820 #endif /* defined(CONFIG_USER_ONLY) */
5823 /* All 405 MAC instructions are translated here */
5824 static inline void gen_405_mulladd_insn(DisasContext
*ctx
, int opc2
, int opc3
,
5825 int ra
, int rb
, int rt
, int Rc
)
5829 t0
= tcg_temp_local_new();
5830 t1
= tcg_temp_local_new();
5832 switch (opc3
& 0x0D) {
5834 /* macchw - macchw. - macchwo - macchwo. */
5835 /* macchws - macchws. - macchwso - macchwso. */
5836 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5837 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5838 /* mulchw - mulchw. */
5839 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5840 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5841 tcg_gen_ext16s_tl(t1
, t1
);
5844 /* macchwu - macchwu. - macchwuo - macchwuo. */
5845 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5846 /* mulchwu - mulchwu. */
5847 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5848 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5849 tcg_gen_ext16u_tl(t1
, t1
);
5852 /* machhw - machhw. - machhwo - machhwo. */
5853 /* machhws - machhws. - machhwso - machhwso. */
5854 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5855 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5856 /* mulhhw - mulhhw. */
5857 tcg_gen_sari_tl(t0
, cpu_gpr
[ra
], 16);
5858 tcg_gen_ext16s_tl(t0
, t0
);
5859 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5860 tcg_gen_ext16s_tl(t1
, t1
);
5863 /* machhwu - machhwu. - machhwuo - machhwuo. */
5864 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5865 /* mulhhwu - mulhhwu. */
5866 tcg_gen_shri_tl(t0
, cpu_gpr
[ra
], 16);
5867 tcg_gen_ext16u_tl(t0
, t0
);
5868 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5869 tcg_gen_ext16u_tl(t1
, t1
);
5872 /* maclhw - maclhw. - maclhwo - maclhwo. */
5873 /* maclhws - maclhws. - maclhwso - maclhwso. */
5874 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5875 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5876 /* mullhw - mullhw. */
5877 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5878 tcg_gen_ext16s_tl(t1
, cpu_gpr
[rb
]);
5881 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5882 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5883 /* mullhwu - mullhwu. */
5884 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5885 tcg_gen_ext16u_tl(t1
, cpu_gpr
[rb
]);
5889 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5890 tcg_gen_mul_tl(t1
, t0
, t1
);
5892 /* nmultiply-and-accumulate (0x0E) */
5893 tcg_gen_sub_tl(t0
, cpu_gpr
[rt
], t1
);
5895 /* multiply-and-accumulate (0x0C) */
5896 tcg_gen_add_tl(t0
, cpu_gpr
[rt
], t1
);
5900 /* Check overflow and/or saturate */
5901 TCGLabel
*l1
= gen_new_label();
5904 /* Start with XER OV disabled, the most likely case */
5905 tcg_gen_movi_tl(cpu_ov
, 0);
5909 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t1
);
5910 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
5911 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t0
);
5912 tcg_gen_brcondi_tl(TCG_COND_LT
, t1
, 0, l1
);
5915 tcg_gen_sari_tl(t0
, cpu_gpr
[rt
], 31);
5916 tcg_gen_xori_tl(t0
, t0
, 0x7fffffff);
5920 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
5923 tcg_gen_movi_tl(t0
, UINT32_MAX
);
5927 /* Check overflow */
5928 tcg_gen_movi_tl(cpu_ov
, 1);
5929 tcg_gen_movi_tl(cpu_so
, 1);
5932 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
5935 tcg_gen_mul_tl(cpu_gpr
[rt
], t0
, t1
);
5939 if (unlikely(Rc
) != 0) {
5941 gen_set_Rc0(ctx
, cpu_gpr
[rt
]);
5945 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5946 static void glue(gen_, name)(DisasContext *ctx) \
5948 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5949 rD(ctx->opcode), Rc(ctx->opcode)); \
5952 /* macchw - macchw. */
5953 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
5954 /* macchwo - macchwo. */
5955 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
5956 /* macchws - macchws. */
5957 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
5958 /* macchwso - macchwso. */
5959 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
5960 /* macchwsu - macchwsu. */
5961 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
5962 /* macchwsuo - macchwsuo. */
5963 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
5964 /* macchwu - macchwu. */
5965 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
5966 /* macchwuo - macchwuo. */
5967 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
5968 /* machhw - machhw. */
5969 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
5970 /* machhwo - machhwo. */
5971 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
5972 /* machhws - machhws. */
5973 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
5974 /* machhwso - machhwso. */
5975 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
5976 /* machhwsu - machhwsu. */
5977 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
5978 /* machhwsuo - machhwsuo. */
5979 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
5980 /* machhwu - machhwu. */
5981 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
5982 /* machhwuo - machhwuo. */
5983 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
5984 /* maclhw - maclhw. */
5985 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
5986 /* maclhwo - maclhwo. */
5987 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
5988 /* maclhws - maclhws. */
5989 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
5990 /* maclhwso - maclhwso. */
5991 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
5992 /* maclhwu - maclhwu. */
5993 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
5994 /* maclhwuo - maclhwuo. */
5995 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
5996 /* maclhwsu - maclhwsu. */
5997 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
5998 /* maclhwsuo - maclhwsuo. */
5999 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
6000 /* nmacchw - nmacchw. */
6001 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
6002 /* nmacchwo - nmacchwo. */
6003 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
6004 /* nmacchws - nmacchws. */
6005 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
6006 /* nmacchwso - nmacchwso. */
6007 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
6008 /* nmachhw - nmachhw. */
6009 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
6010 /* nmachhwo - nmachhwo. */
6011 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
6012 /* nmachhws - nmachhws. */
6013 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
6014 /* nmachhwso - nmachhwso. */
6015 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
6016 /* nmaclhw - nmaclhw. */
6017 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
6018 /* nmaclhwo - nmaclhwo. */
6019 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
6020 /* nmaclhws - nmaclhws. */
6021 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
6022 /* nmaclhwso - nmaclhwso. */
6023 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
6025 /* mulchw - mulchw. */
6026 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
6027 /* mulchwu - mulchwu. */
6028 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
6029 /* mulhhw - mulhhw. */
6030 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
6031 /* mulhhwu - mulhhwu. */
6032 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
6033 /* mullhw - mullhw. */
6034 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
6035 /* mullhwu - mullhwu. */
6036 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
6039 static void gen_mfdcr(DisasContext
*ctx
)
6041 #if defined(CONFIG_USER_ONLY)
6047 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
6048 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, dcrn
);
6049 tcg_temp_free(dcrn
);
6050 #endif /* defined(CONFIG_USER_ONLY) */
6054 static void gen_mtdcr(DisasContext
*ctx
)
6056 #if defined(CONFIG_USER_ONLY)
6062 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
6063 gen_helper_store_dcr(cpu_env
, dcrn
, cpu_gpr
[rS(ctx
->opcode
)]);
6064 tcg_temp_free(dcrn
);
6065 #endif /* defined(CONFIG_USER_ONLY) */
6069 /* XXX: not implemented on 440 ? */
6070 static void gen_mfdcrx(DisasContext
*ctx
)
6072 #if defined(CONFIG_USER_ONLY)
6076 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6077 cpu_gpr
[rA(ctx
->opcode
)]);
6078 /* Note: Rc update flag set leads to undefined state of Rc0 */
6079 #endif /* defined(CONFIG_USER_ONLY) */
6083 /* XXX: not implemented on 440 ? */
6084 static void gen_mtdcrx(DisasContext
*ctx
)
6086 #if defined(CONFIG_USER_ONLY)
6090 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6091 cpu_gpr
[rS(ctx
->opcode
)]);
6092 /* Note: Rc update flag set leads to undefined state of Rc0 */
6093 #endif /* defined(CONFIG_USER_ONLY) */
6096 /* mfdcrux (PPC 460) : user-mode access to DCR */
6097 static void gen_mfdcrux(DisasContext
*ctx
)
6099 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6100 cpu_gpr
[rA(ctx
->opcode
)]);
6101 /* Note: Rc update flag set leads to undefined state of Rc0 */
6104 /* mtdcrux (PPC 460) : user-mode access to DCR */
6105 static void gen_mtdcrux(DisasContext
*ctx
)
6107 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6108 cpu_gpr
[rS(ctx
->opcode
)]);
6109 /* Note: Rc update flag set leads to undefined state of Rc0 */
6113 static void gen_dccci(DisasContext
*ctx
)
6116 /* interpreted as no-op */
6120 static void gen_dcread(DisasContext
*ctx
)
6122 #if defined(CONFIG_USER_ONLY)
6128 gen_set_access_type(ctx
, ACCESS_CACHE
);
6129 EA
= tcg_temp_new();
6130 gen_addr_reg_index(ctx
, EA
);
6131 val
= tcg_temp_new();
6132 gen_qemu_ld32u(ctx
, val
, EA
);
6134 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], EA
);
6136 #endif /* defined(CONFIG_USER_ONLY) */
6140 static void gen_icbt_40x(DisasContext
*ctx
)
6142 /* interpreted as no-op */
6143 /* XXX: specification say this is treated as a load by the MMU
6144 * but does not generate any exception
6149 static void gen_iccci(DisasContext
*ctx
)
6152 /* interpreted as no-op */
6156 static void gen_icread(DisasContext
*ctx
)
6159 /* interpreted as no-op */
6162 /* rfci (supervisor only) */
6163 static void gen_rfci_40x(DisasContext
*ctx
)
6165 #if defined(CONFIG_USER_ONLY)
6169 /* Restore CPU state */
6170 gen_helper_40x_rfci(cpu_env
);
6171 gen_sync_exception(ctx
);
6172 #endif /* defined(CONFIG_USER_ONLY) */
6175 static void gen_rfci(DisasContext
*ctx
)
6177 #if defined(CONFIG_USER_ONLY)
6181 /* Restore CPU state */
6182 gen_helper_rfci(cpu_env
);
6183 gen_sync_exception(ctx
);
6184 #endif /* defined(CONFIG_USER_ONLY) */
6187 /* BookE specific */
6189 /* XXX: not implemented on 440 ? */
6190 static void gen_rfdi(DisasContext
*ctx
)
6192 #if defined(CONFIG_USER_ONLY)
6196 /* Restore CPU state */
6197 gen_helper_rfdi(cpu_env
);
6198 gen_sync_exception(ctx
);
6199 #endif /* defined(CONFIG_USER_ONLY) */
6202 /* XXX: not implemented on 440 ? */
6203 static void gen_rfmci(DisasContext
*ctx
)
6205 #if defined(CONFIG_USER_ONLY)
6209 /* Restore CPU state */
6210 gen_helper_rfmci(cpu_env
);
6211 gen_sync_exception(ctx
);
6212 #endif /* defined(CONFIG_USER_ONLY) */
6215 /* TLB management - PowerPC 405 implementation */
6218 static void gen_tlbre_40x(DisasContext
*ctx
)
6220 #if defined(CONFIG_USER_ONLY)
6224 switch (rB(ctx
->opcode
)) {
6226 gen_helper_4xx_tlbre_hi(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6227 cpu_gpr
[rA(ctx
->opcode
)]);
6230 gen_helper_4xx_tlbre_lo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6231 cpu_gpr
[rA(ctx
->opcode
)]);
6234 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6237 #endif /* defined(CONFIG_USER_ONLY) */
6240 /* tlbsx - tlbsx. */
6241 static void gen_tlbsx_40x(DisasContext
*ctx
)
6243 #if defined(CONFIG_USER_ONLY)
6249 t0
= tcg_temp_new();
6250 gen_addr_reg_index(ctx
, t0
);
6251 gen_helper_4xx_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
6253 if (Rc(ctx
->opcode
)) {
6254 TCGLabel
*l1
= gen_new_label();
6255 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
6256 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
6257 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6260 #endif /* defined(CONFIG_USER_ONLY) */
6264 static void gen_tlbwe_40x(DisasContext
*ctx
)
6266 #if defined(CONFIG_USER_ONLY)
6271 switch (rB(ctx
->opcode
)) {
6273 gen_helper_4xx_tlbwe_hi(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6274 cpu_gpr
[rS(ctx
->opcode
)]);
6277 gen_helper_4xx_tlbwe_lo(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6278 cpu_gpr
[rS(ctx
->opcode
)]);
6281 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6284 #endif /* defined(CONFIG_USER_ONLY) */
6287 /* TLB management - PowerPC 440 implementation */
6290 static void gen_tlbre_440(DisasContext
*ctx
)
6292 #if defined(CONFIG_USER_ONLY)
6297 switch (rB(ctx
->opcode
)) {
6302 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6303 gen_helper_440_tlbre(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6304 t0
, cpu_gpr
[rA(ctx
->opcode
)]);
6305 tcg_temp_free_i32(t0
);
6309 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6312 #endif /* defined(CONFIG_USER_ONLY) */
6315 /* tlbsx - tlbsx. */
6316 static void gen_tlbsx_440(DisasContext
*ctx
)
6318 #if defined(CONFIG_USER_ONLY)
6324 t0
= tcg_temp_new();
6325 gen_addr_reg_index(ctx
, t0
);
6326 gen_helper_440_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
6328 if (Rc(ctx
->opcode
)) {
6329 TCGLabel
*l1
= gen_new_label();
6330 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
6331 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
6332 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6335 #endif /* defined(CONFIG_USER_ONLY) */
6339 static void gen_tlbwe_440(DisasContext
*ctx
)
6341 #if defined(CONFIG_USER_ONLY)
6345 switch (rB(ctx
->opcode
)) {
6350 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6351 gen_helper_440_tlbwe(cpu_env
, t0
, cpu_gpr
[rA(ctx
->opcode
)],
6352 cpu_gpr
[rS(ctx
->opcode
)]);
6353 tcg_temp_free_i32(t0
);
6357 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6360 #endif /* defined(CONFIG_USER_ONLY) */
6363 /* TLB management - PowerPC BookE 2.06 implementation */
6366 static void gen_tlbre_booke206(DisasContext
*ctx
)
6368 #if defined(CONFIG_USER_ONLY)
6372 gen_helper_booke206_tlbre(cpu_env
);
6373 #endif /* defined(CONFIG_USER_ONLY) */
6376 /* tlbsx - tlbsx. */
6377 static void gen_tlbsx_booke206(DisasContext
*ctx
)
6379 #if defined(CONFIG_USER_ONLY)
6385 if (rA(ctx
->opcode
)) {
6386 t0
= tcg_temp_new();
6387 tcg_gen_mov_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)]);
6389 t0
= tcg_const_tl(0);
6392 tcg_gen_add_tl(t0
, t0
, cpu_gpr
[rB(ctx
->opcode
)]);
6393 gen_helper_booke206_tlbsx(cpu_env
, t0
);
6395 #endif /* defined(CONFIG_USER_ONLY) */
6399 static void gen_tlbwe_booke206(DisasContext
*ctx
)
6401 #if defined(CONFIG_USER_ONLY)
6405 gen_helper_booke206_tlbwe(cpu_env
);
6406 #endif /* defined(CONFIG_USER_ONLY) */
6409 static void gen_tlbivax_booke206(DisasContext
*ctx
)
6411 #if defined(CONFIG_USER_ONLY)
6417 t0
= tcg_temp_new();
6418 gen_addr_reg_index(ctx
, t0
);
6419 gen_helper_booke206_tlbivax(cpu_env
, t0
);
6421 #endif /* defined(CONFIG_USER_ONLY) */
6424 static void gen_tlbilx_booke206(DisasContext
*ctx
)
6426 #if defined(CONFIG_USER_ONLY)
6432 t0
= tcg_temp_new();
6433 gen_addr_reg_index(ctx
, t0
);
6435 switch((ctx
->opcode
>> 21) & 0x3) {
6437 gen_helper_booke206_tlbilx0(cpu_env
, t0
);
6440 gen_helper_booke206_tlbilx1(cpu_env
, t0
);
6443 gen_helper_booke206_tlbilx3(cpu_env
, t0
);
6446 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6451 #endif /* defined(CONFIG_USER_ONLY) */
6456 static void gen_wrtee(DisasContext
*ctx
)
6458 #if defined(CONFIG_USER_ONLY)
6464 t0
= tcg_temp_new();
6465 tcg_gen_andi_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)], (1 << MSR_EE
));
6466 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6467 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
6469 /* Stop translation to have a chance to raise an exception
6470 * if we just set msr_ee to 1
6472 gen_stop_exception(ctx
);
6473 #endif /* defined(CONFIG_USER_ONLY) */
6477 static void gen_wrteei(DisasContext
*ctx
)
6479 #if defined(CONFIG_USER_ONLY)
6483 if (ctx
->opcode
& 0x00008000) {
6484 tcg_gen_ori_tl(cpu_msr
, cpu_msr
, (1 << MSR_EE
));
6485 /* Stop translation to have a chance to raise an exception */
6486 gen_stop_exception(ctx
);
6488 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6490 #endif /* defined(CONFIG_USER_ONLY) */
6493 /* PowerPC 440 specific instructions */
6496 static void gen_dlmzb(DisasContext
*ctx
)
6498 TCGv_i32 t0
= tcg_const_i32(Rc(ctx
->opcode
));
6499 gen_helper_dlmzb(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
6500 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
6501 tcg_temp_free_i32(t0
);
6504 /* mbar replaces eieio on 440 */
6505 static void gen_mbar(DisasContext
*ctx
)
6507 /* interpreted as no-op */
6510 /* msync replaces sync on 440 */
6511 static void gen_msync_4xx(DisasContext
*ctx
)
6513 /* Only e500 seems to treat reserved bits as invalid */
6514 if ((ctx
->insns_flags2
& PPC2_BOOKE206
) &&
6515 (ctx
->opcode
& 0x03FFF801)) {
6516 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6518 /* otherwise interpreted as no-op */
6522 static void gen_icbt_440(DisasContext
*ctx
)
6524 /* interpreted as no-op */
6525 /* XXX: specification say this is treated as a load by the MMU
6526 * but does not generate any exception
6530 /* Embedded.Processor Control */
6532 static void gen_msgclr(DisasContext
*ctx
)
6534 #if defined(CONFIG_USER_ONLY)
6538 if (is_book3s_arch2x(ctx
)) {
6539 gen_helper_book3s_msgclr(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6541 gen_helper_msgclr(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6543 #endif /* defined(CONFIG_USER_ONLY) */
6546 static void gen_msgsnd(DisasContext
*ctx
)
6548 #if defined(CONFIG_USER_ONLY)
6552 if (is_book3s_arch2x(ctx
)) {
6553 gen_helper_book3s_msgsnd(cpu_gpr
[rB(ctx
->opcode
)]);
6555 gen_helper_msgsnd(cpu_gpr
[rB(ctx
->opcode
)]);
6557 #endif /* defined(CONFIG_USER_ONLY) */
6560 static void gen_msgsync(DisasContext
*ctx
)
6562 #if defined(CONFIG_USER_ONLY)
6566 #endif /* defined(CONFIG_USER_ONLY) */
6567 /* interpreted as no-op */
6570 #if defined(TARGET_PPC64)
6571 static void gen_maddld(DisasContext
*ctx
)
6573 TCGv_i64 t1
= tcg_temp_new_i64();
6575 tcg_gen_mul_i64(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
6576 tcg_gen_add_i64(cpu_gpr
[rD(ctx
->opcode
)], t1
, cpu_gpr
[rC(ctx
->opcode
)]);
6577 tcg_temp_free_i64(t1
);
6580 /* maddhd maddhdu */
6581 static void gen_maddhd_maddhdu(DisasContext
*ctx
)
6583 TCGv_i64 lo
= tcg_temp_new_i64();
6584 TCGv_i64 hi
= tcg_temp_new_i64();
6585 TCGv_i64 t1
= tcg_temp_new_i64();
6587 if (Rc(ctx
->opcode
)) {
6588 tcg_gen_mulu2_i64(lo
, hi
, cpu_gpr
[rA(ctx
->opcode
)],
6589 cpu_gpr
[rB(ctx
->opcode
)]);
6590 tcg_gen_movi_i64(t1
, 0);
6592 tcg_gen_muls2_i64(lo
, hi
, cpu_gpr
[rA(ctx
->opcode
)],
6593 cpu_gpr
[rB(ctx
->opcode
)]);
6594 tcg_gen_sari_i64(t1
, cpu_gpr
[rC(ctx
->opcode
)], 63);
6596 tcg_gen_add2_i64(t1
, cpu_gpr
[rD(ctx
->opcode
)], lo
, hi
,
6597 cpu_gpr
[rC(ctx
->opcode
)], t1
);
6598 tcg_temp_free_i64(lo
);
6599 tcg_temp_free_i64(hi
);
6600 tcg_temp_free_i64(t1
);
6602 #endif /* defined(TARGET_PPC64) */
6604 static void gen_tbegin(DisasContext
*ctx
)
6606 if (unlikely(!ctx
->tm_enabled
)) {
6607 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
6610 gen_helper_tbegin(cpu_env
);
6613 #define GEN_TM_NOOP(name) \
6614 static inline void gen_##name(DisasContext *ctx) \
6616 if (unlikely(!ctx->tm_enabled)) { \
6617 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6620 /* Because tbegin always fails in QEMU, these user \
6621 * space instructions all have a simple implementation: \
6623 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6624 * = 0b0 || 0b00 || 0b0 \
6626 tcg_gen_movi_i32(cpu_crf[0], 0); \
6630 GEN_TM_NOOP(tabort
);
6631 GEN_TM_NOOP(tabortwc
);
6632 GEN_TM_NOOP(tabortwci
);
6633 GEN_TM_NOOP(tabortdc
);
6634 GEN_TM_NOOP(tabortdci
);
6636 static inline void gen_cp_abort(DisasContext
*ctx
)
6641 #define GEN_CP_PASTE_NOOP(name) \
6642 static inline void gen_##name(DisasContext *ctx) \
6644 /* Generate invalid exception until \
6645 * we have an implementation of the copy \
6651 GEN_CP_PASTE_NOOP(copy
)
6652 GEN_CP_PASTE_NOOP(paste
)
6654 static void gen_tcheck(DisasContext
*ctx
)
6656 if (unlikely(!ctx
->tm_enabled
)) {
6657 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
6660 /* Because tbegin always fails, the tcheck implementation
6663 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6664 * = 0b1 || 0b00 || 0b0
6666 tcg_gen_movi_i32(cpu_crf
[crfD(ctx
->opcode
)], 0x8);
6669 #if defined(CONFIG_USER_ONLY)
6670 #define GEN_TM_PRIV_NOOP(name) \
6671 static inline void gen_##name(DisasContext *ctx) \
6673 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6678 #define GEN_TM_PRIV_NOOP(name) \
6679 static inline void gen_##name(DisasContext *ctx) \
6682 if (unlikely(!ctx->tm_enabled)) { \
6683 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6686 /* Because tbegin always fails, the implementation is \
6689 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6690 * = 0b0 || 0b00 | 0b0 \
6692 tcg_gen_movi_i32(cpu_crf[0], 0); \
6697 GEN_TM_PRIV_NOOP(treclaim
);
6698 GEN_TM_PRIV_NOOP(trechkpt
);
6700 static inline void get_fpr(TCGv_i64 dst
, int regno
)
6702 tcg_gen_ld_i64(dst
, cpu_env
, fpr_offset(regno
));
6705 static inline void set_fpr(int regno
, TCGv_i64 src
)
6707 tcg_gen_st_i64(src
, cpu_env
, fpr_offset(regno
));
6710 static inline void get_avr64(TCGv_i64 dst
, int regno
, bool high
)
6712 tcg_gen_ld_i64(dst
, cpu_env
, avr64_offset(regno
, high
));
6715 static inline void set_avr64(int regno
, TCGv_i64 src
, bool high
)
6717 tcg_gen_st_i64(src
, cpu_env
, avr64_offset(regno
, high
));
6720 #include "translate/fp-impl.inc.c"
6722 #include "translate/vmx-impl.inc.c"
6724 #include "translate/vsx-impl.inc.c"
6726 #include "translate/dfp-impl.inc.c"
6728 #include "translate/spe-impl.inc.c"
6730 /* Handles lfdp, lxsd, lxssp */
6731 static void gen_dform39(DisasContext
*ctx
)
6733 switch (ctx
->opcode
& 0x3) {
6735 if (ctx
->insns_flags2
& PPC2_ISA205
) {
6736 return gen_lfdp(ctx
);
6740 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6741 return gen_lxsd(ctx
);
6745 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6746 return gen_lxssp(ctx
);
6750 return gen_invalid(ctx
);
6753 /* handles stfdp, lxv, stxsd, stxssp lxvx */
6754 static void gen_dform3D(DisasContext
*ctx
)
6756 if ((ctx
->opcode
& 3) == 1) { /* DQ-FORM */
6757 switch (ctx
->opcode
& 0x7) {
6759 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6760 return gen_lxv(ctx
);
6764 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6765 return gen_stxv(ctx
);
6769 } else { /* DS-FORM */
6770 switch (ctx
->opcode
& 0x3) {
6772 if (ctx
->insns_flags2
& PPC2_ISA205
) {
6773 return gen_stfdp(ctx
);
6777 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6778 return gen_stxsd(ctx
);
6781 case 3: /* stxssp */
6782 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6783 return gen_stxssp(ctx
);
6788 return gen_invalid(ctx
);
6791 static opcode_t opcodes
[] = {
6792 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
),
6793 GEN_HANDLER(cmp
, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER
),
6794 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
6795 GEN_HANDLER(cmpl
, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER
),
6796 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
6797 #if defined(TARGET_PPC64)
6798 GEN_HANDLER_E(cmpeqb
, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE
, PPC2_ISA300
),
6800 GEN_HANDLER_E(cmpb
, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE
, PPC2_ISA205
),
6801 GEN_HANDLER_E(cmprb
, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE
, PPC2_ISA300
),
6802 GEN_HANDLER(isel
, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL
),
6803 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6804 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6805 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6806 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6807 GEN_HANDLER_E(addpcis
, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA300
),
6808 GEN_HANDLER(mulhw
, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER
),
6809 GEN_HANDLER(mulhwu
, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER
),
6810 GEN_HANDLER(mullw
, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER
),
6811 GEN_HANDLER(mullwo
, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER
),
6812 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6813 #if defined(TARGET_PPC64)
6814 GEN_HANDLER(mulld
, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B
),
6816 GEN_HANDLER(neg
, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER
),
6817 GEN_HANDLER(nego
, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER
),
6818 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6819 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6820 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6821 GEN_HANDLER(cntlzw
, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER
),
6822 GEN_HANDLER_E(cnttzw
, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE
, PPC2_ISA300
),
6823 GEN_HANDLER_E(copy
, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE
, PPC2_ISA300
),
6824 GEN_HANDLER_E(cp_abort
, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE
, PPC2_ISA300
),
6825 GEN_HANDLER_E(paste
, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE
, PPC2_ISA300
),
6826 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
),
6827 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
),
6828 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6829 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6830 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6831 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6832 GEN_HANDLER(popcntb
, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB
),
6833 GEN_HANDLER(popcntw
, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD
),
6834 GEN_HANDLER_E(prtyw
, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
6835 #if defined(TARGET_PPC64)
6836 GEN_HANDLER(popcntd
, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD
),
6837 GEN_HANDLER(cntlzd
, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B
),
6838 GEN_HANDLER_E(cnttzd
, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE
, PPC2_ISA300
),
6839 GEN_HANDLER_E(darn
, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE
, PPC2_ISA300
),
6840 GEN_HANDLER_E(prtyd
, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
6841 GEN_HANDLER_E(bpermd
, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE
, PPC2_PERM_ISA206
),
6843 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6844 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6845 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6846 GEN_HANDLER(slw
, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER
),
6847 GEN_HANDLER(sraw
, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER
),
6848 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
),
6849 GEN_HANDLER(srw
, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER
),
6850 #if defined(TARGET_PPC64)
6851 GEN_HANDLER(sld
, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B
),
6852 GEN_HANDLER(srad
, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B
),
6853 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
),
6854 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
),
6855 GEN_HANDLER(srd
, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B
),
6856 GEN_HANDLER2_E(extswsli0
, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6857 PPC_NONE
, PPC2_ISA300
),
6858 GEN_HANDLER2_E(extswsli1
, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6859 PPC_NONE
, PPC2_ISA300
),
6861 #if defined(TARGET_PPC64)
6862 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
),
6863 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
),
6864 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
),
6866 /* handles lfdp, lxsd, lxssp */
6867 GEN_HANDLER_E(dform39
, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA205
),
6868 /* handles stfdp, lxv, stxsd, stxssp, stxv */
6869 GEN_HANDLER_E(dform3D
, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA205
),
6870 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6871 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6872 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING
),
6873 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING
),
6874 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING
),
6875 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING
),
6876 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO
),
6877 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
),
6878 GEN_HANDLER_E(lbarx
, 0x1F, 0x14, 0x01, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6879 GEN_HANDLER_E(lharx
, 0x1F, 0x14, 0x03, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6880 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES
),
6881 GEN_HANDLER_E(lwat
, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6882 GEN_HANDLER_E(stwat
, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6883 GEN_HANDLER_E(stbcx_
, 0x1F, 0x16, 0x15, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6884 GEN_HANDLER_E(sthcx_
, 0x1F, 0x16, 0x16, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6885 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
),
6886 #if defined(TARGET_PPC64)
6887 GEN_HANDLER_E(ldat
, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6888 GEN_HANDLER_E(stdat
, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6889 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B
),
6890 GEN_HANDLER_E(lqarx
, 0x1F, 0x14, 0x08, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
6891 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
),
6892 GEN_HANDLER_E(stqcx_
, 0x1F, 0x16, 0x05, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
6894 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
),
6895 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
),
6896 GEN_HANDLER_E(wait
, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE
, PPC2_ISA300
),
6897 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
6898 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
6899 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
),
6900 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
),
6901 GEN_HANDLER_E(bctar
, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE
, PPC2_BCTAR_ISA207
),
6902 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
),
6903 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
),
6904 #if defined(TARGET_PPC64)
6905 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
),
6906 GEN_HANDLER_E(stop
, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE
, PPC2_ISA300
),
6907 GEN_HANDLER_E(doze
, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
6908 GEN_HANDLER_E(nap
, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
6909 GEN_HANDLER_E(sleep
, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
6910 GEN_HANDLER_E(rvwinkle
, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
6911 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H
),
6913 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW
),
6914 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
),
6915 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
6916 #if defined(TARGET_PPC64)
6917 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
),
6918 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
),
6920 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
),
6921 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
),
6922 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
),
6923 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
),
6924 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
),
6925 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
),
6926 #if defined(TARGET_PPC64)
6927 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
),
6928 GEN_HANDLER_E(setb
, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE
, PPC2_ISA300
),
6929 GEN_HANDLER_E(mcrxrx
, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE
, PPC2_ISA300
),
6931 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC
),
6932 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC
),
6933 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
),
6934 GEN_HANDLER_E(dcbfep
, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE
, PPC2_BOOKE206
),
6935 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
),
6936 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
),
6937 GEN_HANDLER_E(dcbstep
, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE
, PPC2_BOOKE206
),
6938 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE
),
6939 GEN_HANDLER_E(dcbtep
, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE
, PPC2_BOOKE206
),
6940 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE
),
6941 GEN_HANDLER_E(dcbtstep
, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE
, PPC2_BOOKE206
),
6942 GEN_HANDLER_E(dcbtls
, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE
, PPC2_BOOKE206
),
6943 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ
),
6944 GEN_HANDLER_E(dcbzep
, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE
, PPC2_BOOKE206
),
6945 GEN_HANDLER(dst
, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC
),
6946 GEN_HANDLER(dstst
, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC
),
6947 GEN_HANDLER(dss
, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC
),
6948 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI
),
6949 GEN_HANDLER_E(icbiep
, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE
, PPC2_BOOKE206
),
6950 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
),
6951 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
),
6952 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
),
6953 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
),
6954 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
),
6955 #if defined(TARGET_PPC64)
6956 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
),
6957 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6959 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
),
6960 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6962 GEN_HANDLER2(slbmte
, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B
),
6963 GEN_HANDLER2(slbmfee
, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B
),
6964 GEN_HANDLER2(slbmfev
, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B
),
6965 GEN_HANDLER2(slbfee_
, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B
),
6967 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
),
6968 /* XXX Those instructions will need to be handled differently for
6969 * different ISA versions */
6970 GEN_HANDLER(tlbiel
, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE
),
6971 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE
),
6972 GEN_HANDLER_E(tlbiel
, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE
, PPC2_ISA300
),
6973 GEN_HANDLER_E(tlbie
, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE
, PPC2_ISA300
),
6974 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
),
6975 #if defined(TARGET_PPC64)
6976 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI
),
6977 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
),
6978 GEN_HANDLER_E(slbieg
, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE
, PPC2_ISA300
),
6979 GEN_HANDLER_E(slbsync
, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE
, PPC2_ISA300
),
6981 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
),
6982 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
),
6983 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
),
6984 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
),
6985 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
),
6986 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
),
6987 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
),
6988 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
),
6989 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
),
6990 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
),
6991 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
),
6992 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
6993 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
),
6994 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
),
6995 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
),
6996 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
),
6997 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
),
6998 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
),
6999 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
),
7000 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
7001 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
),
7002 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
),
7003 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
),
7004 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
),
7005 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
),
7006 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
),
7007 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
),
7008 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
),
7009 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
),
7010 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
),
7011 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
),
7012 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
),
7013 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
),
7014 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
),
7015 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
),
7016 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
),
7017 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
),
7018 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
),
7019 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
),
7020 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
),
7021 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
),
7022 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
),
7023 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
),
7024 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
),
7025 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
),
7026 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
),
7027 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
),
7028 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
),
7029 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
),
7030 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
7031 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
7032 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
),
7033 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
),
7034 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
7035 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
7036 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
),
7037 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
),
7038 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI
),
7039 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA
),
7040 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR
),
7041 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR
),
7042 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX
),
7043 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX
),
7044 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
),
7045 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
),
7046 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
),
7047 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
),
7048 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
),
7049 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
),
7050 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
),
7051 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
),
7052 GEN_HANDLER_E(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
, PPC2_BOOKE206
),
7053 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI
),
7054 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
),
7055 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
),
7056 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
),
7057 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
),
7058 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
),
7059 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
),
7060 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
),
7061 GEN_HANDLER2_E(tlbre_booke206
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
7062 PPC_NONE
, PPC2_BOOKE206
),
7063 GEN_HANDLER2_E(tlbsx_booke206
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
7064 PPC_NONE
, PPC2_BOOKE206
),
7065 GEN_HANDLER2_E(tlbwe_booke206
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
7066 PPC_NONE
, PPC2_BOOKE206
),
7067 GEN_HANDLER2_E(tlbivax_booke206
, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
7068 PPC_NONE
, PPC2_BOOKE206
),
7069 GEN_HANDLER2_E(tlbilx_booke206
, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
7070 PPC_NONE
, PPC2_BOOKE206
),
7071 GEN_HANDLER2_E(msgsnd
, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
7072 PPC_NONE
, PPC2_PRCNTL
),
7073 GEN_HANDLER2_E(msgclr
, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
7074 PPC_NONE
, PPC2_PRCNTL
),
7075 GEN_HANDLER2_E(msgsync
, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000,
7076 PPC_NONE
, PPC2_PRCNTL
),
7077 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE
),
7078 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE
),
7079 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
),
7080 GEN_HANDLER_E(mbar
, 0x1F, 0x16, 0x1a, 0x001FF801,
7081 PPC_BOOKE
, PPC2_BOOKE206
),
7082 GEN_HANDLER(msync_4xx
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE
),
7083 GEN_HANDLER2_E(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
7084 PPC_BOOKE
, PPC2_BOOKE206
),
7085 GEN_HANDLER2(icbt_440
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001,
7087 GEN_HANDLER(lvsl
, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC
),
7088 GEN_HANDLER(lvsr
, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC
),
7089 GEN_HANDLER(mfvscr
, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC
),
7090 GEN_HANDLER(mtvscr
, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC
),
7091 GEN_HANDLER(vmladduhm
, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC
),
7092 #if defined(TARGET_PPC64)
7093 GEN_HANDLER_E(maddhd_maddhdu
, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE
,
7095 GEN_HANDLER_E(maddld
, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA300
),
7098 #undef GEN_INT_ARITH_ADD
7099 #undef GEN_INT_ARITH_ADD_CONST
7100 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
7101 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
7102 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
7103 add_ca, compute_ca, compute_ov) \
7104 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
7105 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
7106 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
7107 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
7108 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
7109 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
7110 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
7111 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
7112 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
7113 GEN_HANDLER_E(addex
, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE
, PPC2_ISA300
),
7114 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
7115 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
7117 #undef GEN_INT_ARITH_DIVW
7118 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
7119 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
7120 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0),
7121 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1),
7122 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0),
7123 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1),
7124 GEN_HANDLER_E(divwe
, 0x1F, 0x0B, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7125 GEN_HANDLER_E(divweo
, 0x1F, 0x0B, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7126 GEN_HANDLER_E(divweu
, 0x1F, 0x0B, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7127 GEN_HANDLER_E(divweuo
, 0x1F, 0x0B, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7128 GEN_HANDLER_E(modsw
, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7129 GEN_HANDLER_E(moduw
, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7131 #if defined(TARGET_PPC64)
7132 #undef GEN_INT_ARITH_DIVD
7133 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
7134 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
7135 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0),
7136 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1),
7137 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0),
7138 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1),
7140 GEN_HANDLER_E(divdeu
, 0x1F, 0x09, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7141 GEN_HANDLER_E(divdeuo
, 0x1F, 0x09, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7142 GEN_HANDLER_E(divde
, 0x1F, 0x09, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7143 GEN_HANDLER_E(divdeo
, 0x1F, 0x09, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7144 GEN_HANDLER_E(modsd
, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7145 GEN_HANDLER_E(modud
, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7147 #undef GEN_INT_ARITH_MUL_HELPER
7148 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
7149 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
7150 GEN_INT_ARITH_MUL_HELPER(mulhdu
, 0x00),
7151 GEN_INT_ARITH_MUL_HELPER(mulhd
, 0x02),
7152 GEN_INT_ARITH_MUL_HELPER(mulldo
, 0x17),
7155 #undef GEN_INT_ARITH_SUBF
7156 #undef GEN_INT_ARITH_SUBF_CONST
7157 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
7158 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
7159 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
7160 add_ca, compute_ca, compute_ov) \
7161 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
7162 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
7163 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
7164 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
7165 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
7166 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
7167 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
7168 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
7169 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
7170 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
7171 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
7175 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
7176 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
7177 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
7178 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
7179 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
),
7180 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
),
7181 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
),
7182 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
),
7183 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
),
7184 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
),
7185 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
),
7186 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
),
7187 #if defined(TARGET_PPC64)
7188 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
),
7191 #if defined(TARGET_PPC64)
7194 #define GEN_PPC64_R2(name, opc1, opc2) \
7195 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
7196 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
7198 #define GEN_PPC64_R4(name, opc1, opc2) \
7199 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
7200 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
7202 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
7204 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
7206 GEN_PPC64_R4(rldicl
, 0x1E, 0x00),
7207 GEN_PPC64_R4(rldicr
, 0x1E, 0x02),
7208 GEN_PPC64_R4(rldic
, 0x1E, 0x04),
7209 GEN_PPC64_R2(rldcl
, 0x1E, 0x08),
7210 GEN_PPC64_R2(rldcr
, 0x1E, 0x09),
7211 GEN_PPC64_R4(rldimi
, 0x1E, 0x06),
7219 #define GEN_LD(name, ldop, opc, type) \
7220 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
7221 #define GEN_LDU(name, ldop, opc, type) \
7222 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
7223 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
7224 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
7225 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
7226 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
7227 #define GEN_LDS(name, ldop, op, type) \
7228 GEN_LD(name, ldop, op | 0x20, type) \
7229 GEN_LDU(name, ldop, op | 0x21, type) \
7230 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
7231 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
7233 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
)
7234 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
)
7235 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
)
7236 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
)
7237 #if defined(TARGET_PPC64)
7238 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
)
7239 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
)
7240 GEN_LDUX(ld
, ld64_i64
, 0x15, 0x01, PPC_64B
)
7241 GEN_LDX(ld
, ld64_i64
, 0x15, 0x00, PPC_64B
)
7242 GEN_LDX_E(ldbr
, ld64ur_i64
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
, CHK_NONE
)
7244 /* HV/P7 and later only */
7245 GEN_LDX_HVRM(ldcix
, ld64_i64
, 0x15, 0x1b, PPC_CILDST
)
7246 GEN_LDX_HVRM(lwzcix
, ld32u
, 0x15, 0x18, PPC_CILDST
)
7247 GEN_LDX_HVRM(lhzcix
, ld16u
, 0x15, 0x19, PPC_CILDST
)
7248 GEN_LDX_HVRM(lbzcix
, ld8u
, 0x15, 0x1a, PPC_CILDST
)
7250 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
)
7251 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
)
7253 /* External PID based load */
7255 #define GEN_LDEPX(name, ldop, opc2, opc3) \
7256 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
7257 0x00000001, PPC_NONE, PPC2_BOOKE206),
7259 GEN_LDEPX(lb
, DEF_MEMOP(MO_UB
), 0x1F, 0x02)
7260 GEN_LDEPX(lh
, DEF_MEMOP(MO_UW
), 0x1F, 0x08)
7261 GEN_LDEPX(lw
, DEF_MEMOP(MO_UL
), 0x1F, 0x00)
7262 #if defined(TARGET_PPC64)
7263 GEN_LDEPX(ld
, DEF_MEMOP(MO_Q
), 0x1D, 0x00)
7271 #define GEN_ST(name, stop, opc, type) \
7272 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
7273 #define GEN_STU(name, stop, opc, type) \
7274 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
7275 #define GEN_STUX(name, stop, opc2, opc3, type) \
7276 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
7277 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
7278 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
7279 #define GEN_STS(name, stop, op, type) \
7280 GEN_ST(name, stop, op | 0x20, type) \
7281 GEN_STU(name, stop, op | 0x21, type) \
7282 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
7283 GEN_STX(name, stop, 0x17, op | 0x00, type)
7285 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
)
7286 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
)
7287 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
)
7288 #if defined(TARGET_PPC64)
7289 GEN_STUX(std
, st64_i64
, 0x15, 0x05, PPC_64B
)
7290 GEN_STX(std
, st64_i64
, 0x15, 0x04, PPC_64B
)
7291 GEN_STX_E(stdbr
, st64r_i64
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
, CHK_NONE
)
7292 GEN_STX_HVRM(stdcix
, st64_i64
, 0x15, 0x1f, PPC_CILDST
)
7293 GEN_STX_HVRM(stwcix
, st32
, 0x15, 0x1c, PPC_CILDST
)
7294 GEN_STX_HVRM(sthcix
, st16
, 0x15, 0x1d, PPC_CILDST
)
7295 GEN_STX_HVRM(stbcix
, st8
, 0x15, 0x1e, PPC_CILDST
)
7297 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
)
7298 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
)
7301 #define GEN_STEPX(name, ldop, opc2, opc3) \
7302 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
7303 0x00000001, PPC_NONE, PPC2_BOOKE206),
7305 GEN_STEPX(stb
, DEF_MEMOP(MO_UB
), 0x1F, 0x06)
7306 GEN_STEPX(sth
, DEF_MEMOP(MO_UW
), 0x1F, 0x0C)
7307 GEN_STEPX(stw
, DEF_MEMOP(MO_UL
), 0x1F, 0x04)
7308 #if defined(TARGET_PPC64)
7309 GEN_STEPX(std
, DEF_MEMOP(MO_Q
), 0x1D, 0x04)
7313 #define GEN_CRLOGIC(name, tcg_op, opc) \
7314 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
7315 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08),
7316 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04),
7317 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09),
7318 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07),
7319 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01),
7320 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E),
7321 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D),
7322 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06),
7324 #undef GEN_MAC_HANDLER
7325 #define GEN_MAC_HANDLER(name, opc2, opc3) \
7326 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
7327 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05),
7328 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15),
7329 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07),
7330 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17),
7331 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06),
7332 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16),
7333 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04),
7334 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14),
7335 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01),
7336 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11),
7337 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03),
7338 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13),
7339 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02),
7340 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12),
7341 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00),
7342 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10),
7343 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D),
7344 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D),
7345 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F),
7346 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F),
7347 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C),
7348 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C),
7349 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E),
7350 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E),
7351 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05),
7352 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15),
7353 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07),
7354 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17),
7355 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01),
7356 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11),
7357 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03),
7358 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13),
7359 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D),
7360 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D),
7361 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F),
7362 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F),
7363 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05),
7364 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04),
7365 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01),
7366 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00),
7367 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D),
7368 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C),
7370 GEN_HANDLER2_E(tbegin
, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
7372 GEN_HANDLER2_E(tend
, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
7374 GEN_HANDLER2_E(tabort
, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
7376 GEN_HANDLER2_E(tabortwc
, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
7378 GEN_HANDLER2_E(tabortwci
, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
7380 GEN_HANDLER2_E(tabortdc
, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
7382 GEN_HANDLER2_E(tabortdci
, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
7384 GEN_HANDLER2_E(tsr
, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
7386 GEN_HANDLER2_E(tcheck
, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
7388 GEN_HANDLER2_E(treclaim
, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
7390 GEN_HANDLER2_E(trechkpt
, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
7393 #include "translate/fp-ops.inc.c"
7395 #include "translate/vmx-ops.inc.c"
7397 #include "translate/vsx-ops.inc.c"
7399 #include "translate/dfp-ops.inc.c"
7401 #include "translate/spe-ops.inc.c"
7404 #include "helper_regs.h"
7405 #include "translate_init.inc.c"
7407 /*****************************************************************************/
7408 /* Misc PowerPC helpers */
7409 void ppc_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
7415 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
7416 CPUPPCState
*env
= &cpu
->env
;
7419 cpu_fprintf(f
, "NIP " TARGET_FMT_lx
" LR " TARGET_FMT_lx
" CTR "
7420 TARGET_FMT_lx
" XER " TARGET_FMT_lx
" CPU#%d\n",
7421 env
->nip
, env
->lr
, env
->ctr
, cpu_read_xer(env
),
7423 cpu_fprintf(f
, "MSR " TARGET_FMT_lx
" HID0 " TARGET_FMT_lx
" HF "
7424 TARGET_FMT_lx
" iidx %d didx %d\n",
7425 env
->msr
, env
->spr
[SPR_HID0
],
7426 env
->hflags
, env
->immu_idx
, env
->dmmu_idx
);
7427 #if !defined(NO_TIMER_DUMP)
7428 cpu_fprintf(f
, "TB %08" PRIu32
" %08" PRIu64
7429 #if !defined(CONFIG_USER_ONLY)
7430 " DECR " TARGET_FMT_lu
7433 cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
7434 #if !defined(CONFIG_USER_ONLY)
7435 , cpu_ppc_load_decr(env
)
7439 for (i
= 0; i
< 32; i
++) {
7440 if ((i
& (RGPL
- 1)) == 0)
7441 cpu_fprintf(f
, "GPR%02d", i
);
7442 cpu_fprintf(f
, " %016" PRIx64
, ppc_dump_gpr(env
, i
));
7443 if ((i
& (RGPL
- 1)) == (RGPL
- 1))
7444 cpu_fprintf(f
, "\n");
7446 cpu_fprintf(f
, "CR ");
7447 for (i
= 0; i
< 8; i
++)
7448 cpu_fprintf(f
, "%01x", env
->crf
[i
]);
7449 cpu_fprintf(f
, " [");
7450 for (i
= 0; i
< 8; i
++) {
7452 if (env
->crf
[i
] & 0x08)
7454 else if (env
->crf
[i
] & 0x04)
7456 else if (env
->crf
[i
] & 0x02)
7458 cpu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
7460 cpu_fprintf(f
, " ] RES " TARGET_FMT_lx
"\n",
7463 if (flags
& CPU_DUMP_FPU
) {
7464 for (i
= 0; i
< 32; i
++) {
7465 if ((i
& (RFPL
- 1)) == 0) {
7466 cpu_fprintf(f
, "FPR%02d", i
);
7468 cpu_fprintf(f
, " %016" PRIx64
, *cpu_fpr_ptr(env
, i
));
7469 if ((i
& (RFPL
- 1)) == (RFPL
- 1)) {
7470 cpu_fprintf(f
, "\n");
7473 cpu_fprintf(f
, "FPSCR " TARGET_FMT_lx
"\n", env
->fpscr
);
7476 #if !defined(CONFIG_USER_ONLY)
7477 cpu_fprintf(f
, " SRR0 " TARGET_FMT_lx
" SRR1 " TARGET_FMT_lx
7478 " PVR " TARGET_FMT_lx
" VRSAVE " TARGET_FMT_lx
"\n",
7479 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
7480 env
->spr
[SPR_PVR
], env
->spr
[SPR_VRSAVE
]);
7482 cpu_fprintf(f
, "SPRG0 " TARGET_FMT_lx
" SPRG1 " TARGET_FMT_lx
7483 " SPRG2 " TARGET_FMT_lx
" SPRG3 " TARGET_FMT_lx
"\n",
7484 env
->spr
[SPR_SPRG0
], env
->spr
[SPR_SPRG1
],
7485 env
->spr
[SPR_SPRG2
], env
->spr
[SPR_SPRG3
]);
7487 cpu_fprintf(f
, "SPRG4 " TARGET_FMT_lx
" SPRG5 " TARGET_FMT_lx
7488 " SPRG6 " TARGET_FMT_lx
" SPRG7 " TARGET_FMT_lx
"\n",
7489 env
->spr
[SPR_SPRG4
], env
->spr
[SPR_SPRG5
],
7490 env
->spr
[SPR_SPRG6
], env
->spr
[SPR_SPRG7
]);
7492 #if defined(TARGET_PPC64)
7493 if (env
->excp_model
== POWERPC_EXCP_POWER7
||
7494 env
->excp_model
== POWERPC_EXCP_POWER8
||
7495 env
->excp_model
== POWERPC_EXCP_POWER9
) {
7496 cpu_fprintf(f
, "HSRR0 " TARGET_FMT_lx
" HSRR1 " TARGET_FMT_lx
"\n",
7497 env
->spr
[SPR_HSRR0
], env
->spr
[SPR_HSRR1
]);
7500 if (env
->excp_model
== POWERPC_EXCP_BOOKE
) {
7501 cpu_fprintf(f
, "CSRR0 " TARGET_FMT_lx
" CSRR1 " TARGET_FMT_lx
7502 " MCSRR0 " TARGET_FMT_lx
" MCSRR1 " TARGET_FMT_lx
"\n",
7503 env
->spr
[SPR_BOOKE_CSRR0
], env
->spr
[SPR_BOOKE_CSRR1
],
7504 env
->spr
[SPR_BOOKE_MCSRR0
], env
->spr
[SPR_BOOKE_MCSRR1
]);
7506 cpu_fprintf(f
, " TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
7507 " ESR " TARGET_FMT_lx
" DEAR " TARGET_FMT_lx
"\n",
7508 env
->spr
[SPR_BOOKE_TCR
], env
->spr
[SPR_BOOKE_TSR
],
7509 env
->spr
[SPR_BOOKE_ESR
], env
->spr
[SPR_BOOKE_DEAR
]);
7511 cpu_fprintf(f
, " PIR " TARGET_FMT_lx
" DECAR " TARGET_FMT_lx
7512 " IVPR " TARGET_FMT_lx
" EPCR " TARGET_FMT_lx
"\n",
7513 env
->spr
[SPR_BOOKE_PIR
], env
->spr
[SPR_BOOKE_DECAR
],
7514 env
->spr
[SPR_BOOKE_IVPR
], env
->spr
[SPR_BOOKE_EPCR
]);
7516 cpu_fprintf(f
, " MCSR " TARGET_FMT_lx
" SPRG8 " TARGET_FMT_lx
7517 " EPR " TARGET_FMT_lx
"\n",
7518 env
->spr
[SPR_BOOKE_MCSR
], env
->spr
[SPR_BOOKE_SPRG8
],
7519 env
->spr
[SPR_BOOKE_EPR
]);
7522 cpu_fprintf(f
, " MCAR " TARGET_FMT_lx
" PID1 " TARGET_FMT_lx
7523 " PID2 " TARGET_FMT_lx
" SVR " TARGET_FMT_lx
"\n",
7524 env
->spr
[SPR_Exxx_MCAR
], env
->spr
[SPR_BOOKE_PID1
],
7525 env
->spr
[SPR_BOOKE_PID2
], env
->spr
[SPR_E500_SVR
]);
7528 * IVORs are left out as they are large and do not change often --
7529 * they can be read with "p $ivor0", "p $ivor1", etc.
7533 #if defined(TARGET_PPC64)
7534 if (env
->flags
& POWERPC_FLAG_CFAR
) {
7535 cpu_fprintf(f
, " CFAR " TARGET_FMT_lx
"\n", env
->cfar
);
7539 if (env
->spr_cb
[SPR_LPCR
].name
)
7540 cpu_fprintf(f
, " LPCR " TARGET_FMT_lx
"\n", env
->spr
[SPR_LPCR
]);
7542 switch (env
->mmu_model
) {
7543 case POWERPC_MMU_32B
:
7544 case POWERPC_MMU_601
:
7545 case POWERPC_MMU_SOFT_6xx
:
7546 case POWERPC_MMU_SOFT_74xx
:
7547 #if defined(TARGET_PPC64)
7548 case POWERPC_MMU_64B
:
7549 case POWERPC_MMU_2_03
:
7550 case POWERPC_MMU_2_06
:
7551 case POWERPC_MMU_2_07
:
7552 case POWERPC_MMU_3_00
:
7554 if (env
->spr_cb
[SPR_SDR1
].name
) { /* SDR1 Exists */
7555 cpu_fprintf(f
, " SDR1 " TARGET_FMT_lx
" ", env
->spr
[SPR_SDR1
]);
7557 if (env
->spr_cb
[SPR_PTCR
].name
) { /* PTCR Exists */
7558 cpu_fprintf(f
, " PTCR " TARGET_FMT_lx
" ", env
->spr
[SPR_PTCR
]);
7560 cpu_fprintf(f
, " DAR " TARGET_FMT_lx
" DSISR " TARGET_FMT_lx
"\n",
7561 env
->spr
[SPR_DAR
], env
->spr
[SPR_DSISR
]);
7563 case POWERPC_MMU_BOOKE206
:
7564 cpu_fprintf(f
, " MAS0 " TARGET_FMT_lx
" MAS1 " TARGET_FMT_lx
7565 " MAS2 " TARGET_FMT_lx
" MAS3 " TARGET_FMT_lx
"\n",
7566 env
->spr
[SPR_BOOKE_MAS0
], env
->spr
[SPR_BOOKE_MAS1
],
7567 env
->spr
[SPR_BOOKE_MAS2
], env
->spr
[SPR_BOOKE_MAS3
]);
7569 cpu_fprintf(f
, " MAS4 " TARGET_FMT_lx
" MAS6 " TARGET_FMT_lx
7570 " MAS7 " TARGET_FMT_lx
" PID " TARGET_FMT_lx
"\n",
7571 env
->spr
[SPR_BOOKE_MAS4
], env
->spr
[SPR_BOOKE_MAS6
],
7572 env
->spr
[SPR_BOOKE_MAS7
], env
->spr
[SPR_BOOKE_PID
]);
7574 cpu_fprintf(f
, "MMUCFG " TARGET_FMT_lx
" TLB0CFG " TARGET_FMT_lx
7575 " TLB1CFG " TARGET_FMT_lx
"\n",
7576 env
->spr
[SPR_MMUCFG
], env
->spr
[SPR_BOOKE_TLB0CFG
],
7577 env
->spr
[SPR_BOOKE_TLB1CFG
]);
7588 void ppc_cpu_dump_statistics(CPUState
*cs
, FILE*f
,
7589 fprintf_function cpu_fprintf
, int flags
)
7591 #if defined(DO_PPC_STATISTICS)
7592 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
7593 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
7596 t1
= cpu
->env
.opcodes
;
7597 for (op1
= 0; op1
< 64; op1
++) {
7599 if (is_indirect_opcode(handler
)) {
7600 t2
= ind_table(handler
);
7601 for (op2
= 0; op2
< 32; op2
++) {
7603 if (is_indirect_opcode(handler
)) {
7604 t3
= ind_table(handler
);
7605 for (op3
= 0; op3
< 32; op3
++) {
7607 if (handler
->count
== 0)
7609 cpu_fprintf(f
, "%02x %02x %02x (%02x %04d) %16s: "
7610 "%016" PRIx64
" %" PRId64
"\n",
7611 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
7613 handler
->count
, handler
->count
);
7616 if (handler
->count
== 0)
7618 cpu_fprintf(f
, "%02x %02x (%02x %04d) %16s: "
7619 "%016" PRIx64
" %" PRId64
"\n",
7620 op1
, op2
, op1
, op2
, handler
->oname
,
7621 handler
->count
, handler
->count
);
7625 if (handler
->count
== 0)
7627 cpu_fprintf(f
, "%02x (%02x ) %16s: %016" PRIx64
7629 op1
, op1
, handler
->oname
,
7630 handler
->count
, handler
->count
);
7636 static void ppc_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
7638 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
7639 CPUPPCState
*env
= cs
->env_ptr
;
7642 ctx
->exception
= POWERPC_EXCP_NONE
;
7643 ctx
->spr_cb
= env
->spr_cb
;
7645 ctx
->mem_idx
= env
->dmmu_idx
;
7647 #if !defined(CONFIG_USER_ONLY)
7648 ctx
->hv
= msr_hv
|| !env
->has_hv_mode
;
7650 ctx
->insns_flags
= env
->insns_flags
;
7651 ctx
->insns_flags2
= env
->insns_flags2
;
7652 ctx
->access_type
= -1;
7653 ctx
->need_access_type
= !(env
->mmu_model
& POWERPC_MMU_64B
);
7654 ctx
->le_mode
= !!(env
->hflags
& (1 << MSR_LE
));
7655 ctx
->default_tcg_memop_mask
= ctx
->le_mode
? MO_LE
: MO_BE
;
7656 ctx
->flags
= env
->flags
;
7657 #if defined(TARGET_PPC64)
7658 ctx
->sf_mode
= msr_is_64bit(env
, env
->msr
);
7659 ctx
->has_cfar
= !!(env
->flags
& POWERPC_FLAG_CFAR
);
7661 ctx
->lazy_tlb_flush
= env
->mmu_model
== POWERPC_MMU_32B
7662 || env
->mmu_model
== POWERPC_MMU_601
7663 || (env
->mmu_model
& POWERPC_MMU_64B
);
7665 ctx
->fpu_enabled
= !!msr_fp
;
7666 if ((env
->flags
& POWERPC_FLAG_SPE
) && msr_spe
)
7667 ctx
->spe_enabled
= !!msr_spe
;
7669 ctx
->spe_enabled
= false;
7670 if ((env
->flags
& POWERPC_FLAG_VRE
) && msr_vr
)
7671 ctx
->altivec_enabled
= !!msr_vr
;
7673 ctx
->altivec_enabled
= false;
7674 if ((env
->flags
& POWERPC_FLAG_VSX
) && msr_vsx
) {
7675 ctx
->vsx_enabled
= !!msr_vsx
;
7677 ctx
->vsx_enabled
= false;
7679 #if defined(TARGET_PPC64)
7680 if ((env
->flags
& POWERPC_FLAG_TM
) && msr_tm
) {
7681 ctx
->tm_enabled
= !!msr_tm
;
7683 ctx
->tm_enabled
= false;
7686 ctx
->gtse
= !!(env
->spr
[SPR_LPCR
] & LPCR_GTSE
);
7687 if ((env
->flags
& POWERPC_FLAG_SE
) && msr_se
)
7688 ctx
->singlestep_enabled
= CPU_SINGLE_STEP
;
7690 ctx
->singlestep_enabled
= 0;
7691 if ((env
->flags
& POWERPC_FLAG_BE
) && msr_be
)
7692 ctx
->singlestep_enabled
|= CPU_BRANCH_STEP
;
7693 if ((env
->flags
& POWERPC_FLAG_DE
) && msr_de
) {
7694 ctx
->singlestep_enabled
= 0;
7695 target_ulong dbcr0
= env
->spr
[SPR_BOOKE_DBCR0
];
7696 if (dbcr0
& DBCR0_ICMP
) {
7697 ctx
->singlestep_enabled
|= CPU_SINGLE_STEP
;
7699 if (dbcr0
& DBCR0_BRT
) {
7700 ctx
->singlestep_enabled
|= CPU_BRANCH_STEP
;
7704 if (unlikely(ctx
->base
.singlestep_enabled
)) {
7705 ctx
->singlestep_enabled
|= GDBSTUB_SINGLE_STEP
;
7707 #if defined (DO_SINGLE_STEP) && 0
7708 /* Single step trace mode */
7712 bound
= -(ctx
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
7713 ctx
->base
.max_insns
= MIN(ctx
->base
.max_insns
, bound
);
7716 static void ppc_tr_tb_start(DisasContextBase
*db
, CPUState
*cs
)
7720 static void ppc_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cs
)
7722 tcg_gen_insn_start(dcbase
->pc_next
);
7725 static bool ppc_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cs
,
7726 const CPUBreakpoint
*bp
)
7728 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
7730 gen_debug_exception(ctx
);
7731 dcbase
->is_jmp
= DISAS_NORETURN
;
7732 /* The address covered by the breakpoint must be included in
7733 [tb->pc, tb->pc + tb->size) in order to for it to be
7734 properly cleared -- thus we increment the PC here so that
7735 the logic setting tb->size below does the right thing. */
7736 ctx
->base
.pc_next
+= 4;
7740 static void ppc_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cs
)
7742 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
7743 CPUPPCState
*env
= cs
->env_ptr
;
7744 opc_handler_t
**table
, *handler
;
7746 LOG_DISAS("----------------\n");
7747 LOG_DISAS("nip=" TARGET_FMT_lx
" super=%d ir=%d\n",
7748 ctx
->base
.pc_next
, ctx
->mem_idx
, (int)msr_ir
);
7750 if (unlikely(need_byteswap(ctx
))) {
7751 ctx
->opcode
= bswap32(cpu_ldl_code(env
, ctx
->base
.pc_next
));
7753 ctx
->opcode
= cpu_ldl_code(env
, ctx
->base
.pc_next
);
7755 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7756 ctx
->opcode
, opc1(ctx
->opcode
), opc2(ctx
->opcode
),
7757 opc3(ctx
->opcode
), opc4(ctx
->opcode
),
7758 ctx
->le_mode
? "little" : "big");
7759 ctx
->base
.pc_next
+= 4;
7760 table
= env
->opcodes
;
7761 handler
= table
[opc1(ctx
->opcode
)];
7762 if (is_indirect_opcode(handler
)) {
7763 table
= ind_table(handler
);
7764 handler
= table
[opc2(ctx
->opcode
)];
7765 if (is_indirect_opcode(handler
)) {
7766 table
= ind_table(handler
);
7767 handler
= table
[opc3(ctx
->opcode
)];
7768 if (is_indirect_opcode(handler
)) {
7769 table
= ind_table(handler
);
7770 handler
= table
[opc4(ctx
->opcode
)];
7774 /* Is opcode *REALLY* valid ? */
7775 if (unlikely(handler
->handler
== &gen_invalid
)) {
7776 qemu_log_mask(LOG_GUEST_ERROR
, "invalid/unsupported opcode: "
7777 "%02x - %02x - %02x - %02x (%08x) "
7778 TARGET_FMT_lx
" %d\n",
7779 opc1(ctx
->opcode
), opc2(ctx
->opcode
),
7780 opc3(ctx
->opcode
), opc4(ctx
->opcode
),
7781 ctx
->opcode
, ctx
->base
.pc_next
- 4, (int)msr_ir
);
7785 if (unlikely(handler
->type
& (PPC_SPE
| PPC_SPE_SINGLE
| PPC_SPE_DOUBLE
)
7786 && Rc(ctx
->opcode
))) {
7787 inval
= handler
->inval2
;
7789 inval
= handler
->inval1
;
7792 if (unlikely((ctx
->opcode
& inval
) != 0)) {
7793 qemu_log_mask(LOG_GUEST_ERROR
, "invalid bits: %08x for opcode: "
7794 "%02x - %02x - %02x - %02x (%08x) "
7795 TARGET_FMT_lx
"\n", ctx
->opcode
& inval
,
7796 opc1(ctx
->opcode
), opc2(ctx
->opcode
),
7797 opc3(ctx
->opcode
), opc4(ctx
->opcode
),
7798 ctx
->opcode
, ctx
->base
.pc_next
- 4);
7799 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
7800 ctx
->base
.is_jmp
= DISAS_NORETURN
;
7804 (*(handler
->handler
))(ctx
);
7805 #if defined(DO_PPC_STATISTICS)
7808 /* Check trace mode exceptions */
7809 if (unlikely(ctx
->singlestep_enabled
& CPU_SINGLE_STEP
&&
7810 (ctx
->base
.pc_next
<= 0x100 || ctx
->base
.pc_next
> 0xF00) &&
7811 ctx
->exception
!= POWERPC_SYSCALL
&&
7812 ctx
->exception
!= POWERPC_EXCP_TRAP
&&
7813 ctx
->exception
!= POWERPC_EXCP_BRANCH
)) {
7814 uint32_t excp
= gen_prep_dbgex(ctx
);
7815 gen_exception_nip(ctx
, excp
, ctx
->base
.pc_next
);
7818 if (tcg_check_temp_count()) {
7819 qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked "
7820 "temporaries\n", opc1(ctx
->opcode
), opc2(ctx
->opcode
),
7821 opc3(ctx
->opcode
), opc4(ctx
->opcode
), ctx
->opcode
);
7824 ctx
->base
.is_jmp
= ctx
->exception
== POWERPC_EXCP_NONE
?
7825 DISAS_NEXT
: DISAS_NORETURN
;
7828 static void ppc_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cs
)
7830 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
7832 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
7833 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
);
7834 } else if (ctx
->exception
!= POWERPC_EXCP_BRANCH
) {
7835 if (unlikely(ctx
->base
.singlestep_enabled
)) {
7836 gen_debug_exception(ctx
);
7838 /* Generate the return instruction */
7839 tcg_gen_exit_tb(NULL
, 0);
7843 static void ppc_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cs
)
7845 qemu_log("IN: %s\n", lookup_symbol(dcbase
->pc_first
));
7846 log_target_disas(cs
, dcbase
->pc_first
, dcbase
->tb
->size
);
7849 static const TranslatorOps ppc_tr_ops
= {
7850 .init_disas_context
= ppc_tr_init_disas_context
,
7851 .tb_start
= ppc_tr_tb_start
,
7852 .insn_start
= ppc_tr_insn_start
,
7853 .breakpoint_check
= ppc_tr_breakpoint_check
,
7854 .translate_insn
= ppc_tr_translate_insn
,
7855 .tb_stop
= ppc_tr_tb_stop
,
7856 .disas_log
= ppc_tr_disas_log
,
7859 void gen_intermediate_code(CPUState
*cs
, struct TranslationBlock
*tb
)
7863 translator_loop(&ppc_tr_ops
, &ctx
.base
, cs
, tb
);
7866 void restore_state_to_opc(CPUPPCState
*env
, TranslationBlock
*tb
,