4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #include "hw/core/cpu.h"
24 #include "exec/cpu-defs.h"
25 #include "fpu/softfloat-types.h"
27 #define TCG_GUEST_DEFAULT_MO 0
29 #define TYPE_RISCV_CPU "riscv-cpu"
31 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
32 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
33 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
35 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
36 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
37 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
38 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
39 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
40 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
41 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
43 #define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
44 #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
45 #define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
46 #define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
47 #define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
48 #define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
50 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
51 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
53 #if defined(TARGET_RISCV32)
55 #elif defined(TARGET_RISCV64)
59 #define RV(x) ((target_ulong)1 << (x - 'A'))
62 #define RVE RV('E') /* E and I are mutually exclusive */
72 /* S extension denotes that Supervisor mode exists, however it is possible
73 to have a core that support S mode but does not have an MMU and there
74 is currently no bit in misa to indicate whether an MMU exists or not
75 so a cpu features bitfield is required, likewise for optional PMP support */
82 #define PRIV_VERSION_1_09_1 0x00010901
83 #define PRIV_VERSION_1_10_0 0x00011000
84 #define PRIV_VERSION_1_11_0 0x00011100
86 #define TRANSLATE_PMP_FAIL 2
87 #define TRANSLATE_FAIL 1
88 #define TRANSLATE_SUCCESS 0
89 #define MMU_USER_IDX 3
91 #define MAX_RISCV_PMPS (16)
93 typedef struct CPURISCVState CPURISCVState
;
97 struct CPURISCVState
{
99 uint64_t fpr
[32]; /* assume both F and D extensions */
101 target_ulong load_res
;
102 target_ulong load_val
;
106 target_ulong badaddr
;
108 target_ulong priv_ver
;
110 target_ulong misa_mask
;
114 #ifdef CONFIG_USER_ONLY
118 #ifndef CONFIG_USER_ONLY
120 /* This contains QEMU specific information about the virt state. */
122 target_ulong resetvec
;
124 target_ulong mhartid
;
125 target_ulong mstatus
;
131 target_ulong mideleg
;
133 target_ulong sptbr
; /* until: priv-1.9.1 */
134 target_ulong satp
; /* since: priv-1.10.0 */
135 target_ulong sbadaddr
;
136 target_ulong mbadaddr
;
137 target_ulong medeleg
;
146 target_ulong mtval
; /* since: priv-1.10.0 */
148 /* Hypervisor CSRs */
149 target_ulong hstatus
;
150 target_ulong hedeleg
;
151 target_ulong hideleg
;
152 target_ulong hcounteren
;
158 target_ulong vsstatus
;
160 target_ulong vsscratch
;
162 target_ulong vscause
;
169 target_ulong scounteren
;
170 target_ulong mcounteren
;
172 target_ulong sscratch
;
173 target_ulong mscratch
;
175 /* temporary htif regs */
180 /* physical memory protection */
181 pmp_table_t pmp_state
;
183 /* True if in debugger mode. */
187 float_status fp_status
;
189 /* Fields from here on are preserved across CPU reset. */
190 QEMUTimer
*timer
; /* Internal timer */
193 #define RISCV_CPU_CLASS(klass) \
194 OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU)
195 #define RISCV_CPU(obj) \
196 OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU)
197 #define RISCV_CPU_GET_CLASS(obj) \
198 OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU)
202 * @parent_realize: The parent class' realize handler.
203 * @parent_reset: The parent class' reset handler.
207 typedef struct RISCVCPUClass
{
209 CPUClass parent_class
;
211 DeviceRealize parent_realize
;
212 void (*parent_reset
)(CPUState
*cpu
);
217 * @env: #CPURISCVState
221 typedef struct RISCVCPU
{
225 CPUNegativeOffsetState neg
;
228 /* Configuration Settings */
251 static inline int riscv_has_ext(CPURISCVState
*env
, target_ulong ext
)
253 return (env
->misa
& ext
) != 0;
256 static inline bool riscv_feature(CPURISCVState
*env
, int feature
)
258 return env
->features
& (1ULL << feature
);
261 #include "cpu_user.h"
262 #include "cpu_bits.h"
264 extern const char * const riscv_int_regnames
[];
265 extern const char * const riscv_fpr_regnames
[];
266 extern const char * const riscv_excp_names
[];
267 extern const char * const riscv_intr_names
[];
269 void riscv_cpu_do_interrupt(CPUState
*cpu
);
270 int riscv_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
271 int riscv_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
272 bool riscv_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
);
273 bool riscv_cpu_fp_enabled(CPURISCVState
*env
);
274 bool riscv_cpu_virt_enabled(CPURISCVState
*env
);
275 void riscv_cpu_set_virt_enabled(CPURISCVState
*env
, bool enable
);
276 int riscv_cpu_mmu_index(CPURISCVState
*env
, bool ifetch
);
277 hwaddr
riscv_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
278 void riscv_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
279 MMUAccessType access_type
, int mmu_idx
,
281 bool riscv_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
282 MMUAccessType access_type
, int mmu_idx
,
283 bool probe
, uintptr_t retaddr
);
284 void riscv_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
285 vaddr addr
, unsigned size
,
286 MMUAccessType access_type
,
287 int mmu_idx
, MemTxAttrs attrs
,
288 MemTxResult response
, uintptr_t retaddr
);
289 char *riscv_isa_string(RISCVCPU
*cpu
);
290 void riscv_cpu_list(void);
292 #define cpu_signal_handler riscv_cpu_signal_handler
293 #define cpu_list riscv_cpu_list
294 #define cpu_mmu_index riscv_cpu_mmu_index
296 #ifndef CONFIG_USER_ONLY
297 int riscv_cpu_claim_interrupts(RISCVCPU
*cpu
, uint32_t interrupts
);
298 uint32_t riscv_cpu_update_mip(RISCVCPU
*cpu
, uint32_t mask
, uint32_t value
);
299 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
301 void riscv_cpu_set_mode(CPURISCVState
*env
, target_ulong newpriv
);
303 void riscv_translate_init(void);
304 int riscv_cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
);
305 void QEMU_NORETURN
riscv_raise_exception(CPURISCVState
*env
,
306 uint32_t exception
, uintptr_t pc
);
308 target_ulong
riscv_cpu_get_fflags(CPURISCVState
*env
);
309 void riscv_cpu_set_fflags(CPURISCVState
*env
, target_ulong
);
311 #define TB_FLAGS_MMU_MASK 3
312 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
314 static inline void cpu_get_tb_cpu_state(CPURISCVState
*env
, target_ulong
*pc
,
315 target_ulong
*cs_base
, uint32_t *flags
)
319 #ifdef CONFIG_USER_ONLY
320 *flags
= TB_FLAGS_MSTATUS_FS
;
322 *flags
= cpu_mmu_index(env
, 0) | (env
->mstatus
& MSTATUS_FS
);
326 int riscv_csrrw(CPURISCVState
*env
, int csrno
, target_ulong
*ret_value
,
327 target_ulong new_value
, target_ulong write_mask
);
328 int riscv_csrrw_debug(CPURISCVState
*env
, int csrno
, target_ulong
*ret_value
,
329 target_ulong new_value
, target_ulong write_mask
);
331 static inline void riscv_csr_write(CPURISCVState
*env
, int csrno
,
334 riscv_csrrw(env
, csrno
, NULL
, val
, MAKE_64BIT_MASK(0, TARGET_LONG_BITS
));
337 static inline target_ulong
riscv_csr_read(CPURISCVState
*env
, int csrno
)
339 target_ulong val
= 0;
340 riscv_csrrw(env
, csrno
, &val
, 0, 0);
344 typedef int (*riscv_csr_predicate_fn
)(CPURISCVState
*env
, int csrno
);
345 typedef int (*riscv_csr_read_fn
)(CPURISCVState
*env
, int csrno
,
346 target_ulong
*ret_value
);
347 typedef int (*riscv_csr_write_fn
)(CPURISCVState
*env
, int csrno
,
348 target_ulong new_value
);
349 typedef int (*riscv_csr_op_fn
)(CPURISCVState
*env
, int csrno
,
350 target_ulong
*ret_value
, target_ulong new_value
, target_ulong write_mask
);
353 riscv_csr_predicate_fn predicate
;
354 riscv_csr_read_fn read
;
355 riscv_csr_write_fn write
;
357 } riscv_csr_operations
;
359 void riscv_get_csr_ops(int csrno
, riscv_csr_operations
*ops
);
360 void riscv_set_csr_ops(int csrno
, riscv_csr_operations
*ops
);
362 void riscv_cpu_register_gdb_regs_for_features(CPUState
*cs
);
364 typedef CPURISCVState CPUArchState
;
365 typedef RISCVCPU ArchCPU
;
367 #include "exec/cpu-all.h"
369 #endif /* RISCV_CPU_H */