target/riscv/cpu.h

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef RISCV_CPU_H
  21 #define RISCV_CPU_H
  22
  23 #include "hw/core/cpu.h"
  24 #include "exec/cpu-defs.h"
  25 #include "fpu/softfloat-types.h"
  26
  27 #define TCG_GUEST_DEFAULT_MO 0
  28
  29 #define TYPE_RISCV_CPU "riscv-cpu"
  30
  31 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
  32 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
  33 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
  34
  35 #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
  36 #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
  37 #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
  38 #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
  39 #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
  40 #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
  41 #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
  42 /* Deprecated */
  43 #define TYPE_RISCV_CPU_RV32IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
  44 #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
  45 #define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
  46 #define TYPE_RISCV_CPU_RV64IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
  47 #define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
  48 #define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
  49
  50 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
  51 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
  52
  53 #if defined(TARGET_RISCV32)
  54 #define RVXLEN RV32
  55 #elif defined(TARGET_RISCV64)
  56 #define RVXLEN RV64
  57 #endif
  58
  59 #define RV(x) ((target_ulong)1 << (x - 'A'))
  60
  61 #define RVI RV('I')
  62 #define RVE RV('E') /* E and I are mutually exclusive */
  63 #define RVM RV('M')
  64 #define RVA RV('A')
  65 #define RVF RV('F')
  66 #define RVD RV('D')
  67 #define RVC RV('C')
  68 #define RVS RV('S')
  69 #define RVU RV('U')
  70
  71 /* S extension denotes that Supervisor mode exists, however it is possible
  72    to have a core that support S mode but does not have an MMU and there
  73    is currently no bit in misa to indicate whether an MMU exists or not
  74    so a cpu features bitfield is required, likewise for optional PMP support */
  75 enum {
  76     RISCV_FEATURE_MMU,
  77     RISCV_FEATURE_PMP,
  78     RISCV_FEATURE_MISA
  79 };
  80
  81 #define PRIV_VERSION_1_09_1 0x00010901
  82 #define PRIV_VERSION_1_10_0 0x00011000
  83 #define PRIV_VERSION_1_11_0 0x00011100
  84
  85 #define TRANSLATE_PMP_FAIL 2
  86 #define TRANSLATE_FAIL 1
  87 #define TRANSLATE_SUCCESS 0
  88 #define MMU_USER_IDX 3
  89
  90 #define MAX_RISCV_PMPS (16)
  91
  92 typedef struct CPURISCVState CPURISCVState;
  93
  94 #include "pmp.h"
  95
  96 struct CPURISCVState {
  97     target_ulong gpr[32];
  98     uint64_t fpr[32]; /* assume both F and D extensions */
  99     target_ulong pc;
 100     target_ulong load_res;
 101     target_ulong load_val;
 102
 103     target_ulong frm;
 104
 105     target_ulong badaddr;
 106
 107     target_ulong priv_ver;
 108     target_ulong misa;
 109     target_ulong misa_mask;
 110
 111     uint32_t features;
 112
 113 #ifdef CONFIG_USER_ONLY
 114     uint32_t elf_flags;
 115 #endif
 116
 117 #ifndef CONFIG_USER_ONLY
 118     target_ulong priv;
 119     target_ulong resetvec;
 120
 121     target_ulong mhartid;
 122     target_ulong mstatus;
 123
 124     target_ulong mip;
 125     uint32_t miclaim;
 126
 127     target_ulong mie;
 128     target_ulong mideleg;
 129
 130     target_ulong sptbr;  /* until: priv-1.9.1 */
 131     target_ulong satp;   /* since: priv-1.10.0 */
 132     target_ulong sbadaddr;
 133     target_ulong mbadaddr;
 134     target_ulong medeleg;
 135
 136     target_ulong stvec;
 137     target_ulong sepc;
 138     target_ulong scause;
 139
 140     target_ulong mtvec;
 141     target_ulong mepc;
 142     target_ulong mcause;
 143     target_ulong mtval;  /* since: priv-1.10.0 */
 144
 145     target_ulong scounteren;
 146     target_ulong mcounteren;
 147
 148     target_ulong sscratch;
 149     target_ulong mscratch;
 150
 151     /* temporary htif regs */
 152     uint64_t mfromhost;
 153     uint64_t mtohost;
 154     uint64_t timecmp;
 155
 156     /* physical memory protection */
 157     pmp_table_t pmp_state;
 158
 159     /* True if in debugger mode.  */
 160     bool debugger;
 161 #endif
 162
 163     float_status fp_status;
 164
 165     /* Fields from here on are preserved across CPU reset. */
 166     QEMUTimer *timer; /* Internal timer */
 167 };
 168
 169 #define RISCV_CPU_CLASS(klass) \
 170     OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU)
 171 #define RISCV_CPU(obj) \
 172     OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU)
 173 #define RISCV_CPU_GET_CLASS(obj) \
 174     OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU)
 175
 176 /**
 177  * RISCVCPUClass:
 178  * @parent_realize: The parent class' realize handler.
 179  * @parent_reset: The parent class' reset handler.
 180  *
 181  * A RISCV CPU model.
 182  */
 183 typedef struct RISCVCPUClass {
 184     /*< private >*/
 185     CPUClass parent_class;
 186     /*< public >*/
 187     DeviceRealize parent_realize;
 188     void (*parent_reset)(CPUState *cpu);
 189 } RISCVCPUClass;
 190
 191 /**
 192  * RISCVCPU:
 193  * @env: #CPURISCVState
 194  *
 195  * A RISCV CPU.
 196  */
 197 typedef struct RISCVCPU {
 198     /*< private >*/
 199     CPUState parent_obj;
 200     /*< public >*/
 201     CPUNegativeOffsetState neg;
 202     CPURISCVState env;
 203
 204     /* Configuration Settings */
 205     struct {
 206         bool ext_i;
 207         bool ext_e;
 208         bool ext_g;
 209         bool ext_m;
 210         bool ext_a;
 211         bool ext_f;
 212         bool ext_d;
 213         bool ext_c;
 214         bool ext_s;
 215         bool ext_u;
 216         bool ext_counters;
 217         bool ext_ifencei;
 218         bool ext_icsr;
 219
 220         char *priv_spec;
 221         char *user_spec;
 222         bool mmu;
 223         bool pmp;
 224     } cfg;
 225 } RISCVCPU;
 226
 227 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
 228 {
 229     return (env->misa & ext) != 0;
 230 }
 231
 232 static inline bool riscv_feature(CPURISCVState *env, int feature)
 233 {
 234     return env->features & (1ULL << feature);
 235 }
 236
 237 #include "cpu_user.h"
 238 #include "cpu_bits.h"
 239
 240 extern const char * const riscv_int_regnames[];
 241 extern const char * const riscv_fpr_regnames[];
 242 extern const char * const riscv_excp_names[];
 243 extern const char * const riscv_intr_names[];
 244
 245 void riscv_cpu_do_interrupt(CPUState *cpu);
 246 int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 247 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 248 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
 249 bool riscv_cpu_fp_enabled(CPURISCVState *env);
 250 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
 251 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 252 void  riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 253                                     MMUAccessType access_type, int mmu_idx,
 254                                     uintptr_t retaddr);
 255 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 256                         MMUAccessType access_type, int mmu_idx,
 257                         bool probe, uintptr_t retaddr);
 258 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 259                                      vaddr addr, unsigned size,
 260                                      MMUAccessType access_type,
 261                                      int mmu_idx, MemTxAttrs attrs,
 262                                      MemTxResult response, uintptr_t retaddr);
 263 char *riscv_isa_string(RISCVCPU *cpu);
 264 void riscv_cpu_list(void);
 265
 266 #define cpu_signal_handler riscv_cpu_signal_handler
 267 #define cpu_list riscv_cpu_list
 268 #define cpu_mmu_index riscv_cpu_mmu_index
 269
 270 #ifndef CONFIG_USER_ONLY
 271 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
 272 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
 273 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
 274 #endif
 275 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
 276
 277 void riscv_translate_init(void);
 278 int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
 279 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
 280                                          uint32_t exception, uintptr_t pc);
 281
 282 target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
 283 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
 284
 285 #define TB_FLAGS_MMU_MASK   3
 286 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
 287
 288 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
 289                                         target_ulong *cs_base, uint32_t *flags)
 290 {
 291     *pc = env->pc;
 292     *cs_base = 0;
 293 #ifdef CONFIG_USER_ONLY
 294     *flags = TB_FLAGS_MSTATUS_FS;
 295 #else
 296     *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS);
 297 #endif
 298 }
 299
 300 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
 301                 target_ulong new_value, target_ulong write_mask);
 302 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
 303                       target_ulong new_value, target_ulong write_mask);
 304
 305 static inline void riscv_csr_write(CPURISCVState *env, int csrno,
 306                                    target_ulong val)
 307 {
 308     riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
 309 }
 310
 311 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
 312 {
 313     target_ulong val = 0;
 314     riscv_csrrw(env, csrno, &val, 0, 0);
 315     return val;
 316 }
 317
 318 typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno);
 319 typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
 320     target_ulong *ret_value);
 321 typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
 322     target_ulong new_value);
 323 typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
 324     target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
 325
 326 typedef struct {
 327     riscv_csr_predicate_fn predicate;
 328     riscv_csr_read_fn read;
 329     riscv_csr_write_fn write;
 330     riscv_csr_op_fn op;
 331 } riscv_csr_operations;
 332
 333 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
 334 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 335
 336 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 337
 338 typedef CPURISCVState CPUArchState;
 339 typedef RISCVCPU ArchCPU;
 340
 341 #include "exec/cpu-all.h"
 342
 343 #endif /* RISCV_CPU_H */