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include/qemu/osdep.h: Don't include qapi/error.h
[thirdparty/qemu.git] / target-i386 / kvm.c
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/mman.h>
19 #include <sys/utsname.h>
20
21 #include <linux/kvm.h>
22 #include <linux/kvm_para.h>
23
24 #include "qemu-common.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/kvm_int.h"
27 #include "kvm_i386.h"
28 #include "cpu.h"
29 #include "hyperv.h"
30
31 #include "exec/gdbstub.h"
32 #include "qemu/host-utils.h"
33 #include "qemu/config-file.h"
34 #include "qemu/error-report.h"
35 #include "hw/i386/pc.h"
36 #include "hw/i386/apic.h"
37 #include "hw/i386/apic_internal.h"
38 #include "hw/i386/apic-msidef.h"
39
40 #include "exec/ioport.h"
41 #include "standard-headers/asm-x86/hyperv.h"
42 #include "hw/pci/pci.h"
43 #include "hw/pci/msi.h"
44 #include "migration/migration.h"
45 #include "exec/memattrs.h"
46
47 //#define DEBUG_KVM
48
49 #ifdef DEBUG_KVM
50 #define DPRINTF(fmt, ...) \
51 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
52 #else
53 #define DPRINTF(fmt, ...) \
54 do { } while (0)
55 #endif
56
57 #define MSR_KVM_WALL_CLOCK 0x11
58 #define MSR_KVM_SYSTEM_TIME 0x12
59
60 #ifndef BUS_MCEERR_AR
61 #define BUS_MCEERR_AR 4
62 #endif
63 #ifndef BUS_MCEERR_AO
64 #define BUS_MCEERR_AO 5
65 #endif
66
67 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
68 KVM_CAP_INFO(SET_TSS_ADDR),
69 KVM_CAP_INFO(EXT_CPUID),
70 KVM_CAP_INFO(MP_STATE),
71 KVM_CAP_LAST_INFO
72 };
73
74 static bool has_msr_star;
75 static bool has_msr_hsave_pa;
76 static bool has_msr_tsc_aux;
77 static bool has_msr_tsc_adjust;
78 static bool has_msr_tsc_deadline;
79 static bool has_msr_feature_control;
80 static bool has_msr_async_pf_en;
81 static bool has_msr_pv_eoi_en;
82 static bool has_msr_misc_enable;
83 static bool has_msr_smbase;
84 static bool has_msr_bndcfgs;
85 static bool has_msr_kvm_steal_time;
86 static int lm_capable_kernel;
87 static bool has_msr_hv_hypercall;
88 static bool has_msr_hv_vapic;
89 static bool has_msr_hv_tsc;
90 static bool has_msr_hv_crash;
91 static bool has_msr_hv_reset;
92 static bool has_msr_hv_vpindex;
93 static bool has_msr_hv_runtime;
94 static bool has_msr_hv_synic;
95 static bool has_msr_hv_stimer;
96 static bool has_msr_mtrr;
97 static bool has_msr_xss;
98
99 static bool has_msr_architectural_pmu;
100 static uint32_t num_architectural_pmu_counters;
101
102 static int has_xsave;
103 static int has_xcrs;
104 static int has_pit_state2;
105
106 int kvm_has_pit_state2(void)
107 {
108 return has_pit_state2;
109 }
110
111 bool kvm_has_smm(void)
112 {
113 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
114 }
115
116 bool kvm_allows_irq0_override(void)
117 {
118 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
119 }
120
121 static int kvm_get_tsc(CPUState *cs)
122 {
123 X86CPU *cpu = X86_CPU(cs);
124 CPUX86State *env = &cpu->env;
125 struct {
126 struct kvm_msrs info;
127 struct kvm_msr_entry entries[1];
128 } msr_data;
129 int ret;
130
131 if (env->tsc_valid) {
132 return 0;
133 }
134
135 msr_data.info.nmsrs = 1;
136 msr_data.entries[0].index = MSR_IA32_TSC;
137 env->tsc_valid = !runstate_is_running();
138
139 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
140 if (ret < 0) {
141 return ret;
142 }
143
144 env->tsc = msr_data.entries[0].data;
145 return 0;
146 }
147
148 static inline void do_kvm_synchronize_tsc(void *arg)
149 {
150 CPUState *cpu = arg;
151
152 kvm_get_tsc(cpu);
153 }
154
155 void kvm_synchronize_all_tsc(void)
156 {
157 CPUState *cpu;
158
159 if (kvm_enabled()) {
160 CPU_FOREACH(cpu) {
161 run_on_cpu(cpu, do_kvm_synchronize_tsc, cpu);
162 }
163 }
164 }
165
166 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
167 {
168 struct kvm_cpuid2 *cpuid;
169 int r, size;
170
171 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
172 cpuid = g_malloc0(size);
173 cpuid->nent = max;
174 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
175 if (r == 0 && cpuid->nent >= max) {
176 r = -E2BIG;
177 }
178 if (r < 0) {
179 if (r == -E2BIG) {
180 g_free(cpuid);
181 return NULL;
182 } else {
183 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
184 strerror(-r));
185 exit(1);
186 }
187 }
188 return cpuid;
189 }
190
191 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
192 * for all entries.
193 */
194 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
195 {
196 struct kvm_cpuid2 *cpuid;
197 int max = 1;
198 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
199 max *= 2;
200 }
201 return cpuid;
202 }
203
204 static const struct kvm_para_features {
205 int cap;
206 int feature;
207 } para_features[] = {
208 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
209 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
210 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
211 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
212 };
213
214 static int get_para_features(KVMState *s)
215 {
216 int i, features = 0;
217
218 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
219 if (kvm_check_extension(s, para_features[i].cap)) {
220 features |= (1 << para_features[i].feature);
221 }
222 }
223
224 return features;
225 }
226
227
228 /* Returns the value for a specific register on the cpuid entry
229 */
230 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
231 {
232 uint32_t ret = 0;
233 switch (reg) {
234 case R_EAX:
235 ret = entry->eax;
236 break;
237 case R_EBX:
238 ret = entry->ebx;
239 break;
240 case R_ECX:
241 ret = entry->ecx;
242 break;
243 case R_EDX:
244 ret = entry->edx;
245 break;
246 }
247 return ret;
248 }
249
250 /* Find matching entry for function/index on kvm_cpuid2 struct
251 */
252 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
253 uint32_t function,
254 uint32_t index)
255 {
256 int i;
257 for (i = 0; i < cpuid->nent; ++i) {
258 if (cpuid->entries[i].function == function &&
259 cpuid->entries[i].index == index) {
260 return &cpuid->entries[i];
261 }
262 }
263 /* not found: */
264 return NULL;
265 }
266
267 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
268 uint32_t index, int reg)
269 {
270 struct kvm_cpuid2 *cpuid;
271 uint32_t ret = 0;
272 uint32_t cpuid_1_edx;
273 bool found = false;
274
275 cpuid = get_supported_cpuid(s);
276
277 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
278 if (entry) {
279 found = true;
280 ret = cpuid_entry_get_reg(entry, reg);
281 }
282
283 /* Fixups for the data returned by KVM, below */
284
285 if (function == 1 && reg == R_EDX) {
286 /* KVM before 2.6.30 misreports the following features */
287 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
288 } else if (function == 1 && reg == R_ECX) {
289 /* We can set the hypervisor flag, even if KVM does not return it on
290 * GET_SUPPORTED_CPUID
291 */
292 ret |= CPUID_EXT_HYPERVISOR;
293 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
294 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
295 * and the irqchip is in the kernel.
296 */
297 if (kvm_irqchip_in_kernel() &&
298 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
299 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
300 }
301
302 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
303 * without the in-kernel irqchip
304 */
305 if (!kvm_irqchip_in_kernel()) {
306 ret &= ~CPUID_EXT_X2APIC;
307 }
308 } else if (function == 6 && reg == R_EAX) {
309 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
310 } else if (function == 0x80000001 && reg == R_EDX) {
311 /* On Intel, kvm returns cpuid according to the Intel spec,
312 * so add missing bits according to the AMD spec:
313 */
314 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
315 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
316 }
317
318 g_free(cpuid);
319
320 /* fallback for older kernels */
321 if ((function == KVM_CPUID_FEATURES) && !found) {
322 ret = get_para_features(s);
323 }
324
325 return ret;
326 }
327
328 typedef struct HWPoisonPage {
329 ram_addr_t ram_addr;
330 QLIST_ENTRY(HWPoisonPage) list;
331 } HWPoisonPage;
332
333 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
334 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
335
336 static void kvm_unpoison_all(void *param)
337 {
338 HWPoisonPage *page, *next_page;
339
340 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
341 QLIST_REMOVE(page, list);
342 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
343 g_free(page);
344 }
345 }
346
347 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
348 {
349 HWPoisonPage *page;
350
351 QLIST_FOREACH(page, &hwpoison_page_list, list) {
352 if (page->ram_addr == ram_addr) {
353 return;
354 }
355 }
356 page = g_new(HWPoisonPage, 1);
357 page->ram_addr = ram_addr;
358 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
359 }
360
361 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
362 int *max_banks)
363 {
364 int r;
365
366 r = kvm_check_extension(s, KVM_CAP_MCE);
367 if (r > 0) {
368 *max_banks = r;
369 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
370 }
371 return -ENOSYS;
372 }
373
374 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
375 {
376 CPUX86State *env = &cpu->env;
377 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
378 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
379 uint64_t mcg_status = MCG_STATUS_MCIP;
380
381 if (code == BUS_MCEERR_AR) {
382 status |= MCI_STATUS_AR | 0x134;
383 mcg_status |= MCG_STATUS_EIPV;
384 } else {
385 status |= 0xc0;
386 mcg_status |= MCG_STATUS_RIPV;
387 }
388 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
389 (MCM_ADDR_PHYS << 6) | 0xc,
390 cpu_x86_support_mca_broadcast(env) ?
391 MCE_INJECT_BROADCAST : 0);
392 }
393
394 static void hardware_memory_error(void)
395 {
396 fprintf(stderr, "Hardware memory error!\n");
397 exit(1);
398 }
399
400 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
401 {
402 X86CPU *cpu = X86_CPU(c);
403 CPUX86State *env = &cpu->env;
404 ram_addr_t ram_addr;
405 hwaddr paddr;
406
407 if ((env->mcg_cap & MCG_SER_P) && addr
408 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
409 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
410 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
411 fprintf(stderr, "Hardware memory error for memory used by "
412 "QEMU itself instead of guest system!\n");
413 /* Hope we are lucky for AO MCE */
414 if (code == BUS_MCEERR_AO) {
415 return 0;
416 } else {
417 hardware_memory_error();
418 }
419 }
420 kvm_hwpoison_page_add(ram_addr);
421 kvm_mce_inject(cpu, paddr, code);
422 } else {
423 if (code == BUS_MCEERR_AO) {
424 return 0;
425 } else if (code == BUS_MCEERR_AR) {
426 hardware_memory_error();
427 } else {
428 return 1;
429 }
430 }
431 return 0;
432 }
433
434 int kvm_arch_on_sigbus(int code, void *addr)
435 {
436 X86CPU *cpu = X86_CPU(first_cpu);
437
438 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
439 ram_addr_t ram_addr;
440 hwaddr paddr;
441
442 /* Hope we are lucky for AO MCE */
443 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
444 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
445 addr, &paddr)) {
446 fprintf(stderr, "Hardware memory error for memory used by "
447 "QEMU itself instead of guest system!: %p\n", addr);
448 return 0;
449 }
450 kvm_hwpoison_page_add(ram_addr);
451 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
452 } else {
453 if (code == BUS_MCEERR_AO) {
454 return 0;
455 } else if (code == BUS_MCEERR_AR) {
456 hardware_memory_error();
457 } else {
458 return 1;
459 }
460 }
461 return 0;
462 }
463
464 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
465 {
466 CPUX86State *env = &cpu->env;
467
468 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
469 unsigned int bank, bank_num = env->mcg_cap & 0xff;
470 struct kvm_x86_mce mce;
471
472 env->exception_injected = -1;
473
474 /*
475 * There must be at least one bank in use if an MCE is pending.
476 * Find it and use its values for the event injection.
477 */
478 for (bank = 0; bank < bank_num; bank++) {
479 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
480 break;
481 }
482 }
483 assert(bank < bank_num);
484
485 mce.bank = bank;
486 mce.status = env->mce_banks[bank * 4 + 1];
487 mce.mcg_status = env->mcg_status;
488 mce.addr = env->mce_banks[bank * 4 + 2];
489 mce.misc = env->mce_banks[bank * 4 + 3];
490
491 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
492 }
493 return 0;
494 }
495
496 static void cpu_update_state(void *opaque, int running, RunState state)
497 {
498 CPUX86State *env = opaque;
499
500 if (running) {
501 env->tsc_valid = false;
502 }
503 }
504
505 unsigned long kvm_arch_vcpu_id(CPUState *cs)
506 {
507 X86CPU *cpu = X86_CPU(cs);
508 return cpu->apic_id;
509 }
510
511 #ifndef KVM_CPUID_SIGNATURE_NEXT
512 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
513 #endif
514
515 static bool hyperv_hypercall_available(X86CPU *cpu)
516 {
517 return cpu->hyperv_vapic ||
518 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
519 }
520
521 static bool hyperv_enabled(X86CPU *cpu)
522 {
523 CPUState *cs = CPU(cpu);
524 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
525 (hyperv_hypercall_available(cpu) ||
526 cpu->hyperv_time ||
527 cpu->hyperv_relaxed_timing ||
528 cpu->hyperv_crash ||
529 cpu->hyperv_reset ||
530 cpu->hyperv_vpindex ||
531 cpu->hyperv_runtime ||
532 cpu->hyperv_synic ||
533 cpu->hyperv_stimer);
534 }
535
536 static int kvm_arch_set_tsc_khz(CPUState *cs)
537 {
538 X86CPU *cpu = X86_CPU(cs);
539 CPUX86State *env = &cpu->env;
540 int r;
541
542 if (!env->tsc_khz) {
543 return 0;
544 }
545
546 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
547 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
548 -ENOTSUP;
549 if (r < 0) {
550 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
551 * TSC frequency doesn't match the one we want.
552 */
553 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
554 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
555 -ENOTSUP;
556 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
557 error_report("warning: TSC frequency mismatch between "
558 "VM and host, and TSC scaling unavailable");
559 return r;
560 }
561 }
562
563 return 0;
564 }
565
566 static Error *invtsc_mig_blocker;
567
568 #define KVM_MAX_CPUID_ENTRIES 100
569
570 int kvm_arch_init_vcpu(CPUState *cs)
571 {
572 struct {
573 struct kvm_cpuid2 cpuid;
574 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
575 } QEMU_PACKED cpuid_data;
576 X86CPU *cpu = X86_CPU(cs);
577 CPUX86State *env = &cpu->env;
578 uint32_t limit, i, j, cpuid_i;
579 uint32_t unused;
580 struct kvm_cpuid_entry2 *c;
581 uint32_t signature[3];
582 int kvm_base = KVM_CPUID_SIGNATURE;
583 int r;
584
585 memset(&cpuid_data, 0, sizeof(cpuid_data));
586
587 cpuid_i = 0;
588
589 /* Paravirtualization CPUIDs */
590 if (hyperv_enabled(cpu)) {
591 c = &cpuid_data.entries[cpuid_i++];
592 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
593 if (!cpu->hyperv_vendor_id) {
594 memcpy(signature, "Microsoft Hv", 12);
595 } else {
596 size_t len = strlen(cpu->hyperv_vendor_id);
597
598 if (len > 12) {
599 error_report("hv-vendor-id truncated to 12 characters");
600 len = 12;
601 }
602 memset(signature, 0, 12);
603 memcpy(signature, cpu->hyperv_vendor_id, len);
604 }
605 c->eax = HYPERV_CPUID_MIN;
606 c->ebx = signature[0];
607 c->ecx = signature[1];
608 c->edx = signature[2];
609
610 c = &cpuid_data.entries[cpuid_i++];
611 c->function = HYPERV_CPUID_INTERFACE;
612 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
613 c->eax = signature[0];
614 c->ebx = 0;
615 c->ecx = 0;
616 c->edx = 0;
617
618 c = &cpuid_data.entries[cpuid_i++];
619 c->function = HYPERV_CPUID_VERSION;
620 c->eax = 0x00001bbc;
621 c->ebx = 0x00060001;
622
623 c = &cpuid_data.entries[cpuid_i++];
624 c->function = HYPERV_CPUID_FEATURES;
625 if (cpu->hyperv_relaxed_timing) {
626 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
627 }
628 if (cpu->hyperv_vapic) {
629 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
630 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
631 has_msr_hv_vapic = true;
632 }
633 if (cpu->hyperv_time &&
634 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
635 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
636 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
637 c->eax |= 0x200;
638 has_msr_hv_tsc = true;
639 }
640 if (cpu->hyperv_crash && has_msr_hv_crash) {
641 c->edx |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
642 }
643 c->edx |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
644 if (cpu->hyperv_reset && has_msr_hv_reset) {
645 c->eax |= HV_X64_MSR_RESET_AVAILABLE;
646 }
647 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
648 c->eax |= HV_X64_MSR_VP_INDEX_AVAILABLE;
649 }
650 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
651 c->eax |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
652 }
653 if (cpu->hyperv_synic) {
654 int sint;
655
656 if (!has_msr_hv_synic ||
657 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
658 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
659 return -ENOSYS;
660 }
661
662 c->eax |= HV_X64_MSR_SYNIC_AVAILABLE;
663 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
664 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
665 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
666 }
667 }
668 if (cpu->hyperv_stimer) {
669 if (!has_msr_hv_stimer) {
670 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
671 return -ENOSYS;
672 }
673 c->eax |= HV_X64_MSR_SYNTIMER_AVAILABLE;
674 }
675 c = &cpuid_data.entries[cpuid_i++];
676 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
677 if (cpu->hyperv_relaxed_timing) {
678 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
679 }
680 if (has_msr_hv_vapic) {
681 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
682 }
683 c->ebx = cpu->hyperv_spinlock_attempts;
684
685 c = &cpuid_data.entries[cpuid_i++];
686 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
687 c->eax = 0x40;
688 c->ebx = 0x40;
689
690 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
691 has_msr_hv_hypercall = true;
692 }
693
694 if (cpu->expose_kvm) {
695 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
696 c = &cpuid_data.entries[cpuid_i++];
697 c->function = KVM_CPUID_SIGNATURE | kvm_base;
698 c->eax = KVM_CPUID_FEATURES | kvm_base;
699 c->ebx = signature[0];
700 c->ecx = signature[1];
701 c->edx = signature[2];
702
703 c = &cpuid_data.entries[cpuid_i++];
704 c->function = KVM_CPUID_FEATURES | kvm_base;
705 c->eax = env->features[FEAT_KVM];
706
707 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
708
709 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
710
711 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
712 }
713
714 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
715
716 for (i = 0; i <= limit; i++) {
717 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
718 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
719 abort();
720 }
721 c = &cpuid_data.entries[cpuid_i++];
722
723 switch (i) {
724 case 2: {
725 /* Keep reading function 2 till all the input is received */
726 int times;
727
728 c->function = i;
729 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
730 KVM_CPUID_FLAG_STATE_READ_NEXT;
731 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
732 times = c->eax & 0xff;
733
734 for (j = 1; j < times; ++j) {
735 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
736 fprintf(stderr, "cpuid_data is full, no space for "
737 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
738 abort();
739 }
740 c = &cpuid_data.entries[cpuid_i++];
741 c->function = i;
742 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
743 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
744 }
745 break;
746 }
747 case 4:
748 case 0xb:
749 case 0xd:
750 for (j = 0; ; j++) {
751 if (i == 0xd && j == 64) {
752 break;
753 }
754 c->function = i;
755 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
756 c->index = j;
757 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
758
759 if (i == 4 && c->eax == 0) {
760 break;
761 }
762 if (i == 0xb && !(c->ecx & 0xff00)) {
763 break;
764 }
765 if (i == 0xd && c->eax == 0) {
766 continue;
767 }
768 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
769 fprintf(stderr, "cpuid_data is full, no space for "
770 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
771 abort();
772 }
773 c = &cpuid_data.entries[cpuid_i++];
774 }
775 break;
776 default:
777 c->function = i;
778 c->flags = 0;
779 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
780 break;
781 }
782 }
783
784 if (limit >= 0x0a) {
785 uint32_t ver;
786
787 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
788 if ((ver & 0xff) > 0) {
789 has_msr_architectural_pmu = true;
790 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
791
792 /* Shouldn't be more than 32, since that's the number of bits
793 * available in EBX to tell us _which_ counters are available.
794 * Play it safe.
795 */
796 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
797 num_architectural_pmu_counters = MAX_GP_COUNTERS;
798 }
799 }
800 }
801
802 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
803
804 for (i = 0x80000000; i <= limit; i++) {
805 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
806 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
807 abort();
808 }
809 c = &cpuid_data.entries[cpuid_i++];
810
811 c->function = i;
812 c->flags = 0;
813 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
814 }
815
816 /* Call Centaur's CPUID instructions they are supported. */
817 if (env->cpuid_xlevel2 > 0) {
818 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
819
820 for (i = 0xC0000000; i <= limit; i++) {
821 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
822 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
823 abort();
824 }
825 c = &cpuid_data.entries[cpuid_i++];
826
827 c->function = i;
828 c->flags = 0;
829 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
830 }
831 }
832
833 cpuid_data.cpuid.nent = cpuid_i;
834
835 if (((env->cpuid_version >> 8)&0xF) >= 6
836 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
837 (CPUID_MCE | CPUID_MCA)
838 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
839 uint64_t mcg_cap, unsupported_caps;
840 int banks;
841 int ret;
842
843 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
844 if (ret < 0) {
845 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
846 return ret;
847 }
848
849 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
850 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
851 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
852 return -ENOTSUP;
853 }
854
855 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
856 if (unsupported_caps) {
857 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
858 unsupported_caps);
859 }
860
861 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
862 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
863 if (ret < 0) {
864 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
865 return ret;
866 }
867 }
868
869 qemu_add_vm_change_state_handler(cpu_update_state, env);
870
871 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
872 if (c) {
873 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
874 !!(c->ecx & CPUID_EXT_SMX);
875 }
876
877 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
878 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
879 /* for migration */
880 error_setg(&invtsc_mig_blocker,
881 "State blocked by non-migratable CPU device"
882 " (invtsc flag)");
883 migrate_add_blocker(invtsc_mig_blocker);
884 /* for savevm */
885 vmstate_x86_cpu.unmigratable = 1;
886 }
887
888 cpuid_data.cpuid.padding = 0;
889 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
890 if (r) {
891 return r;
892 }
893
894 r = kvm_arch_set_tsc_khz(cs);
895 if (r < 0) {
896 return r;
897 }
898
899 /* vcpu's TSC frequency is either specified by user, or following
900 * the value used by KVM if the former is not present. In the
901 * latter case, we query it from KVM and record in env->tsc_khz,
902 * so that vcpu's TSC frequency can be migrated later via this field.
903 */
904 if (!env->tsc_khz) {
905 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
906 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
907 -ENOTSUP;
908 if (r > 0) {
909 env->tsc_khz = r;
910 }
911 }
912
913 if (has_xsave) {
914 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
915 }
916
917 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
918 has_msr_mtrr = true;
919 }
920
921 return 0;
922 }
923
924 void kvm_arch_reset_vcpu(X86CPU *cpu)
925 {
926 CPUX86State *env = &cpu->env;
927
928 env->exception_injected = -1;
929 env->interrupt_injected = -1;
930 env->xcr0 = 1;
931 if (kvm_irqchip_in_kernel()) {
932 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
933 KVM_MP_STATE_UNINITIALIZED;
934 } else {
935 env->mp_state = KVM_MP_STATE_RUNNABLE;
936 }
937 }
938
939 void kvm_arch_do_init_vcpu(X86CPU *cpu)
940 {
941 CPUX86State *env = &cpu->env;
942
943 /* APs get directly into wait-for-SIPI state. */
944 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
945 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
946 }
947 }
948
949 static int kvm_get_supported_msrs(KVMState *s)
950 {
951 static int kvm_supported_msrs;
952 int ret = 0;
953
954 /* first time */
955 if (kvm_supported_msrs == 0) {
956 struct kvm_msr_list msr_list, *kvm_msr_list;
957
958 kvm_supported_msrs = -1;
959
960 /* Obtain MSR list from KVM. These are the MSRs that we must
961 * save/restore */
962 msr_list.nmsrs = 0;
963 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
964 if (ret < 0 && ret != -E2BIG) {
965 return ret;
966 }
967 /* Old kernel modules had a bug and could write beyond the provided
968 memory. Allocate at least a safe amount of 1K. */
969 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
970 msr_list.nmsrs *
971 sizeof(msr_list.indices[0])));
972
973 kvm_msr_list->nmsrs = msr_list.nmsrs;
974 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
975 if (ret >= 0) {
976 int i;
977
978 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
979 if (kvm_msr_list->indices[i] == MSR_STAR) {
980 has_msr_star = true;
981 continue;
982 }
983 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
984 has_msr_hsave_pa = true;
985 continue;
986 }
987 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
988 has_msr_tsc_aux = true;
989 continue;
990 }
991 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
992 has_msr_tsc_adjust = true;
993 continue;
994 }
995 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
996 has_msr_tsc_deadline = true;
997 continue;
998 }
999 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1000 has_msr_smbase = true;
1001 continue;
1002 }
1003 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1004 has_msr_misc_enable = true;
1005 continue;
1006 }
1007 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1008 has_msr_bndcfgs = true;
1009 continue;
1010 }
1011 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1012 has_msr_xss = true;
1013 continue;
1014 }
1015 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1016 has_msr_hv_crash = true;
1017 continue;
1018 }
1019 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1020 has_msr_hv_reset = true;
1021 continue;
1022 }
1023 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1024 has_msr_hv_vpindex = true;
1025 continue;
1026 }
1027 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1028 has_msr_hv_runtime = true;
1029 continue;
1030 }
1031 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1032 has_msr_hv_synic = true;
1033 continue;
1034 }
1035 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1036 has_msr_hv_stimer = true;
1037 continue;
1038 }
1039 }
1040 }
1041
1042 g_free(kvm_msr_list);
1043 }
1044
1045 return ret;
1046 }
1047
1048 static Notifier smram_machine_done;
1049 static KVMMemoryListener smram_listener;
1050 static AddressSpace smram_address_space;
1051 static MemoryRegion smram_as_root;
1052 static MemoryRegion smram_as_mem;
1053
1054 static void register_smram_listener(Notifier *n, void *unused)
1055 {
1056 MemoryRegion *smram =
1057 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1058
1059 /* Outer container... */
1060 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1061 memory_region_set_enabled(&smram_as_root, true);
1062
1063 /* ... with two regions inside: normal system memory with low
1064 * priority, and...
1065 */
1066 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1067 get_system_memory(), 0, ~0ull);
1068 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1069 memory_region_set_enabled(&smram_as_mem, true);
1070
1071 if (smram) {
1072 /* ... SMRAM with higher priority */
1073 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1074 memory_region_set_enabled(smram, true);
1075 }
1076
1077 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1078 kvm_memory_listener_register(kvm_state, &smram_listener,
1079 &smram_address_space, 1);
1080 }
1081
1082 int kvm_arch_init(MachineState *ms, KVMState *s)
1083 {
1084 uint64_t identity_base = 0xfffbc000;
1085 uint64_t shadow_mem;
1086 int ret;
1087 struct utsname utsname;
1088
1089 #ifdef KVM_CAP_XSAVE
1090 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1091 #endif
1092
1093 #ifdef KVM_CAP_XCRS
1094 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1095 #endif
1096
1097 #ifdef KVM_CAP_PIT_STATE2
1098 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1099 #endif
1100
1101 ret = kvm_get_supported_msrs(s);
1102 if (ret < 0) {
1103 return ret;
1104 }
1105
1106 uname(&utsname);
1107 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1108
1109 /*
1110 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1111 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1112 * Since these must be part of guest physical memory, we need to allocate
1113 * them, both by setting their start addresses in the kernel and by
1114 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1115 *
1116 * Older KVM versions may not support setting the identity map base. In
1117 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1118 * size.
1119 */
1120 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1121 /* Allows up to 16M BIOSes. */
1122 identity_base = 0xfeffc000;
1123
1124 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1125 if (ret < 0) {
1126 return ret;
1127 }
1128 }
1129
1130 /* Set TSS base one page after EPT identity map. */
1131 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1132 if (ret < 0) {
1133 return ret;
1134 }
1135
1136 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1137 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1138 if (ret < 0) {
1139 fprintf(stderr, "e820_add_entry() table is full\n");
1140 return ret;
1141 }
1142 qemu_register_reset(kvm_unpoison_all, NULL);
1143
1144 shadow_mem = machine_kvm_shadow_mem(ms);
1145 if (shadow_mem != -1) {
1146 shadow_mem /= 4096;
1147 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1148 if (ret < 0) {
1149 return ret;
1150 }
1151 }
1152
1153 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1154 smram_machine_done.notify = register_smram_listener;
1155 qemu_add_machine_init_done_notifier(&smram_machine_done);
1156 }
1157 return 0;
1158 }
1159
1160 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1161 {
1162 lhs->selector = rhs->selector;
1163 lhs->base = rhs->base;
1164 lhs->limit = rhs->limit;
1165 lhs->type = 3;
1166 lhs->present = 1;
1167 lhs->dpl = 3;
1168 lhs->db = 0;
1169 lhs->s = 1;
1170 lhs->l = 0;
1171 lhs->g = 0;
1172 lhs->avl = 0;
1173 lhs->unusable = 0;
1174 }
1175
1176 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1177 {
1178 unsigned flags = rhs->flags;
1179 lhs->selector = rhs->selector;
1180 lhs->base = rhs->base;
1181 lhs->limit = rhs->limit;
1182 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1183 lhs->present = (flags & DESC_P_MASK) != 0;
1184 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1185 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1186 lhs->s = (flags & DESC_S_MASK) != 0;
1187 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1188 lhs->g = (flags & DESC_G_MASK) != 0;
1189 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1190 lhs->unusable = !lhs->present;
1191 lhs->padding = 0;
1192 }
1193
1194 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1195 {
1196 lhs->selector = rhs->selector;
1197 lhs->base = rhs->base;
1198 lhs->limit = rhs->limit;
1199 if (rhs->unusable) {
1200 lhs->flags = 0;
1201 } else {
1202 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1203 (rhs->present * DESC_P_MASK) |
1204 (rhs->dpl << DESC_DPL_SHIFT) |
1205 (rhs->db << DESC_B_SHIFT) |
1206 (rhs->s * DESC_S_MASK) |
1207 (rhs->l << DESC_L_SHIFT) |
1208 (rhs->g * DESC_G_MASK) |
1209 (rhs->avl * DESC_AVL_MASK);
1210 }
1211 }
1212
1213 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1214 {
1215 if (set) {
1216 *kvm_reg = *qemu_reg;
1217 } else {
1218 *qemu_reg = *kvm_reg;
1219 }
1220 }
1221
1222 static int kvm_getput_regs(X86CPU *cpu, int set)
1223 {
1224 CPUX86State *env = &cpu->env;
1225 struct kvm_regs regs;
1226 int ret = 0;
1227
1228 if (!set) {
1229 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1230 if (ret < 0) {
1231 return ret;
1232 }
1233 }
1234
1235 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1236 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1237 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1238 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1239 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1240 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1241 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1242 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1243 #ifdef TARGET_X86_64
1244 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1245 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1246 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1247 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1248 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1249 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1250 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1251 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1252 #endif
1253
1254 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1255 kvm_getput_reg(&regs.rip, &env->eip, set);
1256
1257 if (set) {
1258 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1259 }
1260
1261 return ret;
1262 }
1263
1264 static int kvm_put_fpu(X86CPU *cpu)
1265 {
1266 CPUX86State *env = &cpu->env;
1267 struct kvm_fpu fpu;
1268 int i;
1269
1270 memset(&fpu, 0, sizeof fpu);
1271 fpu.fsw = env->fpus & ~(7 << 11);
1272 fpu.fsw |= (env->fpstt & 7) << 11;
1273 fpu.fcw = env->fpuc;
1274 fpu.last_opcode = env->fpop;
1275 fpu.last_ip = env->fpip;
1276 fpu.last_dp = env->fpdp;
1277 for (i = 0; i < 8; ++i) {
1278 fpu.ftwx |= (!env->fptags[i]) << i;
1279 }
1280 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1281 for (i = 0; i < CPU_NB_REGS; i++) {
1282 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1283 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1284 }
1285 fpu.mxcsr = env->mxcsr;
1286
1287 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1288 }
1289
1290 #define XSAVE_FCW_FSW 0
1291 #define XSAVE_FTW_FOP 1
1292 #define XSAVE_CWD_RIP 2
1293 #define XSAVE_CWD_RDP 4
1294 #define XSAVE_MXCSR 6
1295 #define XSAVE_ST_SPACE 8
1296 #define XSAVE_XMM_SPACE 40
1297 #define XSAVE_XSTATE_BV 128
1298 #define XSAVE_YMMH_SPACE 144
1299 #define XSAVE_BNDREGS 240
1300 #define XSAVE_BNDCSR 256
1301 #define XSAVE_OPMASK 272
1302 #define XSAVE_ZMM_Hi256 288
1303 #define XSAVE_Hi16_ZMM 416
1304 #define XSAVE_PKRU 672
1305
1306 static int kvm_put_xsave(X86CPU *cpu)
1307 {
1308 CPUX86State *env = &cpu->env;
1309 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1310 uint16_t cwd, swd, twd;
1311 uint8_t *xmm, *ymmh, *zmmh;
1312 int i, r;
1313
1314 if (!has_xsave) {
1315 return kvm_put_fpu(cpu);
1316 }
1317
1318 memset(xsave, 0, sizeof(struct kvm_xsave));
1319 twd = 0;
1320 swd = env->fpus & ~(7 << 11);
1321 swd |= (env->fpstt & 7) << 11;
1322 cwd = env->fpuc;
1323 for (i = 0; i < 8; ++i) {
1324 twd |= (!env->fptags[i]) << i;
1325 }
1326 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
1327 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
1328 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1329 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
1330 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1331 sizeof env->fpregs);
1332 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1333 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
1334 memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
1335 sizeof env->bnd_regs);
1336 memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
1337 sizeof(env->bndcs_regs));
1338 memcpy(&xsave->region[XSAVE_OPMASK], env->opmask_regs,
1339 sizeof env->opmask_regs);
1340
1341 xmm = (uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
1342 ymmh = (uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1343 zmmh = (uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1344 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
1345 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1346 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1347 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1348 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1349 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1350 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1351 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1352 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
1353 }
1354
1355 #ifdef TARGET_X86_64
1356 memcpy(&xsave->region[XSAVE_Hi16_ZMM], &env->xmm_regs[16],
1357 16 * sizeof env->xmm_regs[16]);
1358 memcpy(&xsave->region[XSAVE_PKRU], &env->pkru, sizeof env->pkru);
1359 #endif
1360 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1361 return r;
1362 }
1363
1364 static int kvm_put_xcrs(X86CPU *cpu)
1365 {
1366 CPUX86State *env = &cpu->env;
1367 struct kvm_xcrs xcrs = {};
1368
1369 if (!has_xcrs) {
1370 return 0;
1371 }
1372
1373 xcrs.nr_xcrs = 1;
1374 xcrs.flags = 0;
1375 xcrs.xcrs[0].xcr = 0;
1376 xcrs.xcrs[0].value = env->xcr0;
1377 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1378 }
1379
1380 static int kvm_put_sregs(X86CPU *cpu)
1381 {
1382 CPUX86State *env = &cpu->env;
1383 struct kvm_sregs sregs;
1384
1385 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1386 if (env->interrupt_injected >= 0) {
1387 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1388 (uint64_t)1 << (env->interrupt_injected % 64);
1389 }
1390
1391 if ((env->eflags & VM_MASK)) {
1392 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1393 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1394 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1395 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1396 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1397 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1398 } else {
1399 set_seg(&sregs.cs, &env->segs[R_CS]);
1400 set_seg(&sregs.ds, &env->segs[R_DS]);
1401 set_seg(&sregs.es, &env->segs[R_ES]);
1402 set_seg(&sregs.fs, &env->segs[R_FS]);
1403 set_seg(&sregs.gs, &env->segs[R_GS]);
1404 set_seg(&sregs.ss, &env->segs[R_SS]);
1405 }
1406
1407 set_seg(&sregs.tr, &env->tr);
1408 set_seg(&sregs.ldt, &env->ldt);
1409
1410 sregs.idt.limit = env->idt.limit;
1411 sregs.idt.base = env->idt.base;
1412 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1413 sregs.gdt.limit = env->gdt.limit;
1414 sregs.gdt.base = env->gdt.base;
1415 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1416
1417 sregs.cr0 = env->cr[0];
1418 sregs.cr2 = env->cr[2];
1419 sregs.cr3 = env->cr[3];
1420 sregs.cr4 = env->cr[4];
1421
1422 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1423 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1424
1425 sregs.efer = env->efer;
1426
1427 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1428 }
1429
1430 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1431 uint32_t index, uint64_t value)
1432 {
1433 entry->index = index;
1434 entry->reserved = 0;
1435 entry->data = value;
1436 }
1437
1438 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1439 {
1440 CPUX86State *env = &cpu->env;
1441 struct {
1442 struct kvm_msrs info;
1443 struct kvm_msr_entry entries[1];
1444 } msr_data;
1445 struct kvm_msr_entry *msrs = msr_data.entries;
1446
1447 if (!has_msr_tsc_deadline) {
1448 return 0;
1449 }
1450
1451 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1452
1453 msr_data.info = (struct kvm_msrs) {
1454 .nmsrs = 1,
1455 };
1456
1457 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1458 }
1459
1460 /*
1461 * Provide a separate write service for the feature control MSR in order to
1462 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1463 * before writing any other state because forcibly leaving nested mode
1464 * invalidates the VCPU state.
1465 */
1466 static int kvm_put_msr_feature_control(X86CPU *cpu)
1467 {
1468 struct {
1469 struct kvm_msrs info;
1470 struct kvm_msr_entry entry;
1471 } msr_data;
1472
1473 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1474 cpu->env.msr_ia32_feature_control);
1475
1476 msr_data.info = (struct kvm_msrs) {
1477 .nmsrs = 1,
1478 };
1479
1480 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1481 }
1482
1483 static int kvm_put_msrs(X86CPU *cpu, int level)
1484 {
1485 CPUX86State *env = &cpu->env;
1486 struct {
1487 struct kvm_msrs info;
1488 struct kvm_msr_entry entries[150];
1489 } msr_data;
1490 struct kvm_msr_entry *msrs = msr_data.entries;
1491 int n = 0, i;
1492
1493 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1494 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1495 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1496 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1497 if (has_msr_star) {
1498 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1499 }
1500 if (has_msr_hsave_pa) {
1501 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1502 }
1503 if (has_msr_tsc_aux) {
1504 kvm_msr_entry_set(&msrs[n++], MSR_TSC_AUX, env->tsc_aux);
1505 }
1506 if (has_msr_tsc_adjust) {
1507 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1508 }
1509 if (has_msr_misc_enable) {
1510 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1511 env->msr_ia32_misc_enable);
1512 }
1513 if (has_msr_smbase) {
1514 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SMBASE, env->smbase);
1515 }
1516 if (has_msr_bndcfgs) {
1517 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1518 }
1519 if (has_msr_xss) {
1520 kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
1521 }
1522 #ifdef TARGET_X86_64
1523 if (lm_capable_kernel) {
1524 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1525 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1526 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1527 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1528 }
1529 #endif
1530 /*
1531 * The following MSRs have side effects on the guest or are too heavy
1532 * for normal writeback. Limit them to reset or full state updates.
1533 */
1534 if (level >= KVM_PUT_RESET_STATE) {
1535 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1536 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1537 env->system_time_msr);
1538 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1539 if (has_msr_async_pf_en) {
1540 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1541 env->async_pf_en_msr);
1542 }
1543 if (has_msr_pv_eoi_en) {
1544 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1545 env->pv_eoi_en_msr);
1546 }
1547 if (has_msr_kvm_steal_time) {
1548 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1549 env->steal_time_msr);
1550 }
1551 if (has_msr_architectural_pmu) {
1552 /* Stop the counter. */
1553 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1554 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1555
1556 /* Set the counter values. */
1557 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1558 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1559 env->msr_fixed_counters[i]);
1560 }
1561 for (i = 0; i < num_architectural_pmu_counters; i++) {
1562 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1563 env->msr_gp_counters[i]);
1564 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1565 env->msr_gp_evtsel[i]);
1566 }
1567 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1568 env->msr_global_status);
1569 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1570 env->msr_global_ovf_ctrl);
1571
1572 /* Now start the PMU. */
1573 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1574 env->msr_fixed_ctr_ctrl);
1575 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1576 env->msr_global_ctrl);
1577 }
1578 if (has_msr_hv_hypercall) {
1579 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1580 env->msr_hv_guest_os_id);
1581 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1582 env->msr_hv_hypercall);
1583 }
1584 if (has_msr_hv_vapic) {
1585 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1586 env->msr_hv_vapic);
1587 }
1588 if (has_msr_hv_tsc) {
1589 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
1590 env->msr_hv_tsc);
1591 }
1592 if (has_msr_hv_crash) {
1593 int j;
1594
1595 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1596 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_P0 + j,
1597 env->msr_hv_crash_params[j]);
1598
1599 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_CTL,
1600 HV_X64_MSR_CRASH_CTL_NOTIFY);
1601 }
1602 if (has_msr_hv_runtime) {
1603 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_VP_RUNTIME,
1604 env->msr_hv_runtime);
1605 }
1606 if (cpu->hyperv_synic) {
1607 int j;
1608
1609 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SCONTROL,
1610 env->msr_hv_synic_control);
1611 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SVERSION,
1612 env->msr_hv_synic_version);
1613 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SIEFP,
1614 env->msr_hv_synic_evt_page);
1615 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SIMP,
1616 env->msr_hv_synic_msg_page);
1617
1618 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1619 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SINT0 + j,
1620 env->msr_hv_synic_sint[j]);
1621 }
1622 }
1623 if (has_msr_hv_stimer) {
1624 int j;
1625
1626 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1627 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_STIMER0_CONFIG + j*2,
1628 env->msr_hv_stimer_config[j]);
1629 }
1630
1631 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1632 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_STIMER0_COUNT + j*2,
1633 env->msr_hv_stimer_count[j]);
1634 }
1635 }
1636 if (has_msr_mtrr) {
1637 kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype);
1638 kvm_msr_entry_set(&msrs[n++],
1639 MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1640 kvm_msr_entry_set(&msrs[n++],
1641 MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1642 kvm_msr_entry_set(&msrs[n++],
1643 MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1644 kvm_msr_entry_set(&msrs[n++],
1645 MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1646 kvm_msr_entry_set(&msrs[n++],
1647 MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1648 kvm_msr_entry_set(&msrs[n++],
1649 MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1650 kvm_msr_entry_set(&msrs[n++],
1651 MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1652 kvm_msr_entry_set(&msrs[n++],
1653 MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1654 kvm_msr_entry_set(&msrs[n++],
1655 MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1656 kvm_msr_entry_set(&msrs[n++],
1657 MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1658 kvm_msr_entry_set(&msrs[n++],
1659 MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1660 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1661 kvm_msr_entry_set(&msrs[n++],
1662 MSR_MTRRphysBase(i), env->mtrr_var[i].base);
1663 kvm_msr_entry_set(&msrs[n++],
1664 MSR_MTRRphysMask(i), env->mtrr_var[i].mask);
1665 }
1666 }
1667
1668 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1669 * kvm_put_msr_feature_control. */
1670 }
1671 if (env->mcg_cap) {
1672 int i;
1673
1674 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1675 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1676 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1677 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1678 }
1679 }
1680
1681 msr_data.info = (struct kvm_msrs) {
1682 .nmsrs = n,
1683 };
1684
1685 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1686
1687 }
1688
1689
1690 static int kvm_get_fpu(X86CPU *cpu)
1691 {
1692 CPUX86State *env = &cpu->env;
1693 struct kvm_fpu fpu;
1694 int i, ret;
1695
1696 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1697 if (ret < 0) {
1698 return ret;
1699 }
1700
1701 env->fpstt = (fpu.fsw >> 11) & 7;
1702 env->fpus = fpu.fsw;
1703 env->fpuc = fpu.fcw;
1704 env->fpop = fpu.last_opcode;
1705 env->fpip = fpu.last_ip;
1706 env->fpdp = fpu.last_dp;
1707 for (i = 0; i < 8; ++i) {
1708 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1709 }
1710 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1711 for (i = 0; i < CPU_NB_REGS; i++) {
1712 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1713 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1714 }
1715 env->mxcsr = fpu.mxcsr;
1716
1717 return 0;
1718 }
1719
1720 static int kvm_get_xsave(X86CPU *cpu)
1721 {
1722 CPUX86State *env = &cpu->env;
1723 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1724 int ret, i;
1725 const uint8_t *xmm, *ymmh, *zmmh;
1726 uint16_t cwd, swd, twd;
1727
1728 if (!has_xsave) {
1729 return kvm_get_fpu(cpu);
1730 }
1731
1732 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1733 if (ret < 0) {
1734 return ret;
1735 }
1736
1737 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1738 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1739 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1740 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1741 env->fpstt = (swd >> 11) & 7;
1742 env->fpus = swd;
1743 env->fpuc = cwd;
1744 for (i = 0; i < 8; ++i) {
1745 env->fptags[i] = !((twd >> i) & 1);
1746 }
1747 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1748 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1749 env->mxcsr = xsave->region[XSAVE_MXCSR];
1750 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1751 sizeof env->fpregs);
1752 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1753 memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
1754 sizeof env->bnd_regs);
1755 memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
1756 sizeof(env->bndcs_regs));
1757 memcpy(env->opmask_regs, &xsave->region[XSAVE_OPMASK],
1758 sizeof env->opmask_regs);
1759
1760 xmm = (const uint8_t *)&xsave->region[XSAVE_XMM_SPACE];
1761 ymmh = (const uint8_t *)&xsave->region[XSAVE_YMMH_SPACE];
1762 zmmh = (const uint8_t *)&xsave->region[XSAVE_ZMM_Hi256];
1763 for (i = 0; i < CPU_NB_REGS; i++, xmm += 16, ymmh += 16, zmmh += 32) {
1764 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1765 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1766 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1767 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1768 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1769 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1770 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1771 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
1772 }
1773
1774 #ifdef TARGET_X86_64
1775 memcpy(&env->xmm_regs[16], &xsave->region[XSAVE_Hi16_ZMM],
1776 16 * sizeof env->xmm_regs[16]);
1777 memcpy(&env->pkru, &xsave->region[XSAVE_PKRU], sizeof env->pkru);
1778 #endif
1779 return 0;
1780 }
1781
1782 static int kvm_get_xcrs(X86CPU *cpu)
1783 {
1784 CPUX86State *env = &cpu->env;
1785 int i, ret;
1786 struct kvm_xcrs xcrs;
1787
1788 if (!has_xcrs) {
1789 return 0;
1790 }
1791
1792 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1793 if (ret < 0) {
1794 return ret;
1795 }
1796
1797 for (i = 0; i < xcrs.nr_xcrs; i++) {
1798 /* Only support xcr0 now */
1799 if (xcrs.xcrs[i].xcr == 0) {
1800 env->xcr0 = xcrs.xcrs[i].value;
1801 break;
1802 }
1803 }
1804 return 0;
1805 }
1806
1807 static int kvm_get_sregs(X86CPU *cpu)
1808 {
1809 CPUX86State *env = &cpu->env;
1810 struct kvm_sregs sregs;
1811 uint32_t hflags;
1812 int bit, i, ret;
1813
1814 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1815 if (ret < 0) {
1816 return ret;
1817 }
1818
1819 /* There can only be one pending IRQ set in the bitmap at a time, so try
1820 to find it and save its number instead (-1 for none). */
1821 env->interrupt_injected = -1;
1822 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1823 if (sregs.interrupt_bitmap[i]) {
1824 bit = ctz64(sregs.interrupt_bitmap[i]);
1825 env->interrupt_injected = i * 64 + bit;
1826 break;
1827 }
1828 }
1829
1830 get_seg(&env->segs[R_CS], &sregs.cs);
1831 get_seg(&env->segs[R_DS], &sregs.ds);
1832 get_seg(&env->segs[R_ES], &sregs.es);
1833 get_seg(&env->segs[R_FS], &sregs.fs);
1834 get_seg(&env->segs[R_GS], &sregs.gs);
1835 get_seg(&env->segs[R_SS], &sregs.ss);
1836
1837 get_seg(&env->tr, &sregs.tr);
1838 get_seg(&env->ldt, &sregs.ldt);
1839
1840 env->idt.limit = sregs.idt.limit;
1841 env->idt.base = sregs.idt.base;
1842 env->gdt.limit = sregs.gdt.limit;
1843 env->gdt.base = sregs.gdt.base;
1844
1845 env->cr[0] = sregs.cr0;
1846 env->cr[2] = sregs.cr2;
1847 env->cr[3] = sregs.cr3;
1848 env->cr[4] = sregs.cr4;
1849
1850 env->efer = sregs.efer;
1851
1852 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1853
1854 #define HFLAG_COPY_MASK \
1855 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1856 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1857 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1858 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1859
1860 hflags = env->hflags & HFLAG_COPY_MASK;
1861 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1862 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1863 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1864 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1865 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1866
1867 if (env->cr[4] & CR4_OSFXSR_MASK) {
1868 hflags |= HF_OSFXSR_MASK;
1869 }
1870
1871 if (env->efer & MSR_EFER_LMA) {
1872 hflags |= HF_LMA_MASK;
1873 }
1874
1875 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1876 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1877 } else {
1878 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1879 (DESC_B_SHIFT - HF_CS32_SHIFT);
1880 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1881 (DESC_B_SHIFT - HF_SS32_SHIFT);
1882 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1883 !(hflags & HF_CS32_MASK)) {
1884 hflags |= HF_ADDSEG_MASK;
1885 } else {
1886 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1887 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1888 }
1889 }
1890 env->hflags = hflags;
1891
1892 return 0;
1893 }
1894
1895 static int kvm_get_msrs(X86CPU *cpu)
1896 {
1897 CPUX86State *env = &cpu->env;
1898 struct {
1899 struct kvm_msrs info;
1900 struct kvm_msr_entry entries[150];
1901 } msr_data;
1902 struct kvm_msr_entry *msrs = msr_data.entries;
1903 int ret, i, n;
1904
1905 n = 0;
1906 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1907 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1908 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1909 msrs[n++].index = MSR_PAT;
1910 if (has_msr_star) {
1911 msrs[n++].index = MSR_STAR;
1912 }
1913 if (has_msr_hsave_pa) {
1914 msrs[n++].index = MSR_VM_HSAVE_PA;
1915 }
1916 if (has_msr_tsc_aux) {
1917 msrs[n++].index = MSR_TSC_AUX;
1918 }
1919 if (has_msr_tsc_adjust) {
1920 msrs[n++].index = MSR_TSC_ADJUST;
1921 }
1922 if (has_msr_tsc_deadline) {
1923 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1924 }
1925 if (has_msr_misc_enable) {
1926 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1927 }
1928 if (has_msr_smbase) {
1929 msrs[n++].index = MSR_IA32_SMBASE;
1930 }
1931 if (has_msr_feature_control) {
1932 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1933 }
1934 if (has_msr_bndcfgs) {
1935 msrs[n++].index = MSR_IA32_BNDCFGS;
1936 }
1937 if (has_msr_xss) {
1938 msrs[n++].index = MSR_IA32_XSS;
1939 }
1940
1941
1942 if (!env->tsc_valid) {
1943 msrs[n++].index = MSR_IA32_TSC;
1944 env->tsc_valid = !runstate_is_running();
1945 }
1946
1947 #ifdef TARGET_X86_64
1948 if (lm_capable_kernel) {
1949 msrs[n++].index = MSR_CSTAR;
1950 msrs[n++].index = MSR_KERNELGSBASE;
1951 msrs[n++].index = MSR_FMASK;
1952 msrs[n++].index = MSR_LSTAR;
1953 }
1954 #endif
1955 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1956 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1957 if (has_msr_async_pf_en) {
1958 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1959 }
1960 if (has_msr_pv_eoi_en) {
1961 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1962 }
1963 if (has_msr_kvm_steal_time) {
1964 msrs[n++].index = MSR_KVM_STEAL_TIME;
1965 }
1966 if (has_msr_architectural_pmu) {
1967 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1968 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1969 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1970 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1971 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1972 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1973 }
1974 for (i = 0; i < num_architectural_pmu_counters; i++) {
1975 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1976 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1977 }
1978 }
1979
1980 if (env->mcg_cap) {
1981 msrs[n++].index = MSR_MCG_STATUS;
1982 msrs[n++].index = MSR_MCG_CTL;
1983 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1984 msrs[n++].index = MSR_MC0_CTL + i;
1985 }
1986 }
1987
1988 if (has_msr_hv_hypercall) {
1989 msrs[n++].index = HV_X64_MSR_HYPERCALL;
1990 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
1991 }
1992 if (has_msr_hv_vapic) {
1993 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
1994 }
1995 if (has_msr_hv_tsc) {
1996 msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
1997 }
1998 if (has_msr_hv_crash) {
1999 int j;
2000
2001 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
2002 msrs[n++].index = HV_X64_MSR_CRASH_P0 + j;
2003 }
2004 }
2005 if (has_msr_hv_runtime) {
2006 msrs[n++].index = HV_X64_MSR_VP_RUNTIME;
2007 }
2008 if (cpu->hyperv_synic) {
2009 uint32_t msr;
2010
2011 msrs[n++].index = HV_X64_MSR_SCONTROL;
2012 msrs[n++].index = HV_X64_MSR_SVERSION;
2013 msrs[n++].index = HV_X64_MSR_SIEFP;
2014 msrs[n++].index = HV_X64_MSR_SIMP;
2015 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2016 msrs[n++].index = msr;
2017 }
2018 }
2019 if (has_msr_hv_stimer) {
2020 uint32_t msr;
2021
2022 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2023 msr++) {
2024 msrs[n++].index = msr;
2025 }
2026 }
2027 if (has_msr_mtrr) {
2028 msrs[n++].index = MSR_MTRRdefType;
2029 msrs[n++].index = MSR_MTRRfix64K_00000;
2030 msrs[n++].index = MSR_MTRRfix16K_80000;
2031 msrs[n++].index = MSR_MTRRfix16K_A0000;
2032 msrs[n++].index = MSR_MTRRfix4K_C0000;
2033 msrs[n++].index = MSR_MTRRfix4K_C8000;
2034 msrs[n++].index = MSR_MTRRfix4K_D0000;
2035 msrs[n++].index = MSR_MTRRfix4K_D8000;
2036 msrs[n++].index = MSR_MTRRfix4K_E0000;
2037 msrs[n++].index = MSR_MTRRfix4K_E8000;
2038 msrs[n++].index = MSR_MTRRfix4K_F0000;
2039 msrs[n++].index = MSR_MTRRfix4K_F8000;
2040 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2041 msrs[n++].index = MSR_MTRRphysBase(i);
2042 msrs[n++].index = MSR_MTRRphysMask(i);
2043 }
2044 }
2045
2046 msr_data.info = (struct kvm_msrs) {
2047 .nmsrs = n,
2048 };
2049
2050 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
2051 if (ret < 0) {
2052 return ret;
2053 }
2054
2055 for (i = 0; i < ret; i++) {
2056 uint32_t index = msrs[i].index;
2057 switch (index) {
2058 case MSR_IA32_SYSENTER_CS:
2059 env->sysenter_cs = msrs[i].data;
2060 break;
2061 case MSR_IA32_SYSENTER_ESP:
2062 env->sysenter_esp = msrs[i].data;
2063 break;
2064 case MSR_IA32_SYSENTER_EIP:
2065 env->sysenter_eip = msrs[i].data;
2066 break;
2067 case MSR_PAT:
2068 env->pat = msrs[i].data;
2069 break;
2070 case MSR_STAR:
2071 env->star = msrs[i].data;
2072 break;
2073 #ifdef TARGET_X86_64
2074 case MSR_CSTAR:
2075 env->cstar = msrs[i].data;
2076 break;
2077 case MSR_KERNELGSBASE:
2078 env->kernelgsbase = msrs[i].data;
2079 break;
2080 case MSR_FMASK:
2081 env->fmask = msrs[i].data;
2082 break;
2083 case MSR_LSTAR:
2084 env->lstar = msrs[i].data;
2085 break;
2086 #endif
2087 case MSR_IA32_TSC:
2088 env->tsc = msrs[i].data;
2089 break;
2090 case MSR_TSC_AUX:
2091 env->tsc_aux = msrs[i].data;
2092 break;
2093 case MSR_TSC_ADJUST:
2094 env->tsc_adjust = msrs[i].data;
2095 break;
2096 case MSR_IA32_TSCDEADLINE:
2097 env->tsc_deadline = msrs[i].data;
2098 break;
2099 case MSR_VM_HSAVE_PA:
2100 env->vm_hsave = msrs[i].data;
2101 break;
2102 case MSR_KVM_SYSTEM_TIME:
2103 env->system_time_msr = msrs[i].data;
2104 break;
2105 case MSR_KVM_WALL_CLOCK:
2106 env->wall_clock_msr = msrs[i].data;
2107 break;
2108 case MSR_MCG_STATUS:
2109 env->mcg_status = msrs[i].data;
2110 break;
2111 case MSR_MCG_CTL:
2112 env->mcg_ctl = msrs[i].data;
2113 break;
2114 case MSR_IA32_MISC_ENABLE:
2115 env->msr_ia32_misc_enable = msrs[i].data;
2116 break;
2117 case MSR_IA32_SMBASE:
2118 env->smbase = msrs[i].data;
2119 break;
2120 case MSR_IA32_FEATURE_CONTROL:
2121 env->msr_ia32_feature_control = msrs[i].data;
2122 break;
2123 case MSR_IA32_BNDCFGS:
2124 env->msr_bndcfgs = msrs[i].data;
2125 break;
2126 case MSR_IA32_XSS:
2127 env->xss = msrs[i].data;
2128 break;
2129 default:
2130 if (msrs[i].index >= MSR_MC0_CTL &&
2131 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2132 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2133 }
2134 break;
2135 case MSR_KVM_ASYNC_PF_EN:
2136 env->async_pf_en_msr = msrs[i].data;
2137 break;
2138 case MSR_KVM_PV_EOI_EN:
2139 env->pv_eoi_en_msr = msrs[i].data;
2140 break;
2141 case MSR_KVM_STEAL_TIME:
2142 env->steal_time_msr = msrs[i].data;
2143 break;
2144 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2145 env->msr_fixed_ctr_ctrl = msrs[i].data;
2146 break;
2147 case MSR_CORE_PERF_GLOBAL_CTRL:
2148 env->msr_global_ctrl = msrs[i].data;
2149 break;
2150 case MSR_CORE_PERF_GLOBAL_STATUS:
2151 env->msr_global_status = msrs[i].data;
2152 break;
2153 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2154 env->msr_global_ovf_ctrl = msrs[i].data;
2155 break;
2156 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2157 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2158 break;
2159 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2160 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2161 break;
2162 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2163 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2164 break;
2165 case HV_X64_MSR_HYPERCALL:
2166 env->msr_hv_hypercall = msrs[i].data;
2167 break;
2168 case HV_X64_MSR_GUEST_OS_ID:
2169 env->msr_hv_guest_os_id = msrs[i].data;
2170 break;
2171 case HV_X64_MSR_APIC_ASSIST_PAGE:
2172 env->msr_hv_vapic = msrs[i].data;
2173 break;
2174 case HV_X64_MSR_REFERENCE_TSC:
2175 env->msr_hv_tsc = msrs[i].data;
2176 break;
2177 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2178 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2179 break;
2180 case HV_X64_MSR_VP_RUNTIME:
2181 env->msr_hv_runtime = msrs[i].data;
2182 break;
2183 case HV_X64_MSR_SCONTROL:
2184 env->msr_hv_synic_control = msrs[i].data;
2185 break;
2186 case HV_X64_MSR_SVERSION:
2187 env->msr_hv_synic_version = msrs[i].data;
2188 break;
2189 case HV_X64_MSR_SIEFP:
2190 env->msr_hv_synic_evt_page = msrs[i].data;
2191 break;
2192 case HV_X64_MSR_SIMP:
2193 env->msr_hv_synic_msg_page = msrs[i].data;
2194 break;
2195 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2196 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2197 break;
2198 case HV_X64_MSR_STIMER0_CONFIG:
2199 case HV_X64_MSR_STIMER1_CONFIG:
2200 case HV_X64_MSR_STIMER2_CONFIG:
2201 case HV_X64_MSR_STIMER3_CONFIG:
2202 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2203 msrs[i].data;
2204 break;
2205 case HV_X64_MSR_STIMER0_COUNT:
2206 case HV_X64_MSR_STIMER1_COUNT:
2207 case HV_X64_MSR_STIMER2_COUNT:
2208 case HV_X64_MSR_STIMER3_COUNT:
2209 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2210 msrs[i].data;
2211 break;
2212 case MSR_MTRRdefType:
2213 env->mtrr_deftype = msrs[i].data;
2214 break;
2215 case MSR_MTRRfix64K_00000:
2216 env->mtrr_fixed[0] = msrs[i].data;
2217 break;
2218 case MSR_MTRRfix16K_80000:
2219 env->mtrr_fixed[1] = msrs[i].data;
2220 break;
2221 case MSR_MTRRfix16K_A0000:
2222 env->mtrr_fixed[2] = msrs[i].data;
2223 break;
2224 case MSR_MTRRfix4K_C0000:
2225 env->mtrr_fixed[3] = msrs[i].data;
2226 break;
2227 case MSR_MTRRfix4K_C8000:
2228 env->mtrr_fixed[4] = msrs[i].data;
2229 break;
2230 case MSR_MTRRfix4K_D0000:
2231 env->mtrr_fixed[5] = msrs[i].data;
2232 break;
2233 case MSR_MTRRfix4K_D8000:
2234 env->mtrr_fixed[6] = msrs[i].data;
2235 break;
2236 case MSR_MTRRfix4K_E0000:
2237 env->mtrr_fixed[7] = msrs[i].data;
2238 break;
2239 case MSR_MTRRfix4K_E8000:
2240 env->mtrr_fixed[8] = msrs[i].data;
2241 break;
2242 case MSR_MTRRfix4K_F0000:
2243 env->mtrr_fixed[9] = msrs[i].data;
2244 break;
2245 case MSR_MTRRfix4K_F8000:
2246 env->mtrr_fixed[10] = msrs[i].data;
2247 break;
2248 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2249 if (index & 1) {
2250 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
2251 } else {
2252 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2253 }
2254 break;
2255 }
2256 }
2257
2258 return 0;
2259 }
2260
2261 static int kvm_put_mp_state(X86CPU *cpu)
2262 {
2263 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2264
2265 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2266 }
2267
2268 static int kvm_get_mp_state(X86CPU *cpu)
2269 {
2270 CPUState *cs = CPU(cpu);
2271 CPUX86State *env = &cpu->env;
2272 struct kvm_mp_state mp_state;
2273 int ret;
2274
2275 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2276 if (ret < 0) {
2277 return ret;
2278 }
2279 env->mp_state = mp_state.mp_state;
2280 if (kvm_irqchip_in_kernel()) {
2281 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2282 }
2283 return 0;
2284 }
2285
2286 static int kvm_get_apic(X86CPU *cpu)
2287 {
2288 DeviceState *apic = cpu->apic_state;
2289 struct kvm_lapic_state kapic;
2290 int ret;
2291
2292 if (apic && kvm_irqchip_in_kernel()) {
2293 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2294 if (ret < 0) {
2295 return ret;
2296 }
2297
2298 kvm_get_apic_state(apic, &kapic);
2299 }
2300 return 0;
2301 }
2302
2303 static int kvm_put_apic(X86CPU *cpu)
2304 {
2305 DeviceState *apic = cpu->apic_state;
2306 struct kvm_lapic_state kapic;
2307
2308 if (apic && kvm_irqchip_in_kernel()) {
2309 kvm_put_apic_state(apic, &kapic);
2310
2311 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
2312 }
2313 return 0;
2314 }
2315
2316 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2317 {
2318 CPUState *cs = CPU(cpu);
2319 CPUX86State *env = &cpu->env;
2320 struct kvm_vcpu_events events = {};
2321
2322 if (!kvm_has_vcpu_events()) {
2323 return 0;
2324 }
2325
2326 events.exception.injected = (env->exception_injected >= 0);
2327 events.exception.nr = env->exception_injected;
2328 events.exception.has_error_code = env->has_error_code;
2329 events.exception.error_code = env->error_code;
2330 events.exception.pad = 0;
2331
2332 events.interrupt.injected = (env->interrupt_injected >= 0);
2333 events.interrupt.nr = env->interrupt_injected;
2334 events.interrupt.soft = env->soft_interrupt;
2335
2336 events.nmi.injected = env->nmi_injected;
2337 events.nmi.pending = env->nmi_pending;
2338 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2339 events.nmi.pad = 0;
2340
2341 events.sipi_vector = env->sipi_vector;
2342
2343 if (has_msr_smbase) {
2344 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2345 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2346 if (kvm_irqchip_in_kernel()) {
2347 /* As soon as these are moved to the kernel, remove them
2348 * from cs->interrupt_request.
2349 */
2350 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2351 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2352 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2353 } else {
2354 /* Keep these in cs->interrupt_request. */
2355 events.smi.pending = 0;
2356 events.smi.latched_init = 0;
2357 }
2358 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2359 }
2360
2361 events.flags = 0;
2362 if (level >= KVM_PUT_RESET_STATE) {
2363 events.flags |=
2364 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2365 }
2366
2367 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2368 }
2369
2370 static int kvm_get_vcpu_events(X86CPU *cpu)
2371 {
2372 CPUX86State *env = &cpu->env;
2373 struct kvm_vcpu_events events;
2374 int ret;
2375
2376 if (!kvm_has_vcpu_events()) {
2377 return 0;
2378 }
2379
2380 memset(&events, 0, sizeof(events));
2381 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2382 if (ret < 0) {
2383 return ret;
2384 }
2385 env->exception_injected =
2386 events.exception.injected ? events.exception.nr : -1;
2387 env->has_error_code = events.exception.has_error_code;
2388 env->error_code = events.exception.error_code;
2389
2390 env->interrupt_injected =
2391 events.interrupt.injected ? events.interrupt.nr : -1;
2392 env->soft_interrupt = events.interrupt.soft;
2393
2394 env->nmi_injected = events.nmi.injected;
2395 env->nmi_pending = events.nmi.pending;
2396 if (events.nmi.masked) {
2397 env->hflags2 |= HF2_NMI_MASK;
2398 } else {
2399 env->hflags2 &= ~HF2_NMI_MASK;
2400 }
2401
2402 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2403 if (events.smi.smm) {
2404 env->hflags |= HF_SMM_MASK;
2405 } else {
2406 env->hflags &= ~HF_SMM_MASK;
2407 }
2408 if (events.smi.pending) {
2409 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2410 } else {
2411 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2412 }
2413 if (events.smi.smm_inside_nmi) {
2414 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2415 } else {
2416 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2417 }
2418 if (events.smi.latched_init) {
2419 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2420 } else {
2421 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2422 }
2423 }
2424
2425 env->sipi_vector = events.sipi_vector;
2426
2427 return 0;
2428 }
2429
2430 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2431 {
2432 CPUState *cs = CPU(cpu);
2433 CPUX86State *env = &cpu->env;
2434 int ret = 0;
2435 unsigned long reinject_trap = 0;
2436
2437 if (!kvm_has_vcpu_events()) {
2438 if (env->exception_injected == 1) {
2439 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2440 } else if (env->exception_injected == 3) {
2441 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2442 }
2443 env->exception_injected = -1;
2444 }
2445
2446 /*
2447 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2448 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2449 * by updating the debug state once again if single-stepping is on.
2450 * Another reason to call kvm_update_guest_debug here is a pending debug
2451 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2452 * reinject them via SET_GUEST_DEBUG.
2453 */
2454 if (reinject_trap ||
2455 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2456 ret = kvm_update_guest_debug(cs, reinject_trap);
2457 }
2458 return ret;
2459 }
2460
2461 static int kvm_put_debugregs(X86CPU *cpu)
2462 {
2463 CPUX86State *env = &cpu->env;
2464 struct kvm_debugregs dbgregs;
2465 int i;
2466
2467 if (!kvm_has_debugregs()) {
2468 return 0;
2469 }
2470
2471 for (i = 0; i < 4; i++) {
2472 dbgregs.db[i] = env->dr[i];
2473 }
2474 dbgregs.dr6 = env->dr[6];
2475 dbgregs.dr7 = env->dr[7];
2476 dbgregs.flags = 0;
2477
2478 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2479 }
2480
2481 static int kvm_get_debugregs(X86CPU *cpu)
2482 {
2483 CPUX86State *env = &cpu->env;
2484 struct kvm_debugregs dbgregs;
2485 int i, ret;
2486
2487 if (!kvm_has_debugregs()) {
2488 return 0;
2489 }
2490
2491 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2492 if (ret < 0) {
2493 return ret;
2494 }
2495 for (i = 0; i < 4; i++) {
2496 env->dr[i] = dbgregs.db[i];
2497 }
2498 env->dr[4] = env->dr[6] = dbgregs.dr6;
2499 env->dr[5] = env->dr[7] = dbgregs.dr7;
2500
2501 return 0;
2502 }
2503
2504 int kvm_arch_put_registers(CPUState *cpu, int level)
2505 {
2506 X86CPU *x86_cpu = X86_CPU(cpu);
2507 int ret;
2508
2509 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2510
2511 if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) {
2512 ret = kvm_put_msr_feature_control(x86_cpu);
2513 if (ret < 0) {
2514 return ret;
2515 }
2516 }
2517
2518 if (level == KVM_PUT_FULL_STATE) {
2519 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2520 * because TSC frequency mismatch shouldn't abort migration,
2521 * unless the user explicitly asked for a more strict TSC
2522 * setting (e.g. using an explicit "tsc-freq" option).
2523 */
2524 kvm_arch_set_tsc_khz(cpu);
2525 }
2526
2527 ret = kvm_getput_regs(x86_cpu, 1);
2528 if (ret < 0) {
2529 return ret;
2530 }
2531 ret = kvm_put_xsave(x86_cpu);
2532 if (ret < 0) {
2533 return ret;
2534 }
2535 ret = kvm_put_xcrs(x86_cpu);
2536 if (ret < 0) {
2537 return ret;
2538 }
2539 ret = kvm_put_sregs(x86_cpu);
2540 if (ret < 0) {
2541 return ret;
2542 }
2543 /* must be before kvm_put_msrs */
2544 ret = kvm_inject_mce_oldstyle(x86_cpu);
2545 if (ret < 0) {
2546 return ret;
2547 }
2548 ret = kvm_put_msrs(x86_cpu, level);
2549 if (ret < 0) {
2550 return ret;
2551 }
2552 if (level >= KVM_PUT_RESET_STATE) {
2553 ret = kvm_put_mp_state(x86_cpu);
2554 if (ret < 0) {
2555 return ret;
2556 }
2557 ret = kvm_put_apic(x86_cpu);
2558 if (ret < 0) {
2559 return ret;
2560 }
2561 }
2562
2563 ret = kvm_put_tscdeadline_msr(x86_cpu);
2564 if (ret < 0) {
2565 return ret;
2566 }
2567
2568 ret = kvm_put_vcpu_events(x86_cpu, level);
2569 if (ret < 0) {
2570 return ret;
2571 }
2572 ret = kvm_put_debugregs(x86_cpu);
2573 if (ret < 0) {
2574 return ret;
2575 }
2576 /* must be last */
2577 ret = kvm_guest_debug_workarounds(x86_cpu);
2578 if (ret < 0) {
2579 return ret;
2580 }
2581 return 0;
2582 }
2583
2584 int kvm_arch_get_registers(CPUState *cs)
2585 {
2586 X86CPU *cpu = X86_CPU(cs);
2587 int ret;
2588
2589 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2590
2591 ret = kvm_getput_regs(cpu, 0);
2592 if (ret < 0) {
2593 goto out;
2594 }
2595 ret = kvm_get_xsave(cpu);
2596 if (ret < 0) {
2597 goto out;
2598 }
2599 ret = kvm_get_xcrs(cpu);
2600 if (ret < 0) {
2601 goto out;
2602 }
2603 ret = kvm_get_sregs(cpu);
2604 if (ret < 0) {
2605 goto out;
2606 }
2607 ret = kvm_get_msrs(cpu);
2608 if (ret < 0) {
2609 goto out;
2610 }
2611 ret = kvm_get_mp_state(cpu);
2612 if (ret < 0) {
2613 goto out;
2614 }
2615 ret = kvm_get_apic(cpu);
2616 if (ret < 0) {
2617 goto out;
2618 }
2619 ret = kvm_get_vcpu_events(cpu);
2620 if (ret < 0) {
2621 goto out;
2622 }
2623 ret = kvm_get_debugregs(cpu);
2624 if (ret < 0) {
2625 goto out;
2626 }
2627 ret = 0;
2628 out:
2629 cpu_sync_bndcs_hflags(&cpu->env);
2630 return ret;
2631 }
2632
2633 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2634 {
2635 X86CPU *x86_cpu = X86_CPU(cpu);
2636 CPUX86State *env = &x86_cpu->env;
2637 int ret;
2638
2639 /* Inject NMI */
2640 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2641 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2642 qemu_mutex_lock_iothread();
2643 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2644 qemu_mutex_unlock_iothread();
2645 DPRINTF("injected NMI\n");
2646 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2647 if (ret < 0) {
2648 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2649 strerror(-ret));
2650 }
2651 }
2652 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2653 qemu_mutex_lock_iothread();
2654 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2655 qemu_mutex_unlock_iothread();
2656 DPRINTF("injected SMI\n");
2657 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2658 if (ret < 0) {
2659 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2660 strerror(-ret));
2661 }
2662 }
2663 }
2664
2665 if (!kvm_pic_in_kernel()) {
2666 qemu_mutex_lock_iothread();
2667 }
2668
2669 /* Force the VCPU out of its inner loop to process any INIT requests
2670 * or (for userspace APIC, but it is cheap to combine the checks here)
2671 * pending TPR access reports.
2672 */
2673 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2674 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2675 !(env->hflags & HF_SMM_MASK)) {
2676 cpu->exit_request = 1;
2677 }
2678 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2679 cpu->exit_request = 1;
2680 }
2681 }
2682
2683 if (!kvm_pic_in_kernel()) {
2684 /* Try to inject an interrupt if the guest can accept it */
2685 if (run->ready_for_interrupt_injection &&
2686 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2687 (env->eflags & IF_MASK)) {
2688 int irq;
2689
2690 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2691 irq = cpu_get_pic_interrupt(env);
2692 if (irq >= 0) {
2693 struct kvm_interrupt intr;
2694
2695 intr.irq = irq;
2696 DPRINTF("injected interrupt %d\n", irq);
2697 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2698 if (ret < 0) {
2699 fprintf(stderr,
2700 "KVM: injection failed, interrupt lost (%s)\n",
2701 strerror(-ret));
2702 }
2703 }
2704 }
2705
2706 /* If we have an interrupt but the guest is not ready to receive an
2707 * interrupt, request an interrupt window exit. This will
2708 * cause a return to userspace as soon as the guest is ready to
2709 * receive interrupts. */
2710 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2711 run->request_interrupt_window = 1;
2712 } else {
2713 run->request_interrupt_window = 0;
2714 }
2715
2716 DPRINTF("setting tpr\n");
2717 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2718
2719 qemu_mutex_unlock_iothread();
2720 }
2721 }
2722
2723 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2724 {
2725 X86CPU *x86_cpu = X86_CPU(cpu);
2726 CPUX86State *env = &x86_cpu->env;
2727
2728 if (run->flags & KVM_RUN_X86_SMM) {
2729 env->hflags |= HF_SMM_MASK;
2730 } else {
2731 env->hflags &= HF_SMM_MASK;
2732 }
2733 if (run->if_flag) {
2734 env->eflags |= IF_MASK;
2735 } else {
2736 env->eflags &= ~IF_MASK;
2737 }
2738
2739 /* We need to protect the apic state against concurrent accesses from
2740 * different threads in case the userspace irqchip is used. */
2741 if (!kvm_irqchip_in_kernel()) {
2742 qemu_mutex_lock_iothread();
2743 }
2744 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2745 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2746 if (!kvm_irqchip_in_kernel()) {
2747 qemu_mutex_unlock_iothread();
2748 }
2749 return cpu_get_mem_attrs(env);
2750 }
2751
2752 int kvm_arch_process_async_events(CPUState *cs)
2753 {
2754 X86CPU *cpu = X86_CPU(cs);
2755 CPUX86State *env = &cpu->env;
2756
2757 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2758 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2759 assert(env->mcg_cap);
2760
2761 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2762
2763 kvm_cpu_synchronize_state(cs);
2764
2765 if (env->exception_injected == EXCP08_DBLE) {
2766 /* this means triple fault */
2767 qemu_system_reset_request();
2768 cs->exit_request = 1;
2769 return 0;
2770 }
2771 env->exception_injected = EXCP12_MCHK;
2772 env->has_error_code = 0;
2773
2774 cs->halted = 0;
2775 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2776 env->mp_state = KVM_MP_STATE_RUNNABLE;
2777 }
2778 }
2779
2780 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2781 !(env->hflags & HF_SMM_MASK)) {
2782 kvm_cpu_synchronize_state(cs);
2783 do_cpu_init(cpu);
2784 }
2785
2786 if (kvm_irqchip_in_kernel()) {
2787 return 0;
2788 }
2789
2790 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2791 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2792 apic_poll_irq(cpu->apic_state);
2793 }
2794 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2795 (env->eflags & IF_MASK)) ||
2796 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2797 cs->halted = 0;
2798 }
2799 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2800 kvm_cpu_synchronize_state(cs);
2801 do_cpu_sipi(cpu);
2802 }
2803 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2804 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2805 kvm_cpu_synchronize_state(cs);
2806 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2807 env->tpr_access_type);
2808 }
2809
2810 return cs->halted;
2811 }
2812
2813 static int kvm_handle_halt(X86CPU *cpu)
2814 {
2815 CPUState *cs = CPU(cpu);
2816 CPUX86State *env = &cpu->env;
2817
2818 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2819 (env->eflags & IF_MASK)) &&
2820 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2821 cs->halted = 1;
2822 return EXCP_HLT;
2823 }
2824
2825 return 0;
2826 }
2827
2828 static int kvm_handle_tpr_access(X86CPU *cpu)
2829 {
2830 CPUState *cs = CPU(cpu);
2831 struct kvm_run *run = cs->kvm_run;
2832
2833 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2834 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2835 : TPR_ACCESS_READ);
2836 return 1;
2837 }
2838
2839 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2840 {
2841 static const uint8_t int3 = 0xcc;
2842
2843 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2844 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2845 return -EINVAL;
2846 }
2847 return 0;
2848 }
2849
2850 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2851 {
2852 uint8_t int3;
2853
2854 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2855 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2856 return -EINVAL;
2857 }
2858 return 0;
2859 }
2860
2861 static struct {
2862 target_ulong addr;
2863 int len;
2864 int type;
2865 } hw_breakpoint[4];
2866
2867 static int nb_hw_breakpoint;
2868
2869 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2870 {
2871 int n;
2872
2873 for (n = 0; n < nb_hw_breakpoint; n++) {
2874 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2875 (hw_breakpoint[n].len == len || len == -1)) {
2876 return n;
2877 }
2878 }
2879 return -1;
2880 }
2881
2882 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2883 target_ulong len, int type)
2884 {
2885 switch (type) {
2886 case GDB_BREAKPOINT_HW:
2887 len = 1;
2888 break;
2889 case GDB_WATCHPOINT_WRITE:
2890 case GDB_WATCHPOINT_ACCESS:
2891 switch (len) {
2892 case 1:
2893 break;
2894 case 2:
2895 case 4:
2896 case 8:
2897 if (addr & (len - 1)) {
2898 return -EINVAL;
2899 }
2900 break;
2901 default:
2902 return -EINVAL;
2903 }
2904 break;
2905 default:
2906 return -ENOSYS;
2907 }
2908
2909 if (nb_hw_breakpoint == 4) {
2910 return -ENOBUFS;
2911 }
2912 if (find_hw_breakpoint(addr, len, type) >= 0) {
2913 return -EEXIST;
2914 }
2915 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2916 hw_breakpoint[nb_hw_breakpoint].len = len;
2917 hw_breakpoint[nb_hw_breakpoint].type = type;
2918 nb_hw_breakpoint++;
2919
2920 return 0;
2921 }
2922
2923 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2924 target_ulong len, int type)
2925 {
2926 int n;
2927
2928 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2929 if (n < 0) {
2930 return -ENOENT;
2931 }
2932 nb_hw_breakpoint--;
2933 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2934
2935 return 0;
2936 }
2937
2938 void kvm_arch_remove_all_hw_breakpoints(void)
2939 {
2940 nb_hw_breakpoint = 0;
2941 }
2942
2943 static CPUWatchpoint hw_watchpoint;
2944
2945 static int kvm_handle_debug(X86CPU *cpu,
2946 struct kvm_debug_exit_arch *arch_info)
2947 {
2948 CPUState *cs = CPU(cpu);
2949 CPUX86State *env = &cpu->env;
2950 int ret = 0;
2951 int n;
2952
2953 if (arch_info->exception == 1) {
2954 if (arch_info->dr6 & (1 << 14)) {
2955 if (cs->singlestep_enabled) {
2956 ret = EXCP_DEBUG;
2957 }
2958 } else {
2959 for (n = 0; n < 4; n++) {
2960 if (arch_info->dr6 & (1 << n)) {
2961 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2962 case 0x0:
2963 ret = EXCP_DEBUG;
2964 break;
2965 case 0x1:
2966 ret = EXCP_DEBUG;
2967 cs->watchpoint_hit = &hw_watchpoint;
2968 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2969 hw_watchpoint.flags = BP_MEM_WRITE;
2970 break;
2971 case 0x3:
2972 ret = EXCP_DEBUG;
2973 cs->watchpoint_hit = &hw_watchpoint;
2974 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2975 hw_watchpoint.flags = BP_MEM_ACCESS;
2976 break;
2977 }
2978 }
2979 }
2980 }
2981 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
2982 ret = EXCP_DEBUG;
2983 }
2984 if (ret == 0) {
2985 cpu_synchronize_state(cs);
2986 assert(env->exception_injected == -1);
2987
2988 /* pass to guest */
2989 env->exception_injected = arch_info->exception;
2990 env->has_error_code = 0;
2991 }
2992
2993 return ret;
2994 }
2995
2996 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2997 {
2998 const uint8_t type_code[] = {
2999 [GDB_BREAKPOINT_HW] = 0x0,
3000 [GDB_WATCHPOINT_WRITE] = 0x1,
3001 [GDB_WATCHPOINT_ACCESS] = 0x3
3002 };
3003 const uint8_t len_code[] = {
3004 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3005 };
3006 int n;
3007
3008 if (kvm_sw_breakpoints_active(cpu)) {
3009 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3010 }
3011 if (nb_hw_breakpoint > 0) {
3012 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3013 dbg->arch.debugreg[7] = 0x0600;
3014 for (n = 0; n < nb_hw_breakpoint; n++) {
3015 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3016 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3017 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3018 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3019 }
3020 }
3021 }
3022
3023 static bool host_supports_vmx(void)
3024 {
3025 uint32_t ecx, unused;
3026
3027 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3028 return ecx & CPUID_EXT_VMX;
3029 }
3030
3031 #define VMX_INVALID_GUEST_STATE 0x80000021
3032
3033 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3034 {
3035 X86CPU *cpu = X86_CPU(cs);
3036 uint64_t code;
3037 int ret;
3038
3039 switch (run->exit_reason) {
3040 case KVM_EXIT_HLT:
3041 DPRINTF("handle_hlt\n");
3042 qemu_mutex_lock_iothread();
3043 ret = kvm_handle_halt(cpu);
3044 qemu_mutex_unlock_iothread();
3045 break;
3046 case KVM_EXIT_SET_TPR:
3047 ret = 0;
3048 break;
3049 case KVM_EXIT_TPR_ACCESS:
3050 qemu_mutex_lock_iothread();
3051 ret = kvm_handle_tpr_access(cpu);
3052 qemu_mutex_unlock_iothread();
3053 break;
3054 case KVM_EXIT_FAIL_ENTRY:
3055 code = run->fail_entry.hardware_entry_failure_reason;
3056 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3057 code);
3058 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3059 fprintf(stderr,
3060 "\nIf you're running a guest on an Intel machine without "
3061 "unrestricted mode\n"
3062 "support, the failure can be most likely due to the guest "
3063 "entering an invalid\n"
3064 "state for Intel VT. For example, the guest maybe running "
3065 "in big real mode\n"
3066 "which is not supported on less recent Intel processors."
3067 "\n\n");
3068 }
3069 ret = -1;
3070 break;
3071 case KVM_EXIT_EXCEPTION:
3072 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3073 run->ex.exception, run->ex.error_code);
3074 ret = -1;
3075 break;
3076 case KVM_EXIT_DEBUG:
3077 DPRINTF("kvm_exit_debug\n");
3078 qemu_mutex_lock_iothread();
3079 ret = kvm_handle_debug(cpu, &run->debug.arch);
3080 qemu_mutex_unlock_iothread();
3081 break;
3082 case KVM_EXIT_HYPERV:
3083 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3084 break;
3085 case KVM_EXIT_IOAPIC_EOI:
3086 ioapic_eoi_broadcast(run->eoi.vector);
3087 ret = 0;
3088 break;
3089 default:
3090 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3091 ret = -1;
3092 break;
3093 }
3094
3095 return ret;
3096 }
3097
3098 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3099 {
3100 X86CPU *cpu = X86_CPU(cs);
3101 CPUX86State *env = &cpu->env;
3102
3103 kvm_cpu_synchronize_state(cs);
3104 return !(env->cr[0] & CR0_PE_MASK) ||
3105 ((env->segs[R_CS].selector & 3) != 3);
3106 }
3107
3108 void kvm_arch_init_irq_routing(KVMState *s)
3109 {
3110 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3111 /* If kernel can't do irq routing, interrupt source
3112 * override 0->2 cannot be set up as required by HPET.
3113 * So we have to disable it.
3114 */
3115 no_hpet = 1;
3116 }
3117 /* We know at this point that we're using the in-kernel
3118 * irqchip, so we can use irqfds, and on x86 we know
3119 * we can use msi via irqfd and GSI routing.
3120 */
3121 kvm_msi_via_irqfd_allowed = true;
3122 kvm_gsi_routing_allowed = true;
3123
3124 if (kvm_irqchip_is_split()) {
3125 int i;
3126
3127 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3128 MSI routes for signaling interrupts to the local apics. */
3129 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3130 struct MSIMessage msg = { 0x0, 0x0 };
3131 if (kvm_irqchip_add_msi_route(s, msg, NULL) < 0) {
3132 error_report("Could not enable split IRQ mode.");
3133 exit(1);
3134 }
3135 }
3136 }
3137 }
3138
3139 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3140 {
3141 int ret;
3142 if (machine_kernel_irqchip_split(ms)) {
3143 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3144 if (ret) {
3145 error_report("Could not enable split irqchip mode: %s\n",
3146 strerror(-ret));
3147 exit(1);
3148 } else {
3149 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3150 kvm_split_irqchip = true;
3151 return 1;
3152 }
3153 } else {
3154 return 0;
3155 }
3156 }
3157
3158 /* Classic KVM device assignment interface. Will remain x86 only. */
3159 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3160 uint32_t flags, uint32_t *dev_id)
3161 {
3162 struct kvm_assigned_pci_dev dev_data = {
3163 .segnr = dev_addr->domain,
3164 .busnr = dev_addr->bus,
3165 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3166 .flags = flags,
3167 };
3168 int ret;
3169
3170 dev_data.assigned_dev_id =
3171 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3172
3173 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3174 if (ret < 0) {
3175 return ret;
3176 }
3177
3178 *dev_id = dev_data.assigned_dev_id;
3179
3180 return 0;
3181 }
3182
3183 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3184 {
3185 struct kvm_assigned_pci_dev dev_data = {
3186 .assigned_dev_id = dev_id,
3187 };
3188
3189 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3190 }
3191
3192 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3193 uint32_t irq_type, uint32_t guest_irq)
3194 {
3195 struct kvm_assigned_irq assigned_irq = {
3196 .assigned_dev_id = dev_id,
3197 .guest_irq = guest_irq,
3198 .flags = irq_type,
3199 };
3200
3201 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3202 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3203 } else {
3204 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3205 }
3206 }
3207
3208 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3209 uint32_t guest_irq)
3210 {
3211 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3212 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3213
3214 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3215 }
3216
3217 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3218 {
3219 struct kvm_assigned_pci_dev dev_data = {
3220 .assigned_dev_id = dev_id,
3221 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3222 };
3223
3224 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3225 }
3226
3227 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3228 uint32_t type)
3229 {
3230 struct kvm_assigned_irq assigned_irq = {
3231 .assigned_dev_id = dev_id,
3232 .flags = type,
3233 };
3234
3235 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3236 }
3237
3238 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3239 {
3240 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3241 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3242 }
3243
3244 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3245 {
3246 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3247 KVM_DEV_IRQ_GUEST_MSI, virq);
3248 }
3249
3250 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3251 {
3252 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3253 KVM_DEV_IRQ_HOST_MSI);
3254 }
3255
3256 bool kvm_device_msix_supported(KVMState *s)
3257 {
3258 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3259 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3260 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3261 }
3262
3263 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3264 uint32_t nr_vectors)
3265 {
3266 struct kvm_assigned_msix_nr msix_nr = {
3267 .assigned_dev_id = dev_id,
3268 .entry_nr = nr_vectors,
3269 };
3270
3271 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3272 }
3273
3274 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3275 int virq)
3276 {
3277 struct kvm_assigned_msix_entry msix_entry = {
3278 .assigned_dev_id = dev_id,
3279 .gsi = virq,
3280 .entry = vector,
3281 };
3282
3283 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3284 }
3285
3286 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3287 {
3288 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3289 KVM_DEV_IRQ_GUEST_MSIX, 0);
3290 }
3291
3292 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3293 {
3294 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3295 KVM_DEV_IRQ_HOST_MSIX);
3296 }
3297
3298 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3299 uint64_t address, uint32_t data, PCIDevice *dev)
3300 {
3301 return 0;
3302 }
3303
3304 int kvm_arch_msi_data_to_gsi(uint32_t data)
3305 {
3306 abort();
3307 }
Mirror of https://git.qemu.org/git/qemu.git