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[thirdparty/qemu.git] / target-sparc / ldst_helper.c
1 /*
2 * Helpers for loads and stores
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "exec/helper-proto.h"
22
23 //#define DEBUG_MMU
24 //#define DEBUG_MXCC
25 //#define DEBUG_UNALIGNED
26 //#define DEBUG_UNASSIGNED
27 //#define DEBUG_ASI
28 //#define DEBUG_CACHE_CONTROL
29
30 #ifdef DEBUG_MMU
31 #define DPRINTF_MMU(fmt, ...) \
32 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
33 #else
34 #define DPRINTF_MMU(fmt, ...) do {} while (0)
35 #endif
36
37 #ifdef DEBUG_MXCC
38 #define DPRINTF_MXCC(fmt, ...) \
39 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
40 #else
41 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
42 #endif
43
44 #ifdef DEBUG_ASI
45 #define DPRINTF_ASI(fmt, ...) \
46 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
47 #endif
48
49 #ifdef DEBUG_CACHE_CONTROL
50 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
51 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
52 #else
53 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
54 #endif
55
56 #ifdef TARGET_SPARC64
57 #ifndef TARGET_ABI32
58 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
59 #else
60 #define AM_CHECK(env1) (1)
61 #endif
62 #endif
63
64 #define QT0 (env->qt0)
65 #define QT1 (env->qt1)
66
67 #if !defined(CONFIG_USER_ONLY)
68 #include "exec/softmmu_exec.h"
69 #define MMUSUFFIX _mmu
70 #define ALIGNED_ONLY
71
72 #define SHIFT 0
73 #include "exec/softmmu_template.h"
74
75 #define SHIFT 1
76 #include "exec/softmmu_template.h"
77
78 #define SHIFT 2
79 #include "exec/softmmu_template.h"
80
81 #define SHIFT 3
82 #include "exec/softmmu_template.h"
83 #endif
84
85 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
86 /* Calculates TSB pointer value for fault page size 8k or 64k */
87 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
88 uint64_t tag_access_register,
89 int page_size)
90 {
91 uint64_t tsb_base = tsb_register & ~0x1fffULL;
92 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
93 int tsb_size = tsb_register & 0xf;
94
95 /* discard lower 13 bits which hold tag access context */
96 uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
97
98 /* now reorder bits */
99 uint64_t tsb_base_mask = ~0x1fffULL;
100 uint64_t va = tag_access_va;
101
102 /* move va bits to correct position */
103 if (page_size == 8*1024) {
104 va >>= 9;
105 } else if (page_size == 64*1024) {
106 va >>= 12;
107 }
108
109 if (tsb_size) {
110 tsb_base_mask <<= tsb_size;
111 }
112
113 /* calculate tsb_base mask and adjust va if split is in use */
114 if (tsb_split) {
115 if (page_size == 8*1024) {
116 va &= ~(1ULL << (13 + tsb_size));
117 } else if (page_size == 64*1024) {
118 va |= (1ULL << (13 + tsb_size));
119 }
120 tsb_base_mask <<= 1;
121 }
122
123 return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
124 }
125
126 /* Calculates tag target register value by reordering bits
127 in tag access register */
128 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
129 {
130 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
131 }
132
133 static void replace_tlb_entry(SparcTLBEntry *tlb,
134 uint64_t tlb_tag, uint64_t tlb_tte,
135 CPUSPARCState *env1)
136 {
137 target_ulong mask, size, va, offset;
138
139 /* flush page range if translation is valid */
140 if (TTE_IS_VALID(tlb->tte)) {
141 CPUState *cs = CPU(sparc_env_get_cpu(env1));
142
143 mask = 0xffffffffffffe000ULL;
144 mask <<= 3 * ((tlb->tte >> 61) & 3);
145 size = ~mask + 1;
146
147 va = tlb->tag & mask;
148
149 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
150 tlb_flush_page(cs, va + offset);
151 }
152 }
153
154 tlb->tag = tlb_tag;
155 tlb->tte = tlb_tte;
156 }
157
158 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
159 const char *strmmu, CPUSPARCState *env1)
160 {
161 unsigned int i;
162 target_ulong mask;
163 uint64_t context;
164
165 int is_demap_context = (demap_addr >> 6) & 1;
166
167 /* demap context */
168 switch ((demap_addr >> 4) & 3) {
169 case 0: /* primary */
170 context = env1->dmmu.mmu_primary_context;
171 break;
172 case 1: /* secondary */
173 context = env1->dmmu.mmu_secondary_context;
174 break;
175 case 2: /* nucleus */
176 context = 0;
177 break;
178 case 3: /* reserved */
179 default:
180 return;
181 }
182
183 for (i = 0; i < 64; i++) {
184 if (TTE_IS_VALID(tlb[i].tte)) {
185
186 if (is_demap_context) {
187 /* will remove non-global entries matching context value */
188 if (TTE_IS_GLOBAL(tlb[i].tte) ||
189 !tlb_compare_context(&tlb[i], context)) {
190 continue;
191 }
192 } else {
193 /* demap page
194 will remove any entry matching VA */
195 mask = 0xffffffffffffe000ULL;
196 mask <<= 3 * ((tlb[i].tte >> 61) & 3);
197
198 if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
199 continue;
200 }
201
202 /* entry should be global or matching context value */
203 if (!TTE_IS_GLOBAL(tlb[i].tte) &&
204 !tlb_compare_context(&tlb[i], context)) {
205 continue;
206 }
207 }
208
209 replace_tlb_entry(&tlb[i], 0, 0, env1);
210 #ifdef DEBUG_MMU
211 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
212 dump_mmu(stdout, fprintf, env1);
213 #endif
214 }
215 }
216 }
217
218 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
219 uint64_t tlb_tag, uint64_t tlb_tte,
220 const char *strmmu, CPUSPARCState *env1)
221 {
222 unsigned int i, replace_used;
223
224 /* Try replacing invalid entry */
225 for (i = 0; i < 64; i++) {
226 if (!TTE_IS_VALID(tlb[i].tte)) {
227 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
228 #ifdef DEBUG_MMU
229 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
230 dump_mmu(stdout, fprintf, env1);
231 #endif
232 return;
233 }
234 }
235
236 /* All entries are valid, try replacing unlocked entry */
237
238 for (replace_used = 0; replace_used < 2; ++replace_used) {
239
240 /* Used entries are not replaced on first pass */
241
242 for (i = 0; i < 64; i++) {
243 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
244
245 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
246 #ifdef DEBUG_MMU
247 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
248 strmmu, (replace_used ? "used" : "unused"), i);
249 dump_mmu(stdout, fprintf, env1);
250 #endif
251 return;
252 }
253 }
254
255 /* Now reset used bit and search for unused entries again */
256
257 for (i = 0; i < 64; i++) {
258 TTE_SET_UNUSED(tlb[i].tte);
259 }
260 }
261
262 #ifdef DEBUG_MMU
263 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
264 #endif
265 /* error state? */
266 }
267
268 #endif
269
270 static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr)
271 {
272 #ifdef TARGET_SPARC64
273 if (AM_CHECK(env1)) {
274 addr &= 0xffffffffULL;
275 }
276 #endif
277 return addr;
278 }
279
280 /* returns true if access using this ASI is to have address translated by MMU
281 otherwise access is to raw physical address */
282 static inline int is_translating_asi(int asi)
283 {
284 #ifdef TARGET_SPARC64
285 /* Ultrasparc IIi translating asi
286 - note this list is defined by cpu implementation
287 */
288 switch (asi) {
289 case 0x04 ... 0x11:
290 case 0x16 ... 0x19:
291 case 0x1E ... 0x1F:
292 case 0x24 ... 0x2C:
293 case 0x70 ... 0x73:
294 case 0x78 ... 0x79:
295 case 0x80 ... 0xFF:
296 return 1;
297
298 default:
299 return 0;
300 }
301 #else
302 /* TODO: check sparc32 bits */
303 return 0;
304 #endif
305 }
306
307 static inline target_ulong asi_address_mask(CPUSPARCState *env,
308 int asi, target_ulong addr)
309 {
310 if (is_translating_asi(asi)) {
311 return address_mask(env, addr);
312 } else {
313 return addr;
314 }
315 }
316
317 void helper_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align)
318 {
319 if (addr & align) {
320 #ifdef DEBUG_UNALIGNED
321 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
322 "\n", addr, env->pc);
323 #endif
324 helper_raise_exception(env, TT_UNALIGNED);
325 }
326 }
327
328 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
329 defined(DEBUG_MXCC)
330 static void dump_mxcc(CPUSPARCState *env)
331 {
332 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
333 "\n",
334 env->mxccdata[0], env->mxccdata[1],
335 env->mxccdata[2], env->mxccdata[3]);
336 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
337 "\n"
338 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
339 "\n",
340 env->mxccregs[0], env->mxccregs[1],
341 env->mxccregs[2], env->mxccregs[3],
342 env->mxccregs[4], env->mxccregs[5],
343 env->mxccregs[6], env->mxccregs[7]);
344 }
345 #endif
346
347 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
348 && defined(DEBUG_ASI)
349 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
350 uint64_t r1)
351 {
352 switch (size) {
353 case 1:
354 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
355 addr, asi, r1 & 0xff);
356 break;
357 case 2:
358 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
359 addr, asi, r1 & 0xffff);
360 break;
361 case 4:
362 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
363 addr, asi, r1 & 0xffffffff);
364 break;
365 case 8:
366 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
367 addr, asi, r1);
368 break;
369 }
370 }
371 #endif
372
373 #ifndef TARGET_SPARC64
374 #ifndef CONFIG_USER_ONLY
375
376
377 /* Leon3 cache control */
378
379 static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr,
380 uint64_t val, int size)
381 {
382 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",
383 addr, val, size);
384
385 if (size != 4) {
386 DPRINTF_CACHE_CONTROL("32bits only\n");
387 return;
388 }
389
390 switch (addr) {
391 case 0x00: /* Cache control */
392
393 /* These values must always be read as zeros */
394 val &= ~CACHE_CTRL_FD;
395 val &= ~CACHE_CTRL_FI;
396 val &= ~CACHE_CTRL_IB;
397 val &= ~CACHE_CTRL_IP;
398 val &= ~CACHE_CTRL_DP;
399
400 env->cache_control = val;
401 break;
402 case 0x04: /* Instruction cache configuration */
403 case 0x08: /* Data cache configuration */
404 /* Read Only */
405 break;
406 default:
407 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
408 break;
409 };
410 }
411
412 static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr,
413 int size)
414 {
415 uint64_t ret = 0;
416
417 if (size != 4) {
418 DPRINTF_CACHE_CONTROL("32bits only\n");
419 return 0;
420 }
421
422 switch (addr) {
423 case 0x00: /* Cache control */
424 ret = env->cache_control;
425 break;
426
427 /* Configuration registers are read and only always keep those
428 predefined values */
429
430 case 0x04: /* Instruction cache configuration */
431 ret = 0x10220000;
432 break;
433 case 0x08: /* Data cache configuration */
434 ret = 0x18220000;
435 break;
436 default:
437 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
438 break;
439 };
440 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n",
441 addr, ret, size);
442 return ret;
443 }
444
445 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
446 int sign)
447 {
448 CPUState *cs = CPU(sparc_env_get_cpu(env));
449 uint64_t ret = 0;
450 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
451 uint32_t last_addr = addr;
452 #endif
453
454 helper_check_align(env, addr, size - 1);
455 switch (asi) {
456 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
457 switch (addr) {
458 case 0x00: /* Leon3 Cache Control */
459 case 0x08: /* Leon3 Instruction Cache config */
460 case 0x0C: /* Leon3 Date Cache config */
461 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
462 ret = leon3_cache_control_ld(env, addr, size);
463 }
464 break;
465 case 0x01c00a00: /* MXCC control register */
466 if (size == 8) {
467 ret = env->mxccregs[3];
468 } else {
469 qemu_log_mask(LOG_UNIMP,
470 "%08x: unimplemented access size: %d\n", addr,
471 size);
472 }
473 break;
474 case 0x01c00a04: /* MXCC control register */
475 if (size == 4) {
476 ret = env->mxccregs[3];
477 } else {
478 qemu_log_mask(LOG_UNIMP,
479 "%08x: unimplemented access size: %d\n", addr,
480 size);
481 }
482 break;
483 case 0x01c00c00: /* Module reset register */
484 if (size == 8) {
485 ret = env->mxccregs[5];
486 /* should we do something here? */
487 } else {
488 qemu_log_mask(LOG_UNIMP,
489 "%08x: unimplemented access size: %d\n", addr,
490 size);
491 }
492 break;
493 case 0x01c00f00: /* MBus port address register */
494 if (size == 8) {
495 ret = env->mxccregs[7];
496 } else {
497 qemu_log_mask(LOG_UNIMP,
498 "%08x: unimplemented access size: %d\n", addr,
499 size);
500 }
501 break;
502 default:
503 qemu_log_mask(LOG_UNIMP,
504 "%08x: unimplemented address, size: %d\n", addr,
505 size);
506 break;
507 }
508 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
509 "addr = %08x -> ret = %" PRIx64 ","
510 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
511 #ifdef DEBUG_MXCC
512 dump_mxcc(env);
513 #endif
514 break;
515 case 3: /* MMU probe */
516 case 0x18: /* LEON3 MMU probe */
517 {
518 int mmulev;
519
520 mmulev = (addr >> 8) & 15;
521 if (mmulev > 4) {
522 ret = 0;
523 } else {
524 ret = mmu_probe(env, addr, mmulev);
525 }
526 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
527 addr, mmulev, ret);
528 }
529 break;
530 case 4: /* read MMU regs */
531 case 0x19: /* LEON3 read MMU regs */
532 {
533 int reg = (addr >> 8) & 0x1f;
534
535 ret = env->mmuregs[reg];
536 if (reg == 3) { /* Fault status cleared on read */
537 env->mmuregs[3] = 0;
538 } else if (reg == 0x13) { /* Fault status read */
539 ret = env->mmuregs[3];
540 } else if (reg == 0x14) { /* Fault address read */
541 ret = env->mmuregs[4];
542 }
543 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
544 }
545 break;
546 case 5: /* Turbosparc ITLB Diagnostic */
547 case 6: /* Turbosparc DTLB Diagnostic */
548 case 7: /* Turbosparc IOTLB Diagnostic */
549 break;
550 case 9: /* Supervisor code access */
551 switch (size) {
552 case 1:
553 ret = cpu_ldub_code(env, addr);
554 break;
555 case 2:
556 ret = cpu_lduw_code(env, addr);
557 break;
558 default:
559 case 4:
560 ret = cpu_ldl_code(env, addr);
561 break;
562 case 8:
563 ret = cpu_ldq_code(env, addr);
564 break;
565 }
566 break;
567 case 0xa: /* User data access */
568 switch (size) {
569 case 1:
570 ret = cpu_ldub_user(env, addr);
571 break;
572 case 2:
573 ret = cpu_lduw_user(env, addr);
574 break;
575 default:
576 case 4:
577 ret = cpu_ldl_user(env, addr);
578 break;
579 case 8:
580 ret = cpu_ldq_user(env, addr);
581 break;
582 }
583 break;
584 case 0xb: /* Supervisor data access */
585 case 0x80:
586 switch (size) {
587 case 1:
588 ret = cpu_ldub_kernel(env, addr);
589 break;
590 case 2:
591 ret = cpu_lduw_kernel(env, addr);
592 break;
593 default:
594 case 4:
595 ret = cpu_ldl_kernel(env, addr);
596 break;
597 case 8:
598 ret = cpu_ldq_kernel(env, addr);
599 break;
600 }
601 break;
602 case 0xc: /* I-cache tag */
603 case 0xd: /* I-cache data */
604 case 0xe: /* D-cache tag */
605 case 0xf: /* D-cache data */
606 break;
607 case 0x20: /* MMU passthrough */
608 case 0x1c: /* LEON MMU passthrough */
609 switch (size) {
610 case 1:
611 ret = ldub_phys(cs->as, addr);
612 break;
613 case 2:
614 ret = lduw_phys(cs->as, addr);
615 break;
616 default:
617 case 4:
618 ret = ldl_phys(cs->as, addr);
619 break;
620 case 8:
621 ret = ldq_phys(cs->as, addr);
622 break;
623 }
624 break;
625 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
626 switch (size) {
627 case 1:
628 ret = ldub_phys(cs->as, (hwaddr)addr
629 | ((hwaddr)(asi & 0xf) << 32));
630 break;
631 case 2:
632 ret = lduw_phys(cs->as, (hwaddr)addr
633 | ((hwaddr)(asi & 0xf) << 32));
634 break;
635 default:
636 case 4:
637 ret = ldl_phys(cs->as, (hwaddr)addr
638 | ((hwaddr)(asi & 0xf) << 32));
639 break;
640 case 8:
641 ret = ldq_phys(cs->as, (hwaddr)addr
642 | ((hwaddr)(asi & 0xf) << 32));
643 break;
644 }
645 break;
646 case 0x30: /* Turbosparc secondary cache diagnostic */
647 case 0x31: /* Turbosparc RAM snoop */
648 case 0x32: /* Turbosparc page table descriptor diagnostic */
649 case 0x39: /* data cache diagnostic register */
650 ret = 0;
651 break;
652 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
653 {
654 int reg = (addr >> 8) & 3;
655
656 switch (reg) {
657 case 0: /* Breakpoint Value (Addr) */
658 ret = env->mmubpregs[reg];
659 break;
660 case 1: /* Breakpoint Mask */
661 ret = env->mmubpregs[reg];
662 break;
663 case 2: /* Breakpoint Control */
664 ret = env->mmubpregs[reg];
665 break;
666 case 3: /* Breakpoint Status */
667 ret = env->mmubpregs[reg];
668 env->mmubpregs[reg] = 0ULL;
669 break;
670 }
671 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
672 ret);
673 }
674 break;
675 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
676 ret = env->mmubpctrv;
677 break;
678 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
679 ret = env->mmubpctrc;
680 break;
681 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
682 ret = env->mmubpctrs;
683 break;
684 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
685 ret = env->mmubpaction;
686 break;
687 case 8: /* User code access, XXX */
688 default:
689 cpu_unassigned_access(cs, addr, false, false, asi, size);
690 ret = 0;
691 break;
692 }
693 if (sign) {
694 switch (size) {
695 case 1:
696 ret = (int8_t) ret;
697 break;
698 case 2:
699 ret = (int16_t) ret;
700 break;
701 case 4:
702 ret = (int32_t) ret;
703 break;
704 default:
705 break;
706 }
707 }
708 #ifdef DEBUG_ASI
709 dump_asi("read ", last_addr, asi, size, ret);
710 #endif
711 return ret;
712 }
713
714 void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
715 int size)
716 {
717 SPARCCPU *cpu = sparc_env_get_cpu(env);
718 CPUState *cs = CPU(cpu);
719
720 helper_check_align(env, addr, size - 1);
721 switch (asi) {
722 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
723 switch (addr) {
724 case 0x00: /* Leon3 Cache Control */
725 case 0x08: /* Leon3 Instruction Cache config */
726 case 0x0C: /* Leon3 Date Cache config */
727 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
728 leon3_cache_control_st(env, addr, val, size);
729 }
730 break;
731
732 case 0x01c00000: /* MXCC stream data register 0 */
733 if (size == 8) {
734 env->mxccdata[0] = val;
735 } else {
736 qemu_log_mask(LOG_UNIMP,
737 "%08x: unimplemented access size: %d\n", addr,
738 size);
739 }
740 break;
741 case 0x01c00008: /* MXCC stream data register 1 */
742 if (size == 8) {
743 env->mxccdata[1] = val;
744 } else {
745 qemu_log_mask(LOG_UNIMP,
746 "%08x: unimplemented access size: %d\n", addr,
747 size);
748 }
749 break;
750 case 0x01c00010: /* MXCC stream data register 2 */
751 if (size == 8) {
752 env->mxccdata[2] = val;
753 } else {
754 qemu_log_mask(LOG_UNIMP,
755 "%08x: unimplemented access size: %d\n", addr,
756 size);
757 }
758 break;
759 case 0x01c00018: /* MXCC stream data register 3 */
760 if (size == 8) {
761 env->mxccdata[3] = val;
762 } else {
763 qemu_log_mask(LOG_UNIMP,
764 "%08x: unimplemented access size: %d\n", addr,
765 size);
766 }
767 break;
768 case 0x01c00100: /* MXCC stream source */
769 if (size == 8) {
770 env->mxccregs[0] = val;
771 } else {
772 qemu_log_mask(LOG_UNIMP,
773 "%08x: unimplemented access size: %d\n", addr,
774 size);
775 }
776 env->mxccdata[0] = ldq_phys(cs->as,
777 (env->mxccregs[0] & 0xffffffffULL) +
778 0);
779 env->mxccdata[1] = ldq_phys(cs->as,
780 (env->mxccregs[0] & 0xffffffffULL) +
781 8);
782 env->mxccdata[2] = ldq_phys(cs->as,
783 (env->mxccregs[0] & 0xffffffffULL) +
784 16);
785 env->mxccdata[3] = ldq_phys(cs->as,
786 (env->mxccregs[0] & 0xffffffffULL) +
787 24);
788 break;
789 case 0x01c00200: /* MXCC stream destination */
790 if (size == 8) {
791 env->mxccregs[1] = val;
792 } else {
793 qemu_log_mask(LOG_UNIMP,
794 "%08x: unimplemented access size: %d\n", addr,
795 size);
796 }
797 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 0,
798 env->mxccdata[0]);
799 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 8,
800 env->mxccdata[1]);
801 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 16,
802 env->mxccdata[2]);
803 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 24,
804 env->mxccdata[3]);
805 break;
806 case 0x01c00a00: /* MXCC control register */
807 if (size == 8) {
808 env->mxccregs[3] = val;
809 } else {
810 qemu_log_mask(LOG_UNIMP,
811 "%08x: unimplemented access size: %d\n", addr,
812 size);
813 }
814 break;
815 case 0x01c00a04: /* MXCC control register */
816 if (size == 4) {
817 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
818 | val;
819 } else {
820 qemu_log_mask(LOG_UNIMP,
821 "%08x: unimplemented access size: %d\n", addr,
822 size);
823 }
824 break;
825 case 0x01c00e00: /* MXCC error register */
826 /* writing a 1 bit clears the error */
827 if (size == 8) {
828 env->mxccregs[6] &= ~val;
829 } else {
830 qemu_log_mask(LOG_UNIMP,
831 "%08x: unimplemented access size: %d\n", addr,
832 size);
833 }
834 break;
835 case 0x01c00f00: /* MBus port address register */
836 if (size == 8) {
837 env->mxccregs[7] = val;
838 } else {
839 qemu_log_mask(LOG_UNIMP,
840 "%08x: unimplemented access size: %d\n", addr,
841 size);
842 }
843 break;
844 default:
845 qemu_log_mask(LOG_UNIMP,
846 "%08x: unimplemented address, size: %d\n", addr,
847 size);
848 break;
849 }
850 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
851 asi, size, addr, val);
852 #ifdef DEBUG_MXCC
853 dump_mxcc(env);
854 #endif
855 break;
856 case 3: /* MMU flush */
857 case 0x18: /* LEON3 MMU flush */
858 {
859 int mmulev;
860
861 mmulev = (addr >> 8) & 15;
862 DPRINTF_MMU("mmu flush level %d\n", mmulev);
863 switch (mmulev) {
864 case 0: /* flush page */
865 tlb_flush_page(CPU(cpu), addr & 0xfffff000);
866 break;
867 case 1: /* flush segment (256k) */
868 case 2: /* flush region (16M) */
869 case 3: /* flush context (4G) */
870 case 4: /* flush entire */
871 tlb_flush(CPU(cpu), 1);
872 break;
873 default:
874 break;
875 }
876 #ifdef DEBUG_MMU
877 dump_mmu(stdout, fprintf, env);
878 #endif
879 }
880 break;
881 case 4: /* write MMU regs */
882 case 0x19: /* LEON3 write MMU regs */
883 {
884 int reg = (addr >> 8) & 0x1f;
885 uint32_t oldreg;
886
887 oldreg = env->mmuregs[reg];
888 switch (reg) {
889 case 0: /* Control Register */
890 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
891 (val & 0x00ffffff);
892 /* Mappings generated during no-fault mode or MMU
893 disabled mode are invalid in normal mode */
894 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
895 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) {
896 tlb_flush(CPU(cpu), 1);
897 }
898 break;
899 case 1: /* Context Table Pointer Register */
900 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
901 break;
902 case 2: /* Context Register */
903 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
904 if (oldreg != env->mmuregs[reg]) {
905 /* we flush when the MMU context changes because
906 QEMU has no MMU context support */
907 tlb_flush(CPU(cpu), 1);
908 }
909 break;
910 case 3: /* Synchronous Fault Status Register with Clear */
911 case 4: /* Synchronous Fault Address Register */
912 break;
913 case 0x10: /* TLB Replacement Control Register */
914 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
915 break;
916 case 0x13: /* Synchronous Fault Status Register with Read
917 and Clear */
918 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
919 break;
920 case 0x14: /* Synchronous Fault Address Register */
921 env->mmuregs[4] = val;
922 break;
923 default:
924 env->mmuregs[reg] = val;
925 break;
926 }
927 if (oldreg != env->mmuregs[reg]) {
928 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
929 reg, oldreg, env->mmuregs[reg]);
930 }
931 #ifdef DEBUG_MMU
932 dump_mmu(stdout, fprintf, env);
933 #endif
934 }
935 break;
936 case 5: /* Turbosparc ITLB Diagnostic */
937 case 6: /* Turbosparc DTLB Diagnostic */
938 case 7: /* Turbosparc IOTLB Diagnostic */
939 break;
940 case 0xa: /* User data access */
941 switch (size) {
942 case 1:
943 cpu_stb_user(env, addr, val);
944 break;
945 case 2:
946 cpu_stw_user(env, addr, val);
947 break;
948 default:
949 case 4:
950 cpu_stl_user(env, addr, val);
951 break;
952 case 8:
953 cpu_stq_user(env, addr, val);
954 break;
955 }
956 break;
957 case 0xb: /* Supervisor data access */
958 case 0x80:
959 switch (size) {
960 case 1:
961 cpu_stb_kernel(env, addr, val);
962 break;
963 case 2:
964 cpu_stw_kernel(env, addr, val);
965 break;
966 default:
967 case 4:
968 cpu_stl_kernel(env, addr, val);
969 break;
970 case 8:
971 cpu_stq_kernel(env, addr, val);
972 break;
973 }
974 break;
975 case 0xc: /* I-cache tag */
976 case 0xd: /* I-cache data */
977 case 0xe: /* D-cache tag */
978 case 0xf: /* D-cache data */
979 case 0x10: /* I/D-cache flush page */
980 case 0x11: /* I/D-cache flush segment */
981 case 0x12: /* I/D-cache flush region */
982 case 0x13: /* I/D-cache flush context */
983 case 0x14: /* I/D-cache flush user */
984 break;
985 case 0x17: /* Block copy, sta access */
986 {
987 /* val = src
988 addr = dst
989 copy 32 bytes */
990 unsigned int i;
991 uint32_t src = val & ~3, dst = addr & ~3, temp;
992
993 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
994 temp = cpu_ldl_kernel(env, src);
995 cpu_stl_kernel(env, dst, temp);
996 }
997 }
998 break;
999 case 0x1f: /* Block fill, stda access */
1000 {
1001 /* addr = dst
1002 fill 32 bytes with val */
1003 unsigned int i;
1004 uint32_t dst = addr & 7;
1005
1006 for (i = 0; i < 32; i += 8, dst += 8) {
1007 cpu_stq_kernel(env, dst, val);
1008 }
1009 }
1010 break;
1011 case 0x20: /* MMU passthrough */
1012 case 0x1c: /* LEON MMU passthrough */
1013 {
1014 switch (size) {
1015 case 1:
1016 stb_phys(cs->as, addr, val);
1017 break;
1018 case 2:
1019 stw_phys(cs->as, addr, val);
1020 break;
1021 case 4:
1022 default:
1023 stl_phys(cs->as, addr, val);
1024 break;
1025 case 8:
1026 stq_phys(cs->as, addr, val);
1027 break;
1028 }
1029 }
1030 break;
1031 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1032 {
1033 switch (size) {
1034 case 1:
1035 stb_phys(cs->as, (hwaddr)addr
1036 | ((hwaddr)(asi & 0xf) << 32), val);
1037 break;
1038 case 2:
1039 stw_phys(cs->as, (hwaddr)addr
1040 | ((hwaddr)(asi & 0xf) << 32), val);
1041 break;
1042 case 4:
1043 default:
1044 stl_phys(cs->as, (hwaddr)addr
1045 | ((hwaddr)(asi & 0xf) << 32), val);
1046 break;
1047 case 8:
1048 stq_phys(cs->as, (hwaddr)addr
1049 | ((hwaddr)(asi & 0xf) << 32), val);
1050 break;
1051 }
1052 }
1053 break;
1054 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1055 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1056 Turbosparc snoop RAM */
1057 case 0x32: /* store buffer control or Turbosparc page table
1058 descriptor diagnostic */
1059 case 0x36: /* I-cache flash clear */
1060 case 0x37: /* D-cache flash clear */
1061 break;
1062 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1063 {
1064 int reg = (addr >> 8) & 3;
1065
1066 switch (reg) {
1067 case 0: /* Breakpoint Value (Addr) */
1068 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1069 break;
1070 case 1: /* Breakpoint Mask */
1071 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1072 break;
1073 case 2: /* Breakpoint Control */
1074 env->mmubpregs[reg] = (val & 0x7fULL);
1075 break;
1076 case 3: /* Breakpoint Status */
1077 env->mmubpregs[reg] = (val & 0xfULL);
1078 break;
1079 }
1080 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
1081 env->mmuregs[reg]);
1082 }
1083 break;
1084 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1085 env->mmubpctrv = val & 0xffffffff;
1086 break;
1087 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1088 env->mmubpctrc = val & 0x3;
1089 break;
1090 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1091 env->mmubpctrs = val & 0x3;
1092 break;
1093 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1094 env->mmubpaction = val & 0x1fff;
1095 break;
1096 case 8: /* User code access, XXX */
1097 case 9: /* Supervisor code access, XXX */
1098 default:
1099 cpu_unassigned_access(CPU(sparc_env_get_cpu(env)),
1100 addr, true, false, asi, size);
1101 break;
1102 }
1103 #ifdef DEBUG_ASI
1104 dump_asi("write", addr, asi, size, val);
1105 #endif
1106 }
1107
1108 #endif /* CONFIG_USER_ONLY */
1109 #else /* TARGET_SPARC64 */
1110
1111 #ifdef CONFIG_USER_ONLY
1112 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
1113 int sign)
1114 {
1115 uint64_t ret = 0;
1116 #if defined(DEBUG_ASI)
1117 target_ulong last_addr = addr;
1118 #endif
1119
1120 if (asi < 0x80) {
1121 helper_raise_exception(env, TT_PRIV_ACT);
1122 }
1123
1124 helper_check_align(env, addr, size - 1);
1125 addr = asi_address_mask(env, asi, addr);
1126
1127 switch (asi) {
1128 case 0x82: /* Primary no-fault */
1129 case 0x8a: /* Primary no-fault LE */
1130 if (page_check_range(addr, size, PAGE_READ) == -1) {
1131 #ifdef DEBUG_ASI
1132 dump_asi("read ", last_addr, asi, size, ret);
1133 #endif
1134 return 0;
1135 }
1136 /* Fall through */
1137 case 0x80: /* Primary */
1138 case 0x88: /* Primary LE */
1139 {
1140 switch (size) {
1141 case 1:
1142 ret = ldub_raw(addr);
1143 break;
1144 case 2:
1145 ret = lduw_raw(addr);
1146 break;
1147 case 4:
1148 ret = ldl_raw(addr);
1149 break;
1150 default:
1151 case 8:
1152 ret = ldq_raw(addr);
1153 break;
1154 }
1155 }
1156 break;
1157 case 0x83: /* Secondary no-fault */
1158 case 0x8b: /* Secondary no-fault LE */
1159 if (page_check_range(addr, size, PAGE_READ) == -1) {
1160 #ifdef DEBUG_ASI
1161 dump_asi("read ", last_addr, asi, size, ret);
1162 #endif
1163 return 0;
1164 }
1165 /* Fall through */
1166 case 0x81: /* Secondary */
1167 case 0x89: /* Secondary LE */
1168 /* XXX */
1169 break;
1170 default:
1171 break;
1172 }
1173
1174 /* Convert from little endian */
1175 switch (asi) {
1176 case 0x88: /* Primary LE */
1177 case 0x89: /* Secondary LE */
1178 case 0x8a: /* Primary no-fault LE */
1179 case 0x8b: /* Secondary no-fault LE */
1180 switch (size) {
1181 case 2:
1182 ret = bswap16(ret);
1183 break;
1184 case 4:
1185 ret = bswap32(ret);
1186 break;
1187 case 8:
1188 ret = bswap64(ret);
1189 break;
1190 default:
1191 break;
1192 }
1193 default:
1194 break;
1195 }
1196
1197 /* Convert to signed number */
1198 if (sign) {
1199 switch (size) {
1200 case 1:
1201 ret = (int8_t) ret;
1202 break;
1203 case 2:
1204 ret = (int16_t) ret;
1205 break;
1206 case 4:
1207 ret = (int32_t) ret;
1208 break;
1209 default:
1210 break;
1211 }
1212 }
1213 #ifdef DEBUG_ASI
1214 dump_asi("read ", last_addr, asi, size, ret);
1215 #endif
1216 return ret;
1217 }
1218
1219 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1220 int asi, int size)
1221 {
1222 #ifdef DEBUG_ASI
1223 dump_asi("write", addr, asi, size, val);
1224 #endif
1225 if (asi < 0x80) {
1226 helper_raise_exception(env, TT_PRIV_ACT);
1227 }
1228
1229 helper_check_align(env, addr, size - 1);
1230 addr = asi_address_mask(env, asi, addr);
1231
1232 /* Convert to little endian */
1233 switch (asi) {
1234 case 0x88: /* Primary LE */
1235 case 0x89: /* Secondary LE */
1236 switch (size) {
1237 case 2:
1238 val = bswap16(val);
1239 break;
1240 case 4:
1241 val = bswap32(val);
1242 break;
1243 case 8:
1244 val = bswap64(val);
1245 break;
1246 default:
1247 break;
1248 }
1249 default:
1250 break;
1251 }
1252
1253 switch (asi) {
1254 case 0x80: /* Primary */
1255 case 0x88: /* Primary LE */
1256 {
1257 switch (size) {
1258 case 1:
1259 stb_raw(addr, val);
1260 break;
1261 case 2:
1262 stw_raw(addr, val);
1263 break;
1264 case 4:
1265 stl_raw(addr, val);
1266 break;
1267 case 8:
1268 default:
1269 stq_raw(addr, val);
1270 break;
1271 }
1272 }
1273 break;
1274 case 0x81: /* Secondary */
1275 case 0x89: /* Secondary LE */
1276 /* XXX */
1277 return;
1278
1279 case 0x82: /* Primary no-fault, RO */
1280 case 0x83: /* Secondary no-fault, RO */
1281 case 0x8a: /* Primary no-fault LE, RO */
1282 case 0x8b: /* Secondary no-fault LE, RO */
1283 default:
1284 helper_raise_exception(env, TT_DATA_ACCESS);
1285 return;
1286 }
1287 }
1288
1289 #else /* CONFIG_USER_ONLY */
1290
1291 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
1292 int sign)
1293 {
1294 CPUState *cs = CPU(sparc_env_get_cpu(env));
1295 uint64_t ret = 0;
1296 #if defined(DEBUG_ASI)
1297 target_ulong last_addr = addr;
1298 #endif
1299
1300 asi &= 0xff;
1301
1302 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1303 || (cpu_has_hypervisor(env)
1304 && asi >= 0x30 && asi < 0x80
1305 && !(env->hpstate & HS_PRIV))) {
1306 helper_raise_exception(env, TT_PRIV_ACT);
1307 }
1308
1309 helper_check_align(env, addr, size - 1);
1310 addr = asi_address_mask(env, asi, addr);
1311
1312 /* process nonfaulting loads first */
1313 if ((asi & 0xf6) == 0x82) {
1314 int mmu_idx;
1315
1316 /* secondary space access has lowest asi bit equal to 1 */
1317 if (env->pstate & PS_PRIV) {
1318 mmu_idx = (asi & 1) ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX;
1319 } else {
1320 mmu_idx = (asi & 1) ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX;
1321 }
1322
1323 if (cpu_get_phys_page_nofault(env, addr, mmu_idx) == -1ULL) {
1324 #ifdef DEBUG_ASI
1325 dump_asi("read ", last_addr, asi, size, ret);
1326 #endif
1327 /* env->exception_index is set in get_physical_address_data(). */
1328 helper_raise_exception(env, cs->exception_index);
1329 }
1330
1331 /* convert nonfaulting load ASIs to normal load ASIs */
1332 asi &= ~0x02;
1333 }
1334
1335 switch (asi) {
1336 case 0x10: /* As if user primary */
1337 case 0x11: /* As if user secondary */
1338 case 0x18: /* As if user primary LE */
1339 case 0x19: /* As if user secondary LE */
1340 case 0x80: /* Primary */
1341 case 0x81: /* Secondary */
1342 case 0x88: /* Primary LE */
1343 case 0x89: /* Secondary LE */
1344 case 0xe2: /* UA2007 Primary block init */
1345 case 0xe3: /* UA2007 Secondary block init */
1346 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1347 if (cpu_hypervisor_mode(env)) {
1348 switch (size) {
1349 case 1:
1350 ret = cpu_ldub_hypv(env, addr);
1351 break;
1352 case 2:
1353 ret = cpu_lduw_hypv(env, addr);
1354 break;
1355 case 4:
1356 ret = cpu_ldl_hypv(env, addr);
1357 break;
1358 default:
1359 case 8:
1360 ret = cpu_ldq_hypv(env, addr);
1361 break;
1362 }
1363 } else {
1364 /* secondary space access has lowest asi bit equal to 1 */
1365 if (asi & 1) {
1366 switch (size) {
1367 case 1:
1368 ret = cpu_ldub_kernel_secondary(env, addr);
1369 break;
1370 case 2:
1371 ret = cpu_lduw_kernel_secondary(env, addr);
1372 break;
1373 case 4:
1374 ret = cpu_ldl_kernel_secondary(env, addr);
1375 break;
1376 default:
1377 case 8:
1378 ret = cpu_ldq_kernel_secondary(env, addr);
1379 break;
1380 }
1381 } else {
1382 switch (size) {
1383 case 1:
1384 ret = cpu_ldub_kernel(env, addr);
1385 break;
1386 case 2:
1387 ret = cpu_lduw_kernel(env, addr);
1388 break;
1389 case 4:
1390 ret = cpu_ldl_kernel(env, addr);
1391 break;
1392 default:
1393 case 8:
1394 ret = cpu_ldq_kernel(env, addr);
1395 break;
1396 }
1397 }
1398 }
1399 } else {
1400 /* secondary space access has lowest asi bit equal to 1 */
1401 if (asi & 1) {
1402 switch (size) {
1403 case 1:
1404 ret = cpu_ldub_user_secondary(env, addr);
1405 break;
1406 case 2:
1407 ret = cpu_lduw_user_secondary(env, addr);
1408 break;
1409 case 4:
1410 ret = cpu_ldl_user_secondary(env, addr);
1411 break;
1412 default:
1413 case 8:
1414 ret = cpu_ldq_user_secondary(env, addr);
1415 break;
1416 }
1417 } else {
1418 switch (size) {
1419 case 1:
1420 ret = cpu_ldub_user(env, addr);
1421 break;
1422 case 2:
1423 ret = cpu_lduw_user(env, addr);
1424 break;
1425 case 4:
1426 ret = cpu_ldl_user(env, addr);
1427 break;
1428 default:
1429 case 8:
1430 ret = cpu_ldq_user(env, addr);
1431 break;
1432 }
1433 }
1434 }
1435 break;
1436 case 0x14: /* Bypass */
1437 case 0x15: /* Bypass, non-cacheable */
1438 case 0x1c: /* Bypass LE */
1439 case 0x1d: /* Bypass, non-cacheable LE */
1440 {
1441 switch (size) {
1442 case 1:
1443 ret = ldub_phys(cs->as, addr);
1444 break;
1445 case 2:
1446 ret = lduw_phys(cs->as, addr);
1447 break;
1448 case 4:
1449 ret = ldl_phys(cs->as, addr);
1450 break;
1451 default:
1452 case 8:
1453 ret = ldq_phys(cs->as, addr);
1454 break;
1455 }
1456 break;
1457 }
1458 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1459 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1460 Only ldda allowed */
1461 helper_raise_exception(env, TT_ILL_INSN);
1462 return 0;
1463 case 0x04: /* Nucleus */
1464 case 0x0c: /* Nucleus Little Endian (LE) */
1465 {
1466 switch (size) {
1467 case 1:
1468 ret = cpu_ldub_nucleus(env, addr);
1469 break;
1470 case 2:
1471 ret = cpu_lduw_nucleus(env, addr);
1472 break;
1473 case 4:
1474 ret = cpu_ldl_nucleus(env, addr);
1475 break;
1476 default:
1477 case 8:
1478 ret = cpu_ldq_nucleus(env, addr);
1479 break;
1480 }
1481 break;
1482 }
1483 case 0x4a: /* UPA config */
1484 /* XXX */
1485 break;
1486 case 0x45: /* LSU */
1487 ret = env->lsu;
1488 break;
1489 case 0x50: /* I-MMU regs */
1490 {
1491 int reg = (addr >> 3) & 0xf;
1492
1493 if (reg == 0) {
1494 /* I-TSB Tag Target register */
1495 ret = ultrasparc_tag_target(env->immu.tag_access);
1496 } else {
1497 ret = env->immuregs[reg];
1498 }
1499
1500 break;
1501 }
1502 case 0x51: /* I-MMU 8k TSB pointer */
1503 {
1504 /* env->immuregs[5] holds I-MMU TSB register value
1505 env->immuregs[6] holds I-MMU Tag Access register value */
1506 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1507 8*1024);
1508 break;
1509 }
1510 case 0x52: /* I-MMU 64k TSB pointer */
1511 {
1512 /* env->immuregs[5] holds I-MMU TSB register value
1513 env->immuregs[6] holds I-MMU Tag Access register value */
1514 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1515 64*1024);
1516 break;
1517 }
1518 case 0x55: /* I-MMU data access */
1519 {
1520 int reg = (addr >> 3) & 0x3f;
1521
1522 ret = env->itlb[reg].tte;
1523 break;
1524 }
1525 case 0x56: /* I-MMU tag read */
1526 {
1527 int reg = (addr >> 3) & 0x3f;
1528
1529 ret = env->itlb[reg].tag;
1530 break;
1531 }
1532 case 0x58: /* D-MMU regs */
1533 {
1534 int reg = (addr >> 3) & 0xf;
1535
1536 if (reg == 0) {
1537 /* D-TSB Tag Target register */
1538 ret = ultrasparc_tag_target(env->dmmu.tag_access);
1539 } else {
1540 ret = env->dmmuregs[reg];
1541 }
1542 break;
1543 }
1544 case 0x59: /* D-MMU 8k TSB pointer */
1545 {
1546 /* env->dmmuregs[5] holds D-MMU TSB register value
1547 env->dmmuregs[6] holds D-MMU Tag Access register value */
1548 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1549 8*1024);
1550 break;
1551 }
1552 case 0x5a: /* D-MMU 64k TSB pointer */
1553 {
1554 /* env->dmmuregs[5] holds D-MMU TSB register value
1555 env->dmmuregs[6] holds D-MMU Tag Access register value */
1556 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1557 64*1024);
1558 break;
1559 }
1560 case 0x5d: /* D-MMU data access */
1561 {
1562 int reg = (addr >> 3) & 0x3f;
1563
1564 ret = env->dtlb[reg].tte;
1565 break;
1566 }
1567 case 0x5e: /* D-MMU tag read */
1568 {
1569 int reg = (addr >> 3) & 0x3f;
1570
1571 ret = env->dtlb[reg].tag;
1572 break;
1573 }
1574 case 0x48: /* Interrupt dispatch, RO */
1575 break;
1576 case 0x49: /* Interrupt data receive */
1577 ret = env->ivec_status;
1578 break;
1579 case 0x7f: /* Incoming interrupt vector, RO */
1580 {
1581 int reg = (addr >> 4) & 0x3;
1582 if (reg < 3) {
1583 ret = env->ivec_data[reg];
1584 }
1585 break;
1586 }
1587 case 0x46: /* D-cache data */
1588 case 0x47: /* D-cache tag access */
1589 case 0x4b: /* E-cache error enable */
1590 case 0x4c: /* E-cache asynchronous fault status */
1591 case 0x4d: /* E-cache asynchronous fault address */
1592 case 0x4e: /* E-cache tag data */
1593 case 0x66: /* I-cache instruction access */
1594 case 0x67: /* I-cache tag access */
1595 case 0x6e: /* I-cache predecode */
1596 case 0x6f: /* I-cache LRU etc. */
1597 case 0x76: /* E-cache tag */
1598 case 0x7e: /* E-cache tag */
1599 break;
1600 case 0x5b: /* D-MMU data pointer */
1601 case 0x54: /* I-MMU data in, WO */
1602 case 0x57: /* I-MMU demap, WO */
1603 case 0x5c: /* D-MMU data in, WO */
1604 case 0x5f: /* D-MMU demap, WO */
1605 case 0x77: /* Interrupt vector, WO */
1606 default:
1607 cpu_unassigned_access(cs, addr, false, false, 1, size);
1608 ret = 0;
1609 break;
1610 }
1611
1612 /* Convert from little endian */
1613 switch (asi) {
1614 case 0x0c: /* Nucleus Little Endian (LE) */
1615 case 0x18: /* As if user primary LE */
1616 case 0x19: /* As if user secondary LE */
1617 case 0x1c: /* Bypass LE */
1618 case 0x1d: /* Bypass, non-cacheable LE */
1619 case 0x88: /* Primary LE */
1620 case 0x89: /* Secondary LE */
1621 switch(size) {
1622 case 2:
1623 ret = bswap16(ret);
1624 break;
1625 case 4:
1626 ret = bswap32(ret);
1627 break;
1628 case 8:
1629 ret = bswap64(ret);
1630 break;
1631 default:
1632 break;
1633 }
1634 default:
1635 break;
1636 }
1637
1638 /* Convert to signed number */
1639 if (sign) {
1640 switch (size) {
1641 case 1:
1642 ret = (int8_t) ret;
1643 break;
1644 case 2:
1645 ret = (int16_t) ret;
1646 break;
1647 case 4:
1648 ret = (int32_t) ret;
1649 break;
1650 default:
1651 break;
1652 }
1653 }
1654 #ifdef DEBUG_ASI
1655 dump_asi("read ", last_addr, asi, size, ret);
1656 #endif
1657 return ret;
1658 }
1659
1660 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1661 int asi, int size)
1662 {
1663 SPARCCPU *cpu = sparc_env_get_cpu(env);
1664 CPUState *cs = CPU(cpu);
1665
1666 #ifdef DEBUG_ASI
1667 dump_asi("write", addr, asi, size, val);
1668 #endif
1669
1670 asi &= 0xff;
1671
1672 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1673 || (cpu_has_hypervisor(env)
1674 && asi >= 0x30 && asi < 0x80
1675 && !(env->hpstate & HS_PRIV))) {
1676 helper_raise_exception(env, TT_PRIV_ACT);
1677 }
1678
1679 helper_check_align(env, addr, size - 1);
1680 addr = asi_address_mask(env, asi, addr);
1681
1682 /* Convert to little endian */
1683 switch (asi) {
1684 case 0x0c: /* Nucleus Little Endian (LE) */
1685 case 0x18: /* As if user primary LE */
1686 case 0x19: /* As if user secondary LE */
1687 case 0x1c: /* Bypass LE */
1688 case 0x1d: /* Bypass, non-cacheable LE */
1689 case 0x88: /* Primary LE */
1690 case 0x89: /* Secondary LE */
1691 switch (size) {
1692 case 2:
1693 val = bswap16(val);
1694 break;
1695 case 4:
1696 val = bswap32(val);
1697 break;
1698 case 8:
1699 val = bswap64(val);
1700 break;
1701 default:
1702 break;
1703 }
1704 default:
1705 break;
1706 }
1707
1708 switch (asi) {
1709 case 0x10: /* As if user primary */
1710 case 0x11: /* As if user secondary */
1711 case 0x18: /* As if user primary LE */
1712 case 0x19: /* As if user secondary LE */
1713 case 0x80: /* Primary */
1714 case 0x81: /* Secondary */
1715 case 0x88: /* Primary LE */
1716 case 0x89: /* Secondary LE */
1717 case 0xe2: /* UA2007 Primary block init */
1718 case 0xe3: /* UA2007 Secondary block init */
1719 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1720 if (cpu_hypervisor_mode(env)) {
1721 switch (size) {
1722 case 1:
1723 cpu_stb_hypv(env, addr, val);
1724 break;
1725 case 2:
1726 cpu_stw_hypv(env, addr, val);
1727 break;
1728 case 4:
1729 cpu_stl_hypv(env, addr, val);
1730 break;
1731 case 8:
1732 default:
1733 cpu_stq_hypv(env, addr, val);
1734 break;
1735 }
1736 } else {
1737 /* secondary space access has lowest asi bit equal to 1 */
1738 if (asi & 1) {
1739 switch (size) {
1740 case 1:
1741 cpu_stb_kernel_secondary(env, addr, val);
1742 break;
1743 case 2:
1744 cpu_stw_kernel_secondary(env, addr, val);
1745 break;
1746 case 4:
1747 cpu_stl_kernel_secondary(env, addr, val);
1748 break;
1749 case 8:
1750 default:
1751 cpu_stq_kernel_secondary(env, addr, val);
1752 break;
1753 }
1754 } else {
1755 switch (size) {
1756 case 1:
1757 cpu_stb_kernel(env, addr, val);
1758 break;
1759 case 2:
1760 cpu_stw_kernel(env, addr, val);
1761 break;
1762 case 4:
1763 cpu_stl_kernel(env, addr, val);
1764 break;
1765 case 8:
1766 default:
1767 cpu_stq_kernel(env, addr, val);
1768 break;
1769 }
1770 }
1771 }
1772 } else {
1773 /* secondary space access has lowest asi bit equal to 1 */
1774 if (asi & 1) {
1775 switch (size) {
1776 case 1:
1777 cpu_stb_user_secondary(env, addr, val);
1778 break;
1779 case 2:
1780 cpu_stw_user_secondary(env, addr, val);
1781 break;
1782 case 4:
1783 cpu_stl_user_secondary(env, addr, val);
1784 break;
1785 case 8:
1786 default:
1787 cpu_stq_user_secondary(env, addr, val);
1788 break;
1789 }
1790 } else {
1791 switch (size) {
1792 case 1:
1793 cpu_stb_user(env, addr, val);
1794 break;
1795 case 2:
1796 cpu_stw_user(env, addr, val);
1797 break;
1798 case 4:
1799 cpu_stl_user(env, addr, val);
1800 break;
1801 case 8:
1802 default:
1803 cpu_stq_user(env, addr, val);
1804 break;
1805 }
1806 }
1807 }
1808 break;
1809 case 0x14: /* Bypass */
1810 case 0x15: /* Bypass, non-cacheable */
1811 case 0x1c: /* Bypass LE */
1812 case 0x1d: /* Bypass, non-cacheable LE */
1813 {
1814 switch (size) {
1815 case 1:
1816 stb_phys(cs->as, addr, val);
1817 break;
1818 case 2:
1819 stw_phys(cs->as, addr, val);
1820 break;
1821 case 4:
1822 stl_phys(cs->as, addr, val);
1823 break;
1824 case 8:
1825 default:
1826 stq_phys(cs->as, addr, val);
1827 break;
1828 }
1829 }
1830 return;
1831 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1832 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1833 Only ldda allowed */
1834 helper_raise_exception(env, TT_ILL_INSN);
1835 return;
1836 case 0x04: /* Nucleus */
1837 case 0x0c: /* Nucleus Little Endian (LE) */
1838 {
1839 switch (size) {
1840 case 1:
1841 cpu_stb_nucleus(env, addr, val);
1842 break;
1843 case 2:
1844 cpu_stw_nucleus(env, addr, val);
1845 break;
1846 case 4:
1847 cpu_stl_nucleus(env, addr, val);
1848 break;
1849 default:
1850 case 8:
1851 cpu_stq_nucleus(env, addr, val);
1852 break;
1853 }
1854 break;
1855 }
1856
1857 case 0x4a: /* UPA config */
1858 /* XXX */
1859 return;
1860 case 0x45: /* LSU */
1861 {
1862 uint64_t oldreg;
1863
1864 oldreg = env->lsu;
1865 env->lsu = val & (DMMU_E | IMMU_E);
1866 /* Mappings generated during D/I MMU disabled mode are
1867 invalid in normal mode */
1868 if (oldreg != env->lsu) {
1869 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
1870 oldreg, env->lsu);
1871 #ifdef DEBUG_MMU
1872 dump_mmu(stdout, fprintf, env);
1873 #endif
1874 tlb_flush(CPU(cpu), 1);
1875 }
1876 return;
1877 }
1878 case 0x50: /* I-MMU regs */
1879 {
1880 int reg = (addr >> 3) & 0xf;
1881 uint64_t oldreg;
1882
1883 oldreg = env->immuregs[reg];
1884 switch (reg) {
1885 case 0: /* RO */
1886 return;
1887 case 1: /* Not in I-MMU */
1888 case 2:
1889 return;
1890 case 3: /* SFSR */
1891 if ((val & 1) == 0) {
1892 val = 0; /* Clear SFSR */
1893 }
1894 env->immu.sfsr = val;
1895 break;
1896 case 4: /* RO */
1897 return;
1898 case 5: /* TSB access */
1899 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
1900 PRIx64 "\n", env->immu.tsb, val);
1901 env->immu.tsb = val;
1902 break;
1903 case 6: /* Tag access */
1904 env->immu.tag_access = val;
1905 break;
1906 case 7:
1907 case 8:
1908 return;
1909 default:
1910 break;
1911 }
1912
1913 if (oldreg != env->immuregs[reg]) {
1914 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1915 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1916 }
1917 #ifdef DEBUG_MMU
1918 dump_mmu(stdout, fprintf, env);
1919 #endif
1920 return;
1921 }
1922 case 0x54: /* I-MMU data in */
1923 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
1924 return;
1925 case 0x55: /* I-MMU data access */
1926 {
1927 /* TODO: auto demap */
1928
1929 unsigned int i = (addr >> 3) & 0x3f;
1930
1931 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env);
1932
1933 #ifdef DEBUG_MMU
1934 DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
1935 dump_mmu(stdout, fprintf, env);
1936 #endif
1937 return;
1938 }
1939 case 0x57: /* I-MMU demap */
1940 demap_tlb(env->itlb, addr, "immu", env);
1941 return;
1942 case 0x58: /* D-MMU regs */
1943 {
1944 int reg = (addr >> 3) & 0xf;
1945 uint64_t oldreg;
1946
1947 oldreg = env->dmmuregs[reg];
1948 switch (reg) {
1949 case 0: /* RO */
1950 case 4:
1951 return;
1952 case 3: /* SFSR */
1953 if ((val & 1) == 0) {
1954 val = 0; /* Clear SFSR, Fault address */
1955 env->dmmu.sfar = 0;
1956 }
1957 env->dmmu.sfsr = val;
1958 break;
1959 case 1: /* Primary context */
1960 env->dmmu.mmu_primary_context = val;
1961 /* can be optimized to only flush MMU_USER_IDX
1962 and MMU_KERNEL_IDX entries */
1963 tlb_flush(CPU(cpu), 1);
1964 break;
1965 case 2: /* Secondary context */
1966 env->dmmu.mmu_secondary_context = val;
1967 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1968 and MMU_KERNEL_SECONDARY_IDX entries */
1969 tlb_flush(CPU(cpu), 1);
1970 break;
1971 case 5: /* TSB access */
1972 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
1973 PRIx64 "\n", env->dmmu.tsb, val);
1974 env->dmmu.tsb = val;
1975 break;
1976 case 6: /* Tag access */
1977 env->dmmu.tag_access = val;
1978 break;
1979 case 7: /* Virtual Watchpoint */
1980 case 8: /* Physical Watchpoint */
1981 default:
1982 env->dmmuregs[reg] = val;
1983 break;
1984 }
1985
1986 if (oldreg != env->dmmuregs[reg]) {
1987 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1988 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1989 }
1990 #ifdef DEBUG_MMU
1991 dump_mmu(stdout, fprintf, env);
1992 #endif
1993 return;
1994 }
1995 case 0x5c: /* D-MMU data in */
1996 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
1997 return;
1998 case 0x5d: /* D-MMU data access */
1999 {
2000 unsigned int i = (addr >> 3) & 0x3f;
2001
2002 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env);
2003
2004 #ifdef DEBUG_MMU
2005 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
2006 dump_mmu(stdout, fprintf, env);
2007 #endif
2008 return;
2009 }
2010 case 0x5f: /* D-MMU demap */
2011 demap_tlb(env->dtlb, addr, "dmmu", env);
2012 return;
2013 case 0x49: /* Interrupt data receive */
2014 env->ivec_status = val & 0x20;
2015 return;
2016 case 0x46: /* D-cache data */
2017 case 0x47: /* D-cache tag access */
2018 case 0x4b: /* E-cache error enable */
2019 case 0x4c: /* E-cache asynchronous fault status */
2020 case 0x4d: /* E-cache asynchronous fault address */
2021 case 0x4e: /* E-cache tag data */
2022 case 0x66: /* I-cache instruction access */
2023 case 0x67: /* I-cache tag access */
2024 case 0x6e: /* I-cache predecode */
2025 case 0x6f: /* I-cache LRU etc. */
2026 case 0x76: /* E-cache tag */
2027 case 0x7e: /* E-cache tag */
2028 return;
2029 case 0x51: /* I-MMU 8k TSB pointer, RO */
2030 case 0x52: /* I-MMU 64k TSB pointer, RO */
2031 case 0x56: /* I-MMU tag read, RO */
2032 case 0x59: /* D-MMU 8k TSB pointer, RO */
2033 case 0x5a: /* D-MMU 64k TSB pointer, RO */
2034 case 0x5b: /* D-MMU data pointer, RO */
2035 case 0x5e: /* D-MMU tag read, RO */
2036 case 0x48: /* Interrupt dispatch, RO */
2037 case 0x7f: /* Incoming interrupt vector, RO */
2038 case 0x82: /* Primary no-fault, RO */
2039 case 0x83: /* Secondary no-fault, RO */
2040 case 0x8a: /* Primary no-fault LE, RO */
2041 case 0x8b: /* Secondary no-fault LE, RO */
2042 default:
2043 cpu_unassigned_access(cs, addr, true, false, 1, size);
2044 return;
2045 }
2046 }
2047 #endif /* CONFIG_USER_ONLY */
2048
2049 void helper_ldda_asi(CPUSPARCState *env, target_ulong addr, int asi, int rd)
2050 {
2051 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2052 || (cpu_has_hypervisor(env)
2053 && asi >= 0x30 && asi < 0x80
2054 && !(env->hpstate & HS_PRIV))) {
2055 helper_raise_exception(env, TT_PRIV_ACT);
2056 }
2057
2058 addr = asi_address_mask(env, asi, addr);
2059
2060 switch (asi) {
2061 #if !defined(CONFIG_USER_ONLY)
2062 case 0x24: /* Nucleus quad LDD 128 bit atomic */
2063 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE */
2064 helper_check_align(env, addr, 0xf);
2065 if (rd == 0) {
2066 env->gregs[1] = cpu_ldq_nucleus(env, addr + 8);
2067 if (asi == 0x2c) {
2068 bswap64s(&env->gregs[1]);
2069 }
2070 } else if (rd < 8) {
2071 env->gregs[rd] = cpu_ldq_nucleus(env, addr);
2072 env->gregs[rd + 1] = cpu_ldq_nucleus(env, addr + 8);
2073 if (asi == 0x2c) {
2074 bswap64s(&env->gregs[rd]);
2075 bswap64s(&env->gregs[rd + 1]);
2076 }
2077 } else {
2078 env->regwptr[rd] = cpu_ldq_nucleus(env, addr);
2079 env->regwptr[rd + 1] = cpu_ldq_nucleus(env, addr + 8);
2080 if (asi == 0x2c) {
2081 bswap64s(&env->regwptr[rd]);
2082 bswap64s(&env->regwptr[rd + 1]);
2083 }
2084 }
2085 break;
2086 #endif
2087 default:
2088 helper_check_align(env, addr, 0x3);
2089 if (rd == 0) {
2090 env->gregs[1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2091 } else if (rd < 8) {
2092 env->gregs[rd] = helper_ld_asi(env, addr, asi, 4, 0);
2093 env->gregs[rd + 1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2094 } else {
2095 env->regwptr[rd] = helper_ld_asi(env, addr, asi, 4, 0);
2096 env->regwptr[rd + 1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2097 }
2098 break;
2099 }
2100 }
2101
2102 void helper_ldf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
2103 int rd)
2104 {
2105 unsigned int i;
2106 target_ulong val;
2107
2108 helper_check_align(env, addr, 3);
2109 addr = asi_address_mask(env, asi, addr);
2110
2111 switch (asi) {
2112 case 0xf0: /* UA2007/JPS1 Block load primary */
2113 case 0xf1: /* UA2007/JPS1 Block load secondary */
2114 case 0xf8: /* UA2007/JPS1 Block load primary LE */
2115 case 0xf9: /* UA2007/JPS1 Block load secondary LE */
2116 if (rd & 7) {
2117 helper_raise_exception(env, TT_ILL_INSN);
2118 return;
2119 }
2120 helper_check_align(env, addr, 0x3f);
2121 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2122 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x8f, 8, 0);
2123 }
2124 return;
2125
2126 case 0x16: /* UA2007 Block load primary, user privilege */
2127 case 0x17: /* UA2007 Block load secondary, user privilege */
2128 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2129 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2130 case 0x70: /* JPS1 Block load primary, user privilege */
2131 case 0x71: /* JPS1 Block load secondary, user privilege */
2132 case 0x78: /* JPS1 Block load primary LE, user privilege */
2133 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2134 if (rd & 7) {
2135 helper_raise_exception(env, TT_ILL_INSN);
2136 return;
2137 }
2138 helper_check_align(env, addr, 0x3f);
2139 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2140 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x19, 8, 0);
2141 }
2142 return;
2143
2144 default:
2145 break;
2146 }
2147
2148 switch (size) {
2149 default:
2150 case 4:
2151 val = helper_ld_asi(env, addr, asi, size, 0);
2152 if (rd & 1) {
2153 env->fpr[rd / 2].l.lower = val;
2154 } else {
2155 env->fpr[rd / 2].l.upper = val;
2156 }
2157 break;
2158 case 8:
2159 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, size, 0);
2160 break;
2161 case 16:
2162 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, 8, 0);
2163 env->fpr[rd / 2 + 1].ll = helper_ld_asi(env, addr + 8, asi, 8, 0);
2164 break;
2165 }
2166 }
2167
2168 void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
2169 int rd)
2170 {
2171 unsigned int i;
2172 target_ulong val;
2173
2174 helper_check_align(env, addr, 3);
2175 addr = asi_address_mask(env, asi, addr);
2176
2177 switch (asi) {
2178 case 0xe0: /* UA2007/JPS1 Block commit store primary (cache flush) */
2179 case 0xe1: /* UA2007/JPS1 Block commit store secondary (cache flush) */
2180 case 0xf0: /* UA2007/JPS1 Block store primary */
2181 case 0xf1: /* UA2007/JPS1 Block store secondary */
2182 case 0xf8: /* UA2007/JPS1 Block store primary LE */
2183 case 0xf9: /* UA2007/JPS1 Block store secondary LE */
2184 if (rd & 7) {
2185 helper_raise_exception(env, TT_ILL_INSN);
2186 return;
2187 }
2188 helper_check_align(env, addr, 0x3f);
2189 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2190 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x8f, 8);
2191 }
2192
2193 return;
2194 case 0x16: /* UA2007 Block load primary, user privilege */
2195 case 0x17: /* UA2007 Block load secondary, user privilege */
2196 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2197 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2198 case 0x70: /* JPS1 Block store primary, user privilege */
2199 case 0x71: /* JPS1 Block store secondary, user privilege */
2200 case 0x78: /* JPS1 Block load primary LE, user privilege */
2201 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2202 if (rd & 7) {
2203 helper_raise_exception(env, TT_ILL_INSN);
2204 return;
2205 }
2206 helper_check_align(env, addr, 0x3f);
2207 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2208 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x19, 8);
2209 }
2210
2211 return;
2212 default:
2213 break;
2214 }
2215
2216 switch (size) {
2217 default:
2218 case 4:
2219 if (rd & 1) {
2220 val = env->fpr[rd / 2].l.lower;
2221 } else {
2222 val = env->fpr[rd / 2].l.upper;
2223 }
2224 helper_st_asi(env, addr, val, asi, size);
2225 break;
2226 case 8:
2227 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, size);
2228 break;
2229 case 16:
2230 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, 8);
2231 helper_st_asi(env, addr + 8, env->fpr[rd / 2 + 1].ll, asi, 8);
2232 break;
2233 }
2234 }
2235
2236 target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr,
2237 target_ulong val1, target_ulong val2,
2238 uint32_t asi)
2239 {
2240 target_ulong ret;
2241
2242 ret = helper_ld_asi(env, addr, asi, 8, 0);
2243 if (val2 == ret) {
2244 helper_st_asi(env, addr, val1, asi, 8);
2245 }
2246 return ret;
2247 }
2248 #endif /* TARGET_SPARC64 */
2249
2250 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2251 target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr,
2252 target_ulong val1, target_ulong val2, uint32_t asi)
2253 {
2254 target_ulong ret;
2255
2256 val2 &= 0xffffffffUL;
2257 ret = helper_ld_asi(env, addr, asi, 4, 0);
2258 ret &= 0xffffffffUL;
2259 if (val2 == ret) {
2260 helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4);
2261 }
2262 return ret;
2263 }
2264 #endif /* !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) */
2265
2266 void helper_ldqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
2267 {
2268 /* XXX add 128 bit load */
2269 CPU_QuadU u;
2270
2271 helper_check_align(env, addr, 7);
2272 #if !defined(CONFIG_USER_ONLY)
2273 switch (mem_idx) {
2274 case MMU_USER_IDX:
2275 u.ll.upper = cpu_ldq_user(env, addr);
2276 u.ll.lower = cpu_ldq_user(env, addr + 8);
2277 QT0 = u.q;
2278 break;
2279 case MMU_KERNEL_IDX:
2280 u.ll.upper = cpu_ldq_kernel(env, addr);
2281 u.ll.lower = cpu_ldq_kernel(env, addr + 8);
2282 QT0 = u.q;
2283 break;
2284 #ifdef TARGET_SPARC64
2285 case MMU_HYPV_IDX:
2286 u.ll.upper = cpu_ldq_hypv(env, addr);
2287 u.ll.lower = cpu_ldq_hypv(env, addr + 8);
2288 QT0 = u.q;
2289 break;
2290 #endif
2291 default:
2292 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx);
2293 break;
2294 }
2295 #else
2296 u.ll.upper = ldq_raw(address_mask(env, addr));
2297 u.ll.lower = ldq_raw(address_mask(env, addr + 8));
2298 QT0 = u.q;
2299 #endif
2300 }
2301
2302 void helper_stqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
2303 {
2304 /* XXX add 128 bit store */
2305 CPU_QuadU u;
2306
2307 helper_check_align(env, addr, 7);
2308 #if !defined(CONFIG_USER_ONLY)
2309 switch (mem_idx) {
2310 case MMU_USER_IDX:
2311 u.q = QT0;
2312 cpu_stq_user(env, addr, u.ll.upper);
2313 cpu_stq_user(env, addr + 8, u.ll.lower);
2314 break;
2315 case MMU_KERNEL_IDX:
2316 u.q = QT0;
2317 cpu_stq_kernel(env, addr, u.ll.upper);
2318 cpu_stq_kernel(env, addr + 8, u.ll.lower);
2319 break;
2320 #ifdef TARGET_SPARC64
2321 case MMU_HYPV_IDX:
2322 u.q = QT0;
2323 cpu_stq_hypv(env, addr, u.ll.upper);
2324 cpu_stq_hypv(env, addr + 8, u.ll.lower);
2325 break;
2326 #endif
2327 default:
2328 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx);
2329 break;
2330 }
2331 #else
2332 u.q = QT0;
2333 stq_raw(address_mask(env, addr), u.ll.upper);
2334 stq_raw(address_mask(env, addr + 8), u.ll.lower);
2335 #endif
2336 }
2337
2338 #if !defined(CONFIG_USER_ONLY)
2339 #ifndef TARGET_SPARC64
2340 void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2341 bool is_write, bool is_exec, int is_asi,
2342 unsigned size)
2343 {
2344 SPARCCPU *cpu = SPARC_CPU(cs);
2345 CPUSPARCState *env = &cpu->env;
2346 int fault_type;
2347
2348 #ifdef DEBUG_UNASSIGNED
2349 if (is_asi) {
2350 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2351 " asi 0x%02x from " TARGET_FMT_lx "\n",
2352 is_exec ? "exec" : is_write ? "write" : "read", size,
2353 size == 1 ? "" : "s", addr, is_asi, env->pc);
2354 } else {
2355 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2356 " from " TARGET_FMT_lx "\n",
2357 is_exec ? "exec" : is_write ? "write" : "read", size,
2358 size == 1 ? "" : "s", addr, env->pc);
2359 }
2360 #endif
2361 /* Don't overwrite translation and access faults */
2362 fault_type = (env->mmuregs[3] & 0x1c) >> 2;
2363 if ((fault_type > 4) || (fault_type == 0)) {
2364 env->mmuregs[3] = 0; /* Fault status register */
2365 if (is_asi) {
2366 env->mmuregs[3] |= 1 << 16;
2367 }
2368 if (env->psrs) {
2369 env->mmuregs[3] |= 1 << 5;
2370 }
2371 if (is_exec) {
2372 env->mmuregs[3] |= 1 << 6;
2373 }
2374 if (is_write) {
2375 env->mmuregs[3] |= 1 << 7;
2376 }
2377 env->mmuregs[3] |= (5 << 2) | 2;
2378 /* SuperSPARC will never place instruction fault addresses in the FAR */
2379 if (!is_exec) {
2380 env->mmuregs[4] = addr; /* Fault address register */
2381 }
2382 }
2383 /* overflow (same type fault was not read before another fault) */
2384 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) {
2385 env->mmuregs[3] |= 1;
2386 }
2387
2388 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
2389 if (is_exec) {
2390 helper_raise_exception(env, TT_CODE_ACCESS);
2391 } else {
2392 helper_raise_exception(env, TT_DATA_ACCESS);
2393 }
2394 }
2395
2396 /* flush neverland mappings created during no-fault mode,
2397 so the sequential MMU faults report proper fault types */
2398 if (env->mmuregs[0] & MMU_NF) {
2399 tlb_flush(cs, 1);
2400 }
2401 }
2402 #else
2403 void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2404 bool is_write, bool is_exec, int is_asi,
2405 unsigned size)
2406 {
2407 SPARCCPU *cpu = SPARC_CPU(cs);
2408 CPUSPARCState *env = &cpu->env;
2409
2410 #ifdef DEBUG_UNASSIGNED
2411 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
2412 "\n", addr, env->pc);
2413 #endif
2414
2415 if (is_exec) {
2416 helper_raise_exception(env, TT_CODE_ACCESS);
2417 } else {
2418 helper_raise_exception(env, TT_DATA_ACCESS);
2419 }
2420 }
2421 #endif
2422 #endif
2423
2424 #if !defined(CONFIG_USER_ONLY)
2425 void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs,
2426 vaddr addr, int is_write,
2427 int is_user, uintptr_t retaddr)
2428 {
2429 SPARCCPU *cpu = SPARC_CPU(cs);
2430 CPUSPARCState *env = &cpu->env;
2431
2432 #ifdef DEBUG_UNALIGNED
2433 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
2434 "\n", addr, env->pc);
2435 #endif
2436 if (retaddr) {
2437 cpu_restore_state(CPU(cpu), retaddr);
2438 }
2439 helper_raise_exception(env, TT_UNALIGNED);
2440 }
2441
2442 /* try to fill the TLB and return an exception if error. If retaddr is
2443 NULL, it means that the function was called in C code (i.e. not
2444 from generated code or from helper.c) */
2445 /* XXX: fix it to restore all registers */
2446 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2447 uintptr_t retaddr)
2448 {
2449 int ret;
2450
2451 ret = sparc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2452 if (ret) {
2453 if (retaddr) {
2454 cpu_restore_state(cs, retaddr);
2455 }
2456 cpu_loop_exit(cs);
2457 }
2458 }
2459 #endif
Mirror of https://git.qemu.org/git/qemu.git