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target-tricore: Add instructions of RCR opcode format
[thirdparty/qemu.git] / target-tricore / tricore-opcodes.h
1 /*
2 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
3 *
4 * This library is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU Lesser General Public
6 * License as published by the Free Software Foundation; either
7 * version 2 of the License, or (at your option) any later version.
8 *
9 * This library is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * Lesser General Public License for more details.
13 *
14 * You should have received a copy of the GNU Lesser General Public
15 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
16 */
17
18 /*
19 * Opcode Masks for Tricore
20 * Format MASK_OP_InstrFormatName_Field
21 */
22
23 /* This creates a mask with bits start .. end set to 1 and applies it to op */
24 #define MASK_BITS_SHIFT(op, start, end) (extract32(op, (start), \
25 (end) - (start) + 1))
26 #define MASK_BITS_SHIFT_SEXT(op, start, end) (sextract32(op, (start),\
27 (end) - (start) + 1))
28
29 /* new opcode masks */
30
31 #define MASK_OP_MAJOR(op) MASK_BITS_SHIFT(op, 0, 7)
32
33 /* 16-Bit Formats */
34 #define MASK_OP_SB_DISP8(op) MASK_BITS_SHIFT(op, 8, 15)
35 #define MASK_OP_SB_DISP8_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 8, 15)
36
37 #define MASK_OP_SBC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
38 #define MASK_OP_SBC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
39 #define MASK_OP_SBC_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
40
41 #define MASK_OP_SBR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
42 #define MASK_OP_SBR_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
43
44 #define MASK_OP_SBRN_N(op) MASK_BITS_SHIFT(op, 12, 15)
45 #define MASK_OP_SBRN_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
46
47 #define MASK_OP_SC_CONST8(op) MASK_BITS_SHIFT(op, 8, 15)
48
49 #define MASK_OP_SLR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
50 #define MASK_OP_SLR_D(op) MASK_BITS_SHIFT(op, 8, 11)
51
52 #define MASK_OP_SLRO_OFF4(op) MASK_BITS_SHIFT(op, 12, 15)
53 #define MASK_OP_SLRO_D(op) MASK_BITS_SHIFT(op, 8, 11)
54
55 #define MASK_OP_SR_OP2(op) MASK_BITS_SHIFT(op, 12, 15)
56 #define MASK_OP_SR_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
57
58 #define MASK_OP_SRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
59 #define MASK_OP_SRC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
60 #define MASK_OP_SRC_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
61
62 #define MASK_OP_SRO_S2(op) MASK_BITS_SHIFT(op, 12, 15)
63 #define MASK_OP_SRO_OFF4(op) MASK_BITS_SHIFT(op, 8, 11)
64
65 #define MASK_OP_SRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
66 #define MASK_OP_SRR_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
67
68 #define MASK_OP_SRRS_S2(op) MASK_BITS_SHIFT(op, 12, 15)
69 #define MASK_OP_SRRS_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
70 #define MASK_OP_SRRS_N(op) MASK_BITS_SHIFT(op, 6, 7)
71
72 #define MASK_OP_SSR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
73 #define MASK_OP_SSR_S1(op) MASK_BITS_SHIFT(op, 8, 11)
74
75 #define MASK_OP_SSRO_OFF4(op) MASK_BITS_SHIFT(op, 12, 15)
76 #define MASK_OP_SSRO_S1(op) MASK_BITS_SHIFT(op, 8, 11)
77
78 /* 32-Bit Formats */
79
80 /* ABS Format */
81 #define MASK_OP_ABS_OFF18(op) (MASK_BITS_SHIFT(op, 16, 21) + \
82 (MASK_BITS_SHIFT(op, 28, 31) << 6) + \
83 (MASK_BITS_SHIFT(op, 22, 25) << 10) +\
84 (MASK_BITS_SHIFT(op, 12, 15) << 14))
85 #define MASK_OP_ABS_OP2(op) MASK_BITS_SHIFT(op, 26, 27)
86 #define MASK_OP_ABS_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
87
88 /* ABSB Format */
89 #define MASK_OP_ABSB_OFF18(op) MASK_OP_ABS_OFF18(op)
90 #define MASK_OP_ABSB_OP2(op) MASK_BITS_SHIFT(op, 26, 27)
91 #define MASK_OP_ABSB_B(op) MASK_BITS_SHIFT(op, 11, 11)
92 #define MASK_OP_ABSB_BPOS(op) MASK_BITS_SHIFT(op, 8, 10)
93
94 /* B Format */
95 #define MASK_OP_B_DISP24(op) (MASK_BITS_SHIFT(op, 16, 31) + \
96 (MASK_BITS_SHIFT(op, 8, 15) << 16))
97 /* BIT Format */
98 #define MASK_OP_BIT_D(op) MASK_BITS_SHIFT(op, 28, 31)
99 #define MASK_OP_BIT_POS2(op) MASK_BITS_SHIFT(op, 23, 27)
100 #define MASK_OP_BIT_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
101 #define MASK_OP_BIT_POS1(op) MASK_BITS_SHIFT(op, 16, 20)
102 #define MASK_OP_BIT_S2(op) MASK_BITS_SHIFT(op, 12, 15)
103 #define MASK_OP_BIT_S1(op) MASK_BITS_SHIFT(op, 8, 11)
104
105 /* BO Format */
106 #define MASK_OP_BO_OFF10(op) (MASK_BITS_SHIFT(op, 16, 21) + \
107 (MASK_BITS_SHIFT(op, 28, 31) << 6))
108 #define MASK_OP_BO_OFF10_SEXT(op) (MASK_BITS_SHIFT_SEXT(op, 16, 21) + \
109 (MASK_BITS_SHIFT_SEXT(op, 28, 31) << 6))
110 #define MASK_OP_BO_OP2(op) MASK_BITS_SHIFT(op, 22, 27)
111 #define MASK_OP_BO_S2(op) MASK_BITS_SHIFT(op, 12, 15)
112 #define MASK_OP_BO_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
113
114 /* BOL Format */
115 #define MASK_OP_BOL_OFF16(op) ((MASK_BITS_SHIFT(op, 16, 21) + \
116 (MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
117 (MASK_BITS_SHIFT(op, 22, 27) >> 10))
118 #define MASK_OP_BOL_OFF16_SEXT(op) ((MASK_BITS_SHIFT(op, 16, 21) + \
119 (MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
120 (MASK_BITS_SHIFT_SEXT(op, 22, 27) << 10))
121 #define MASK_OP_BOL_S2(op) MASK_BITS_SHIFT(op, 12, 15)
122 #define MASK_OP_BOL_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
123
124 /* BRC Format */
125 #define MASK_OP_BRC_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
126 #define MASK_OP_BRC_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
127 #define MASK_OP_BRC_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30)
128 #define MASK_OP_BRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
129 #define MASK_OP_BRC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
130 #define MASK_OP_BRC_S1(op) MASK_BITS_SHIFT(op, 8, 11)
131
132 /* BRN Format */
133 #define MASK_OP_BRN_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
134 #define MASK_OP_BRN_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
135 #define MASK_OP_BRN_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30)
136 #define MASK_OP_BRN_N(op) (MASK_BITS_SHIFT(op, 12, 15) + \
137 (MASK_BITS_SHIFT(op, 7, 7) << 4))
138 #define MASK_OP_BRN_S1(op) MASK_BITS_SHIFT(op, 8, 11)
139 /* BRR Format */
140 #define MASK_OP_BRR_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
141 #define MASK_OP_BRR_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
142 #define MASK_OP_BRR_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30)
143 #define MASK_OP_BRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
144 #define MASK_OP_BRR_S1(op) MASK_BITS_SHIFT(op, 8, 11)
145
146 /* META MASK for similar instr Formats */
147 #define MASK_OP_META_D(op) MASK_BITS_SHIFT(op, 28, 31)
148 #define MASK_OP_META_S1(op) MASK_BITS_SHIFT(op, 8, 11)
149
150 /* RC Format */
151 #define MASK_OP_RC_D(op) MASK_OP_META_D(op)
152 #define MASK_OP_RC_OP2(op) MASK_BITS_SHIFT(op, 21, 27)
153 #define MASK_OP_RC_CONST9(op) MASK_BITS_SHIFT(op, 12, 20)
154 #define MASK_OP_RC_CONST9_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 20)
155 #define MASK_OP_RC_S1(op) MASK_OP_META_S1(op)
156
157 /* RCPW Format */
158
159 #define MASK_OP_RCPW_D(op) MASK_OP_META_D(op)
160 #define MASK_OP_RCPW_POS(op) MASK_BITS_SHIFT(op, 23, 27)
161 #define MASK_OP_RCPW_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
162 #define MASK_OP_RCPW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
163 #define MASK_OP_RCPW_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
164 #define MASK_OP_RCPW_S1(op) MASK_OP_META_S1(op)
165
166 /* RCR Format */
167
168 #define MASK_OP_RCR_D(op) MASK_OP_META_D(op)
169 #define MASK_OP_RCR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
170 #define MASK_OP_RCR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
171 #define MASK_OP_RCR_CONST9(op) MASK_BITS_SHIFT(op, 12, 20)
172 #define MASK_OP_RCR_CONST9_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 20)
173 #define MASK_OP_RCR_S1(op) MASK_OP_META_S1(op)
174
175 /* RCRR Format */
176
177 #define MASK_OP_RCRR_D(op) MASK_OP_META_D(op)
178 #define MASK_OP_RCRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
179 #define MASK_OP_RCRR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
180 #define MASK_OP_RCRR_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
181 #define MASK_OP_RCRR_S1(op) MASK_OP_META_S1(op)
182
183 /* RCRW Format */
184
185 #define MASK_OP_RCRW_D(op) MASK_OP_META_D(op)
186 #define MASK_OP_RCRW_S3(op) MASK_BITS_SHIFT(op, 24, 27)
187 #define MASK_OP_RCRW_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
188 #define MASK_OP_RCRW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
189 #define MASK_OP_RCRW_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
190 #define MASK_OP_RCRW_S1(op) MASK_OP_META_S1(op)
191
192 /* RLC Format */
193
194 #define MASK_OP_RLC_D(op) MASK_OP_META_D(op)
195 #define MASK_OP_RLC_CONST16(op) MASK_BITS_SHIFT(op, 12, 27)
196 #define MASK_OP_RLC_CONST16_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 27)
197 #define MASK_OP_RLC_S1(op) MASK_OP_META_S1(op)
198
199 /* RR Format */
200 #define MASK_OP_RR_D(op) MASK_OP_META_D(op)
201 #define MASK_OP_RR_OP2(op) MASK_BITS_SHIFT(op, 20, 27)
202 #define MASK_OP_RR_N(op) MASK_BITS_SHIFT(op, 16, 17)
203 #define MASK_OP_RR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
204 #define MASK_OP_RR_S1(op) MASK_OP_META_S1(op)
205
206 /* RR1 Format */
207 #define MASK_OP_RR1_D(op) MASK_OP_META_D(op)
208 #define MASK_OP_RR1_OP2(op) MASK_BITS_SHIFT(op, 18, 27)
209 #define MASK_OP_RR1_N(op) MASK_BITS_SHIFT(op, 16, 17)
210 #define MASK_OP_RR1_S2(op) MASK_BITS_SHIFT(op, 12, 15)
211 #define MASK_OP_RR1_S1(op) MASK_OP_META_S1(op)
212
213 /* RR2 Format */
214 #define MASK_OP_RR2_D(op) MASK_OP_META_D(op)
215 #define MASK_OP_RR2_OP2(op) MASK_BITS_SHIFT(op, 16, 27)
216 #define MASK_OP_RR2_S2(op) MASK_BITS_SHIFT(op, 12, 15)
217 #define MASK_OP_RR2_S1(op) MASK_OP_META_S1(op)
218
219 /* RRPW Format */
220 #define MASK_OP_RRPW_D(op) MASK_OP_META_D(op)
221 #define MASK_OP_RRPW_POS(op) MASK_BITS_SHIFT(op, 23, 27)
222 #define MASK_OP_RRPW_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
223 #define MASK_OP_RRPW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
224 #define MASK_OP_RRPW_S2(op) MASK_BITS_SHIFT(op, 12, 15)
225 #define MASK_OP_RRPW_S1(op) MASK_OP_META_S1(op)
226
227 /* RRR Format */
228 #define MASK_OP_RRR_D(op) MASK_OP_META_D(op)
229 #define MASK_OP_RRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
230 #define MASK_OP_RRR_OP2(op) MASK_BITS_SHIFT(op, 20, 23)
231 #define MASK_OP_RRR_N(op) MASK_BITS_SHIFT(op, 16, 17)
232 #define MASK_OP_RRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
233 #define MASK_OP_RRR_S1(op) MASK_OP_META_S1(op)
234
235 /* RRR1 Format */
236 #define MASK_OP_RRR1_D(op) MASK_OP_META_D(op)
237 #define MASK_OP_RRR1_S3(op) MASK_BITS_SHIFT(op, 24, 27)
238 #define MASK_OP_RRR1_OP2(op) MASK_BITS_SHIFT(op, 18, 23)
239 #define MASK_OP_RRR1_N(op) MASK_BITS_SHIFT(op, 16, 17)
240 #define MASK_OP_RRR1_S2(op) MASK_BITS_SHIFT(op, 12, 15)
241 #define MASK_OP_RRR1_S1(op) MASK_OP_META_S1(op)
242
243 /* RRR2 Format */
244 #define MASK_OP_RRR2_D(op) MASK_OP_META_D(op)
245 #define MASK_OP_RRR2_S3(op) MASK_BITS_SHIFT(op, 24, 27)
246 #define MASK_OP_RRR2_OP2(op) MASK_BITS_SHIFT(op, 16, 23)
247 #define MASK_OP_RRR2_S2(op) MASK_BITS_SHIFT(op, 12, 15)
248 #define MASK_OP_RRR2_S1(op) MASK_OP_META_S1(op)
249
250 /* RRRR Format */
251 #define MASK_OP_RRRR_D(op) MASK_OP_META_D(op)
252 #define MASK_OP_RRRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
253 #define MASK_OP_RRRR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
254 #define MASK_OP_RRRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
255 #define MASK_OP_RRRR_S1(op) MASK_OP_META_S1(op)
256
257 /* RRRW Format */
258 #define MASK_OP_RRRW_D(op) MASK_OP_META_D(op)
259 #define MASK_OP_RRRW_S3(op) MASK_BITS_SHIFT(op, 24, 27)
260 #define MASK_OP_RRRW_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
261 #define MASK_OP_RRRW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
262 #define MASK_OP_RRRW_S2(op) MASK_BITS_SHIFT(op, 12, 15)
263 #define MASK_OP_RRRW_S1(op) MASK_OP_META_S1(op)
264
265 /* SYS Format */
266 #define MASK_OP_SYS_OP2(op) MASK_BITS_SHIFT(op, 22, 27)
267 #define MASK_OP_SYS_S1D(op) MASK_OP_META_S1(op)
268
269
270
271 /*
272 * Tricore Opcodes Enums
273 *
274 * Format: OPC(1|2|M)_InstrLen_Name
275 * OPC1 = only op1 field is used
276 * OPC2 = op1 and op2 field used part of OPCM
277 * OPCM = op1 field used to group Instr
278 * InstrLen = 16|32
279 * Name = Name of Instr
280 */
281
282 /* 16-Bit */
283 enum {
284
285 OPCM_16_SR_SYSTEM = 0x00,
286 OPCM_16_SR_ACCU = 0x32,
287
288 OPC1_16_SRC_ADD = 0xc2,
289 OPC1_16_SRC_ADD_A15 = 0x92,
290 OPC1_16_SRC_ADD_15A = 0x9a,
291 OPC1_16_SRR_ADD = 0x42,
292 OPC1_16_SRR_ADD_A15 = 0x12,
293 OPC1_16_SRR_ADD_15A = 0x1a,
294 OPC1_16_SRC_ADD_A = 0xb0,
295 OPC1_16_SRR_ADD_A = 0x30,
296 OPC1_16_SRR_ADDS = 0x22,
297 OPC1_16_SRRS_ADDSC_A = 0x10,
298 OPC1_16_SC_AND = 0x16,
299 OPC1_16_SRR_AND = 0x26,
300 OPC1_16_SC_BISR = 0xe0,
301 OPC1_16_SRC_CADD = 0x8a,
302 OPC1_16_SRC_CADDN = 0xca,
303 OPC1_16_SB_CALL = 0x5c,
304 OPC1_16_SRC_CMOV = 0xaa,
305 OPC1_16_SRR_CMOV = 0x2a,
306 OPC1_16_SRC_CMOVN = 0xea,
307 OPC1_16_SRR_CMOVN = 0x6a,
308 OPC1_16_SRC_EQ = 0xba,
309 OPC1_16_SRR_EQ = 0x3a,
310 OPC1_16_SB_J = 0x3c,
311 OPC1_16_SBC_JEQ = 0x1e,
312 OPC1_16_SBR_JEQ = 0x3e,
313 OPC1_16_SBR_JGEZ = 0xce,
314 OPC1_16_SBR_JGTZ = 0x4e,
315 OPC1_16_SR_JI = 0xdc,
316 OPC1_16_SBR_JLEZ = 0x8e,
317 OPC1_16_SBR_JLTZ = 0x0e,
318 OPC1_16_SBC_JNE = 0x5e,
319 OPC1_16_SBR_JNE = 0x7e,
320 OPC1_16_SB_JNZ = 0xee,
321 OPC1_16_SBR_JNZ = 0xf6,
322 OPC1_16_SBR_JNZ_A = 0x7c,
323 OPC1_16_SBRN_JNZ_T = 0xae,
324 OPC1_16_SB_JZ = 0x6e,
325 OPC1_16_SBR_JZ = 0x76,
326 OPC1_16_SBR_JZ_A = 0xbc,
327 OPC1_16_SBRN_JZ_T = 0x2e,
328 OPC1_16_SC_LD_A = 0xd8,
329 OPC1_16_SLR_LD_A = 0xd4,
330 OPC1_16_SLR_LD_A_POSTINC = 0xc4,
331 OPC1_16_SLRO_LD_A = 0xc8,
332 OPC1_16_SRO_LD_A = 0xcc,
333 OPC1_16_SLR_LD_BU = 0x14,
334 OPC1_16_SLR_LD_BU_POSTINC = 0x04,
335 OPC1_16_SLRO_LD_BU = 0x08,
336 OPC1_16_SRO_LD_BU = 0x0c,
337 OPC1_16_SLR_LD_H = 0x94,
338 OPC1_16_SLR_LD_H_POSTINC = 0x84,
339 OPC1_16_SLRO_LD_H = 0x88,
340 OPC1_16_SRO_LD_H = 0x8c,
341 OPC1_16_SC_LD_W = 0x58,
342 OPC1_16_SLR_LD_W = 0x54,
343 OPC1_16_SLR_LD_W_POSTINC = 0x44,
344 OPC1_16_SLRO_LD_W = 0x48,
345 OPC1_16_SRO_LD_W = 0x4c,
346 OPC1_16_SBR_LOOP = 0xfc,
347 OPC1_16_SRC_LT = 0xfa,
348 OPC1_16_SRR_LT = 0x7a,
349 OPC1_16_SC_MOV = 0xda,
350 OPC1_16_SRC_MOV = 0x82,
351 OPC1_16_SRR_MOV = 0x02,
352 OPC1_16_SRC_MOV_E = 0xd2,/* 1.6 only */
353 OPC1_16_SRC_MOV_A = 0xa0,
354 OPC1_16_SRR_MOV_A = 0x60,
355 OPC1_16_SRR_MOV_AA = 0x40,
356 OPC1_16_SRR_MOV_D = 0x80,
357 OPC1_16_SRR_MUL = 0xe2,
358 OPC1_16_SR_NOT = 0x46,
359 OPC1_16_SC_OR = 0x96,
360 OPC1_16_SRR_OR = 0xa6,
361 OPC1_16_SRC_SH = 0x06,
362 OPC1_16_SRC_SHA = 0x86,
363 OPC1_16_SC_ST_A = 0xf8,
364 OPC1_16_SRO_ST_A = 0xec,
365 OPC1_16_SSR_ST_A = 0xf4,
366 OPC1_16_SSR_ST_A_POSTINC = 0xe4,
367 OPC1_16_SSRO_ST_A = 0xe8,
368 OPC1_16_SRO_ST_B = 0x2c,
369 OPC1_16_SSR_ST_B = 0x34,
370 OPC1_16_SSR_ST_B_POSTINC = 0x24,
371 OPC1_16_SSRO_ST_B = 0x28,
372 OPC1_16_SRO_ST_H = 0xac,
373 OPC1_16_SSR_ST_H = 0xb4,
374 OPC1_16_SSR_ST_H_POSTINC = 0xa4,
375 OPC1_16_SSRO_ST_H = 0xa8,
376 OPC1_16_SC_ST_W = 0x78,
377 OPC1_16_SRO_ST_W = 0x6c,
378 OPC1_16_SSR_ST_W = 0x74,
379 OPC1_16_SSR_ST_W_POSTINC = 0x64,
380 OPC1_16_SSRO_ST_W = 0x68,
381 OPC1_16_SRR_SUB = 0xa2,
382 OPC1_16_SRR_SUB_A15B = 0x52,
383 OPC1_16_SRR_SUB_15AB = 0x5a,
384 OPC1_16_SC_SUB_A = 0x20,
385 OPC1_16_SRR_SUBS = 0x62,
386 OPC1_16_SRR_XOR = 0xc6,
387
388 };
389
390 /*
391 * SR Format
392 */
393 /* OPCM_16_SR_SYSTEM */
394 enum {
395
396 OPC2_16_SR_NOP = 0x00,
397 OPC2_16_SR_RET = 0x09,
398 OPC2_16_SR_RFE = 0x08,
399 OPC2_16_SR_DEBUG = 0x0a,
400 };
401 /* OPCM_16_SR_ACCU */
402 enum {
403 OPC2_16_SR_RSUB = 0x05,
404 OPC2_16_SR_SAT_B = 0x00,
405 OPC2_16_SR_SAT_BU = 0x01,
406 OPC2_16_SR_SAT_H = 0x02,
407 OPC2_16_SR_SAT_HU = 0x03,
408
409 };
410
411 /* 32-Bit */
412
413 enum {
414 /* ABS Format 1, M */
415 OPCM_32_ABS_LDW = 0x85,
416 OPCM_32_ABS_LDB = 0x05,
417 OPCM_32_ABS_LDMST_SWAP = 0xe5,
418 OPCM_32_ABS_LDST_CONTEXT = 0x15,
419 OPCM_32_ABS_STORE = 0xa5,
420 OPCM_32_ABS_STOREB_H = 0x25,
421 OPC1_32_ABS_STOREQ = 0x65,
422 OPC1_32_ABS_LD_Q = 0x45,
423 OPC1_32_ABS_LEA = 0xc5,
424 /* ABSB Format */
425 OPC1_32_ABSB_ST_T = 0xd5,
426 /* B Format */
427 OPC1_32_B_CALL = 0x6d,
428 OPC1_32_B_CALLA = 0xed,
429 OPC1_32_B_J = 0x1d,
430 OPC1_32_B_JA = 0x9d,
431 OPC1_32_B_JL = 0x5d,
432 OPC1_32_B_JLA = 0xdd,
433 /* Bit Format */
434 OPCM_32_BIT_ANDACC = 0x47,
435 OPCM_32_BIT_LOGICAL_T1 = 0x87,
436 OPCM_32_BIT_INSERT = 0x67,
437 OPCM_32_BIT_LOGICAL_T2 = 0x07,
438 OPCM_32_BIT_ORAND = 0xc7,
439 OPCM_32_BIT_SH_LOGIC1 = 0x27,
440 OPCM_32_BIT_SH_LOGIC2 = 0xa7,
441 /* BO Format */
442 OPCM_32_BO_ADDRMODE_POST_PRE_BASE = 0x89,
443 OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR = 0xa9,
444 OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE = 0x09,
445 OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR = 0x29,
446 OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE = 0x49,
447 OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR = 0x69,
448 /* BOL Format */
449 OPC1_32_BOL_LD_A_LONGOFF = 0x99,
450 OPC1_32_BOL_LD_W_LONFOFF = 0x19,
451 OPC1_32_BOL_LEA_LONGOFF = 0xd9,
452 OPC1_32_BOL_ST_W_LONGOFF = 0x59,
453 OPC1_32_BOL_ST_A_LONGOFF = 0xb5, /* 1.6 only */
454 /* BRC Format */
455 OPCM_32_BRC_EQ_NEQ = 0xdf,
456 OPCM_32_BRC_GE = 0xff,
457 OPCM_32_BRC_JLT = 0xbf,
458 OPCM_32_BRC_JNE = 0x9f,
459 /* BRN Format */
460 OPCM_32_BRN_JTT = 0x6f,
461 /* BRR Format */
462 OPCM_32_BRR_EQ_NEQ = 0x5f,
463 OPCM_32_BRR_ADDR_EQ_NEQ = 0x7d,
464 OPCM_32_BRR_GE = 0x7f,
465 OPCM_32_BRR_JLT = 0x3f,
466 OPCM_32_BRR_JNE = 0x1f,
467 OPCM_32_BRR_JNZ = 0xbd,
468 OPCM_32_BRR_LOOP = 0xfd,
469 /* RC Format */
470 OPCM_32_RC_LOGICAL_SHIFT = 0x8f,
471 OPCM_32_RC_ACCUMULATOR = 0x8b,
472 OPCM_32_RC_SERVICEROUTINE = 0xad,
473 OPCM_32_RC_MUL = 0x53,
474 /* RCPW Format */
475 OPCM_32_RCPW_MASK_INSERT = 0xb7,
476 /* RCR Format */
477 OPCM_32_RCR_COND_SELECT = 0xab,
478 OPCM_32_RCR_MADD = 0x13,
479 OPCM_32_RCR_MSUB = 0x33,
480 /* RCRR Format */
481 OPC1_32_RCRR_INSERT = 0x97,
482 /* RCRW Format */
483 OPCM_32_RCRW_MASK_INSERT = 0xd7,
484 /* RLC Format */
485 OPC1_32_RLC_ADDI = 0x1b,
486 OPC1_32_RLC_ADDIH = 0x9b,
487 OPC1_32_RLC_ADDIH_A = 0x11,
488 OPC1_32_RLC_MFCR = 0x4d,
489 OPC1_32_RLC_MOV = 0x3b,
490 OPC1_32_RLC_MOV_U = 0xbb,
491 OPC1_32_RLC_MOV_H = 0x7b,
492 OPC1_32_RLC_MOVH_A = 0x91,
493 OPC1_32_RLC_MTCR = 0xcd,
494 /* RR Format */
495 OPCM_32_RR_LOGICAL_SHIFT = 0x0f,
496 OPCM_32_RR_ACCUMULATOR = 0x0b,
497 OPCM_32_RR_ADRESS = 0x01,
498 OPCM_32_RR_FLOAT = 0x4b,
499 OPCM_32_RR_IDIRECT = 0x2d,
500 /* RR1 Format */
501 OPCM_32_RR1_MUL = 0xb3,
502 OPCM_32_RR1_MULQ = 0x93,
503 /* RR2 Format */
504 OPCM_32_RR2_MUL = 0x73,
505 /* RRPW Format */
506 OPCM_32_RRPW_EXTRACT_INSERT = 0x37,
507 OPC1_32_RRPW_DEXTR = 0x77,
508 /* RRR Format */
509 OPCM_32_RRR_COND_SELECT = 0x2b,
510 OPCM_32_RRR_FLOAT = 0x6b,
511 /* RRR1 Format */
512 OPCM_32_RRR1_MADD = 0x83,
513 OPCM_32_RRR1_MADDQ_H = 0x43,
514 OPCM_32_RRR1_MADDSU_H = 0xc3,
515 OPCM_32_RRR1_MSUB_H = 0xa3,
516 OPCM_32_RRR1_MSUB_Q = 0x63,
517 OPCM_32_RRR1_MSUBADS_H = 0xe3,
518 /* RRR2 Format */
519 OPCM_32_RRR2_MADD = 0x03,
520 OPCM_32_RRR2_MSUB = 0x23,
521 /* RRRR Format */
522 OPCM_32_RRRR_EXTRACT_INSERT = 0x17,
523 /* RRRW Format */
524 OPCM_32_RRRW_EXTRACT_INSERT = 0x57,
525 /* SYS Format */
526 OPCM_32_SYS_INTERRUPTS = 0x0d,
527 OPC1_32_SYS_RSTV = 0x2f,
528 };
529
530
531
532 /*
533 * ABS Format
534 */
535
536 /* OPCM_32_ABS_LDW */
537 enum {
538
539 OPC2_32_ABS_LD_A = 0x02,
540 OPC2_32_ABS_LD_D = 0x01,
541 OPC2_32_ABS_LD_DA = 0x03,
542 OPC2_32_ABS_LD_W = 0x00,
543 };
544
545 /* OPCM_32_ABS_LDB */
546 enum {
547 OPC2_32_ABS_LD_B = 0x00,
548 OPC2_32_ABS_LD_BU = 0x01,
549 OPC2_32_ABS_LD_H = 0x02,
550 OPC2_32_ABS_LD_HU = 0x03,
551 };
552 /* OPCM_32_ABS_LDMST_SWAP */
553 enum {
554 OPC2_32_ABS_LDMST = 0x01,
555 OPC2_32_ABS_SWAP_W = 0x00,
556 };
557 /* OPCM_32_ABS_LDST_CONTEXT */
558 enum {
559 OPC2_32_ABS_LDLCX = 0x02,
560 OPC2_32_ABS_LDUCX = 0x03,
561 OPC2_32_ABS_STLCX = 0x00,
562 OPC2_32_ABS_STUCX = 0x01,
563 };
564 /* OPCM_32_ABS_STORE */
565 enum {
566 OPC2_32_ABS_ST_A = 0x02,
567 OPC2_32_ABS_ST_D = 0x01,
568 OPC2_32_ABS_ST_DA = 0x03,
569 OPC2_32_ABS_ST_W = 0x00,
570 };
571 /* OPCM_32_ABS_STOREB_H */
572 enum {
573 OPC2_32_ABS_ST_B = 0x00,
574 OPC2_32_ABS_ST_H = 0x02,
575 };
576 /*
577 * Bit Format
578 */
579 /* OPCM_32_BIT_ANDACC */
580 enum {
581 OPC2_32_BIT_AND_AND_T = 0x00,
582 OPC2_32_BIT_AND_ANDN_T = 0x03,
583 OPC2_32_BIT_AND_NOR_T = 0x02,
584 OPC2_32_BIT_AND_OR_T = 0x01,
585 };
586 /* OPCM_32_BIT_LOGICAL_T */
587 enum {
588 OPC2_32_BIT_AND_T = 0x00,
589 OPC2_32_BIT_ANDN_T = 0x03,
590 OPC2_32_BIT_NOR_T = 0x02,
591 OPC2_32_BIT_OR_T = 0x01,
592 };
593 /* OPCM_32_BIT_INSERT */
594 enum {
595 OPC2_32_BIT_INS_T = 0x00,
596 OPC2_32_BIT_INSN_T = 0x01,
597 };
598 /* OPCM_32_BIT_LOGICAL_T2 */
599 enum {
600 OPC2_32_BIT_NAND_T = 0x00,
601 OPC2_32_BIT_ORN_T = 0x01,
602 OPC2_32_BIT_XNOR_T = 0x02,
603 OPC2_32_BIT_XOR_T = 0x03,
604 };
605 /* OPCM_32_BIT_ORAND */
606 enum {
607 OPC2_32_BIT_OR_AND_T = 0x00,
608 OPC2_32_BIT_OR_ANDN_T = 0x03,
609 OPC2_32_BIT_OR_NOR_T = 0x02,
610 OPC2_32_BIT_OR_OR_T = 0x01,
611 };
612 /*OPCM_32_BIT_SH_LOGIC1 */
613 enum {
614 OPC2_32_BIT_SH_AND_T = 0x00,
615 OPC2_32_BIT_SH_ANDN_T = 0x03,
616 OPC2_32_BIT_SH_NOR_T = 0x02,
617 OPC2_32_BIT_SH_OR_T = 0x01,
618 };
619 /* OPCM_32_BIT_SH_LOGIC2 */
620 enum {
621 OPC2_32_BIT_SH_NAND_T = 0x00,
622 OPC2_32_BIT_SH_ORN_T = 0x01,
623 OPC2_32_BIT_SH_XNOR_T = 0x02,
624 OPC2_32_BIT_SH_XOR_T = 0x03,
625 };
626 /*
627 * BO Format
628 */
629 /* OPCM_32_BO_ADDRMODE_POST_PRE_BASE */
630 enum {
631 OPC2_32_BO_CACHEA_I_SHORTOFF = 0x2e,
632 OPC2_32_BO_CACHEA_I_POSTINC = 0x0e,
633 OPC2_32_BO_CACHEA_I_PREINC = 0x1e,
634 OPC2_32_BO_CACHEA_W_SHORTOFF = 0x2c,
635 OPC2_32_BO_CACHEA_W_POSTINC = 0x0c,
636 OPC2_32_BO_CACHEA_W_PREINC = 0x1c,
637 OPC2_32_BO_CACHEA_WI_SHORTOFF = 0x2d,
638 OPC2_32_BO_CACHEA_WI_POSTINC = 0x0d,
639 OPC2_32_BO_CACHEA_WI_PREINC = 0x1d,
640 /* 1.3.1 only */
641 OPC2_32_BO_CACHEI_W_SHORTOFF = 0x2b,
642 OPC2_32_BO_CACHEI_W_POSTINC = 0x0b,
643 OPC2_32_BO_CACHEI_W_PREINC = 0x1b,
644 OPC2_32_BO_CACHEI_WI_SHORTOFF = 0x2f,
645 OPC2_32_BO_CACHEI_WI_POSTINC = 0x0f,
646 OPC2_32_BO_CACHEI_WI_PREINC = 0x1f,
647 /* end 1.3.1 only */
648 OPC2_32_BO_ST_A_SHORTOFF = 0x26,
649 OPC2_32_BO_ST_A_POSTINC = 0x06,
650 OPC2_32_BO_ST_A_PREINC = 0x16,
651 OPC2_32_BO_ST_B_SHORTOFF = 0x20,
652 OPC2_32_BO_ST_B_POSTINC = 0x00,
653 OPC2_32_BO_ST_B_PREINC = 0x10,
654 OPC2_32_BO_ST_D_SHORTOFF = 0x25,
655 OPC2_32_BO_ST_D_POSTINC = 0x05,
656 OPC2_32_BO_ST_D_PREINC = 0x15,
657 OPC2_32_BO_ST_DA_SHORTOFF = 0x27,
658 OPC2_32_BO_ST_DA_POSTINC = 0x07,
659 OPC2_32_BO_ST_DA_PREINC = 0x17,
660 OPC2_32_BO_ST_H_SHORTOFF = 0x22,
661 OPC2_32_BO_ST_H_POSTINC = 0x02,
662 OPC2_32_BO_ST_H_PREINC = 0x12,
663 OPC2_32_BO_ST_Q_SHORTOFF = 0x28,
664 OPC2_32_BO_ST_Q_POSTINC = 0x08,
665 OPC2_32_BO_ST_Q_PREINC = 0x18,
666 OPC2_32_BO_ST_W_SHORTOFF = 0x24,
667 OPC2_32_BO_ST_W_POSTINC = 0x04,
668 OPC2_32_BO_ST_W_PREINC = 0x14,
669 };
670 /* OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR */
671 enum {
672 OPC2_32_BO_CACHEA_I_BR = 0x0e,
673 OPC2_32_BO_CACHEA_I_CIRC = 0x1e,
674 OPC2_32_BO_CACHEA_W_BR = 0x0c,
675 OPC2_32_BO_CACHEA_W_CIRC = 0x1c,
676 OPC2_32_BO_CACHEA_WI_BR = 0x0d,
677 OPC2_32_BO_CACHEA_WI_CIRC = 0x1d,
678 OPC2_32_BO_ST_A_BR = 0x06,
679 OPC2_32_BO_ST_A_CIRC = 0x16,
680 OPC2_32_BO_ST_B_BR = 0x00,
681 OPC2_32_BO_ST_B_CIRC = 0x10,
682 OPC2_32_BO_ST_D_BR = 0x05,
683 OPC2_32_BO_ST_D_CIRC = 0x15,
684 OPC2_32_BO_ST_DA_BR = 0x07,
685 OPC2_32_BO_ST_DA_CIRC = 0x17,
686 OPC2_32_BO_ST_H_BR = 0x02,
687 OPC2_32_BO_ST_H_CIRC = 0x12,
688 OPC2_32_BO_ST_Q_BR = 0x08,
689 OPC2_32_BO_ST_Q_CIRC = 0x18,
690 OPC2_32_BO_ST_W_BR = 0x04,
691 OPC2_32_BO_ST_W_CIRC = 0x14,
692 };
693 /* OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE */
694 enum {
695 OPC2_32_BO_LD_A_SHORTOFF = 0x26,
696 OPC2_32_BO_LD_A_POSTINC = 0x06,
697 OPC2_32_BO_LD_A_PREINC = 0x16,
698 OPC2_32_BO_LD_B_SHORTOFF = 0x20,
699 OPC2_32_BO_LD_B_POSTINC = 0x00,
700 OPC2_32_BO_LD_B_PREINC = 0x10,
701 OPC2_32_BO_LD_BU_SHORTOFF = 0x21,
702 OPC2_32_BO_LD_BU_POSTINC = 0x01,
703 OPC2_32_BO_LD_BU_PREINC = 0x11,
704 OPC2_32_BO_LD_D_SHORTOFF = 0x25,
705 OPC2_32_BO_LD_D_POSTINC = 0x05,
706 OPC2_32_BO_LD_D_PREINC = 0x15,
707 OPC2_32_BO_LD_DA_SHORTOFF = 0x27,
708 OPC2_32_BO_LD_DA_POSTINC = 0x07,
709 OPC2_32_BO_LD_DA_PREINC = 0x17,
710 OPC2_32_BO_LD_H_SHORTOFF = 0x22,
711 OPC2_32_BO_LD_H_POSTINC = 0x02,
712 OPC2_32_BO_LD_H_PREINC = 0x12,
713 OPC2_32_BO_LD_HU_SHORTOFF = 0x23,
714 OPC2_32_BO_LD_HU_POSTINC = 0x03,
715 OPC2_32_BO_LD_HU_PREINC = 0x13,
716 OPC2_32_BO_LD_Q_SHORTOFF = 0x28,
717 OPC2_32_BO_LD_Q_POSTINC = 0x08,
718 OPC2_32_BO_LD_Q_PREINC = 0x18,
719 OPC2_32_BO_LD_W_SHORTOFF = 0x24,
720 OPC2_32_BO_LD_W_POSTINC = 0x04,
721 OPC2_32_BO_LD_W_PREINC = 0x14,
722 };
723 /* OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR */
724 enum {
725 OPC2_32_BO_LD_A_BR = 0x06,
726 OPC2_32_BO_LD_A_CIRC = 0x16,
727 OPC2_32_BO_LD_B_BR = 0x00,
728 OPC2_32_BO_LD_B_CIRC = 0x10,
729 OPC2_32_BO_LD_BU_BR = 0x01,
730 OPC2_32_BO_LD_BU_CIRC = 0x11,
731 OPC2_32_BO_LD_D_BR = 0x05,
732 OPC2_32_BO_LD_D_CIRC = 0x15,
733 OPC2_32_BO_LD_DA_BR = 0x07,
734 OPC2_32_BO_LD_DA_CIRC = 0x17,
735 OPC2_32_BO_LD_H_BR = 0x02,
736 OPC2_32_BO_LD_H_CIRC = 0x12,
737 OPC2_32_BO_LD_HU_BR = 0x03,
738 OPC2_32_BO_LD_HU_CIRC = 0x13,
739 OPC2_32_BO_LD_Q_BR = 0x08,
740 OPC2_32_BO_LD_Q_CIRC = 0x18,
741 OPC2_32_BO_LD_W_BR = 0x04,
742 OPC2_32_BO_LD_W_CIRC = 0x14,
743 };
744 /* OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE */
745 enum {
746 OPC2_32_BO_LDLCX_SHORTOFF = 0x24,
747 OPC2_32_BO_LDMST_SHORTOFF = 0x21,
748 OPC2_32_BO_LDMST_POSTINC = 0x01,
749 OPC2_32_BO_LDMST_PREINC = 0x11,
750 OPC2_32_BO_LDUCX_SHORTOFF = 0x25,
751 OPC2_32_BO_LEA_SHORTOFF = 0x28,
752 OPC2_32_BO_STLCX_SHORTOFF = 0x26,
753 OPC2_32_BO_STUCX_SHORTOFF = 0x27,
754 OPC2_32_BO_SWAP_W_SHORTOFF = 0x20,
755 OPC2_32_BO_SWAP_W_POSTINC = 0x00,
756 OPC2_32_BO_SWAP_W_PREINC = 0x10,
757 };
758 /*OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR */
759 enum {
760 OPC2_32_BO_LDMST_BR = 0x01,
761 OPC2_32_BO_LDMST_CIRC = 0x11,
762 OPC2_32_BO_SWAP_W_BR = 0x00,
763 OPC2_32_BO_SWAP_W_CIRC = 0x10,
764 };
765 /*
766 * BRC Format
767 */
768 /*OPCM_32_BRC_EQ_NEQ */
769 enum {
770 OPC2_32_BRC_JEQ = 0x00,
771 OPC2_32_BRC_JNE = 0x01,
772 };
773 /* OPCM_32_BRC_GE */
774 enum {
775 OP2_32_BRC_JGE = 0x00,
776 OPC_32_BRC_JGE_U = 0x01,
777 };
778 /* OPCM_32_BRC_JLT */
779 enum {
780 OPC2_32_BRC_JLT = 0x00,
781 OPC2_32_BRC_JLT_U = 0x01,
782 };
783 /* OPCM_32_BRC_JNE */
784 enum {
785 OPC2_32_BRC_JNED = 0x01,
786 OPC2_32_BRC_JNEI = 0x00,
787 };
788 /*
789 * BRN Format
790 */
791 /* OPCM_32_BRN_JTT */
792 enum {
793 OPC2_32_BRN_JNZ_T = 0x01,
794 OPC2_32_BRN_JZ_T = 0x00,
795 };
796 /*
797 * BRR Format
798 */
799 /* OPCM_32_BRR_EQ_NEQ */
800 enum {
801 OPC2_32_BRR_JEQ = 0x00,
802 OPC2_32_BRR_JNE = 0x01,
803 };
804 /* OPCM_32_BRR_ADDR_EQ_NEQ */
805 enum {
806 OPC2_32_BRR_JEQ_A = 0x00,
807 OPC2_32_BRR_JNE_A = 0x01,
808 };
809 /*OPCM_32_BRR_GE */
810 enum {
811 OPC2_32_BRR_JGE = 0x00,
812 OPC2_32_BRR_JGE_U = 0x01,
813 };
814 /* OPCM_32_BRR_JLT */
815 enum {
816 OPC2_32_BRR_JLT = 0x00,
817 OPC2_32_BRR_JLT_U = 0x01,
818 };
819 /* OPCM_32_BRR_JNE */
820 enum {
821 OPC2_32_BRR_JNED = 0x01,
822 OPC2_32_BRR_JNEI = 0x00,
823 };
824 /* OPCM_32_BRR_JNZ */
825 enum {
826 OPC2_32_BRR_JNZ_A = 0x01,
827 OPC2_32_BRR_JZ_A = 0x00,
828 };
829 /* OPCM_32_BRR_LOOP */
830 enum {
831 OPC2_32_BRR_LOOP = 0x00,
832 OPC2_32_BRR_LOOPU = 0x01,
833 };
834 /*
835 * RC Format
836 */
837 /* OPCM_32_RC_LOGICAL_SHIFT */
838 enum {
839 OPC2_32_RC_AND = 0x08,
840 OPC2_32_RC_ANDN = 0x0e,
841 OPC2_32_RC_NAND = 0x09,
842 OPC2_32_RC_NOR = 0x0b,
843 OPC2_32_RC_OR = 0x0a,
844 OPC2_32_RC_ORN = 0x0f,
845 OPC2_32_RC_SH = 0x00,
846 OPC2_32_RC_SH_H = 0x40,
847 OPC2_32_RC_SHA = 0x01,
848 OPC2_32_RC_SHA_H = 0x41,
849 OPC2_32_RC_SHAS = 0x02,
850 OPC2_32_RC_XNOR = 0x0d,
851 OPC2_32_RC_XOR = 0x0c,
852 };
853 /* OPCM_32_RC_ACCUMULATOR */
854 enum {
855 OPC2_32_RC_ABSDIF = 0x0e,
856 OPC2_32_RC_ABSDIFS = 0x0f,
857 OPC2_32_RC_ADD = 0x00,
858 OPC2_32_RC_ADDC = 0x05,
859 OPC2_32_RC_ADDS = 0x02,
860 OPC2_32_RC_ADDS_U = 0x03,
861 OPC2_32_RC_ADDX = 0x04,
862 OPC2_32_RC_AND_EQ = 0x20,
863 OPC2_32_RC_AND_GE = 0x24,
864 OPC2_32_RC_AND_GE_U = 0x25,
865 OPC2_32_RC_AND_LT = 0x22,
866 OPC2_32_RC_AND_LT_U = 0x23,
867 OPC2_32_RC_AND_NE = 0x21,
868 OPC2_32_RC_EQ = 0x10,
869 OPC2_32_RC_EQANY_B = 0x56,
870 OPC2_32_RC_EQANY_H = 0x76,
871 OPC2_32_RC_GE = 0x14,
872 OPC2_32_RC_GE_U = 0x15,
873 OPC2_32_RC_LT = 0x12,
874 OPC2_32_RC_LT_U = 0x13,
875 OPC2_32_RC_MAX = 0x1a,
876 OPC2_32_RC_MAX_U = 0x1b,
877 OPC2_32_RC_MIN = 0x18,
878 OPC2_32_RC_MIN_U = 0x19,
879 OPC2_32_RC_NE = 0x11,
880 OPC2_32_RC_OR_EQ = 0x27,
881 OPC2_32_RC_OR_GE = 0x2b,
882 OPC2_32_RC_OR_GE_U = 0x2c,
883 OPC2_32_RC_OR_LT = 0x29,
884 OPC2_32_RC_OR_LT_U = 0x2a,
885 OPC2_32_RC_OR_NE = 0x28,
886 OPC2_32_RC_RSUB = 0x08,
887 OPC2_32_RC_RSUBS = 0x0a,
888 OPC2_32_RC_RSUBS_U = 0x0b,
889 OPC2_32_RC_SH_EQ = 0x37,
890 OPC2_32_RC_SH_GE = 0x3b,
891 OPC2_32_RC_SH_GE_U = 0x3c,
892 OPC2_32_RC_SH_LT = 0x39,
893 OPC2_32_RC_SH_LT_U = 0x3a,
894 OPC2_32_RC_SH_NE = 0x38,
895 OPC2_32_RC_XOR_EQ = 0x2f,
896 OPC2_32_RC_XOR_GE = 0x33,
897 OPC2_32_RC_XOR_GE_U = 0x34,
898 OPC2_32_RC_XOR_LT = 0x31,
899 OPC2_32_RC_XOR_LT_U = 0x32,
900 OPC2_32_RC_XOR_NE = 0x30,
901 };
902 /* OPCM_32_RC_SERVICEROUTINE */
903 enum {
904 OPC2_32_RC_BISR = 0x00,
905 OPC2_32_RC_SYSCALL = 0x04,
906 };
907 /* OPCM_32_RC_MUL */
908 enum {
909 OPC2_32_RC_MUL_32 = 0x01,
910 OPC2_32_RC_MUL_64 = 0x03,
911 OPC2_32_RC_MULS_32 = 0x05,
912 OPC2_32_RC_MUL_U_64 = 0x02,
913 OPC2_32_RC_MULS_U_32 = 0x04,
914 };
915 /*
916 * RCPW Format
917 */
918 /* OPCM_32_RCPW_MASK_INSERT */
919 enum {
920 OPC2_32_RCPW_IMASK = 0x01,
921 OPC2_32_RCPW_INSERT = 0x00,
922 };
923 /*
924 * RCR Format
925 */
926 /* OPCM_32_RCR_COND_SELECT */
927 enum {
928 OPC2_32_RCR_CADD = 0x00,
929 OPC2_32_RCR_CADDN = 0x01,
930 OPC2_32_RCR_SEL = 0x04,
931 OPC2_32_RCR_SELN = 0x05,
932 };
933 /* OPCM_32_RCR_MADD */
934 enum {
935 OPC2_32_RCR_MADD_32 = 0x01,
936 OPC2_32_RCR_MADD_64 = 0x03,
937 OPC2_32_RCR_MADDS_32 = 0x05,
938 OPC2_32_RCR_MADDS_64 = 0x07,
939 OPC2_32_RCR_MADD_U_64 = 0x02,
940 OPC2_32_RCR_MADDS_U_32 = 0x04,
941 OPC2_32_RCR_MADDS_U_64 = 0x06,
942 };
943 /* OPCM_32_RCR_MSUB */
944 enum {
945 OPC2_32_RCR_MSUB_32 = 0x01,
946 OPC2_32_RCR_MSUB_64 = 0x03,
947 OPC2_32_RCR_MSUBS_32 = 0x05,
948 OPC2_32_RCR_MSUBS_64 = 0x07,
949 OPC2_32_RCR_MSUB_U_64 = 0x02,
950 OPC2_32_RCR_MSUBS_U_32 = 0x04,
951 OPC2_32_RCR_MSUBS_U_64 = 0x06,
952 };
953 /*
954 * RCRW Format
955 */
956 /* OPCM_32_RCRW_MASK_INSERT */
957 enum {
958 OPC2_32_RCRW_IMASK = 0x01,
959 OPC2_32_RCRW_INSERT = 0x00,
960 };
961
962 /*
963 * RR Format
964 */
965 /* OPCM_32_RR_LOGICAL_SHIFT */
966 enum {
967 OPC2_32_RR_AND = 0x08,
968 OPC2_32_RR_ANDN = 0x0e,
969 OPC2_32_RR_CLO = 0x1c,
970 OPC2_32_RR_CLO_H = 0x7d,
971 OPC2_32_RR_CLS = 0x1d,
972 OPC2_32_RR_CLS_H = 0x7e,
973 OPC2_32_RR_CLZ = 0x1b,
974 OPC2_32_RR_CLZ_H = 0x7c,
975 OPC2_32_RR_NAND = 0x09,
976 OPC2_32_RR_NOR = 0x0b,
977 OPC2_32_RR_OR = 0x0a,
978 OPC2_32_RR_ORN = 0x0f,
979 OPC2_32_RR_SH = 0x00,
980 OPC2_32_RR_SH_H = 0x40,
981 OPC2_32_RR_SHA = 0x01,
982 OPC2_32_RR_SHA_H = 0x41,
983 OPC2_32_RR_SHAS = 0x02,
984 OPC2_32_RR_XNOR = 0x0d,
985 OPC2_32_RR_XOR = 0x0c,
986 };
987 /* OPCM_32_RR_ACCUMULATOR */
988 enum {
989 OPC2_32_RR_ABS = 0x1c,
990 OPC2_32_RR_ABS_B = 0x5c,
991 OPC2_32_RR_ABS_H = 0x7c,
992 OPC2_32_RR_ABSDIF = 0x0e,
993 OPC2_32_RR_ABSDIF_B = 0x4e,
994 OPC2_32_RR_ABSDIF_H = 0x6e,
995 OPC2_32_RR_ABSDIFS = 0x0f,
996 OPC2_32_RR_ABSDIFS_H = 0x6f,
997 OPC2_32_RR_ABSS = 0x1d,
998 OPC2_32_RR_ABSS_H = 0x7d,
999 OPC2_32_RR_ADD = 0x00,
1000 OPC2_32_RR_ADD_B = 0x40,
1001 OPC2_32_RR_ADD_H = 0x60,
1002 OPC2_32_RR_ADDC = 0x05,
1003 OPC2_32_RR_ADDS = 0x02,
1004 OPC2_32_RR_ADDS_H = 0x62,
1005 OPC2_32_RR_ADDS_HU = 0x63,
1006 OPC2_32_RR_ADDS_U = 0x03,
1007 OPC2_32_RR_ADDX = 0x04,
1008 OPC2_32_RR_AND_EQ = 0x20,
1009 OPC2_32_RR_AND_GE = 0x24,
1010 OPC2_32_RR_AND_GE_U = 0x25,
1011 OPC2_32_RR_AND_LT = 0x22,
1012 OPC2_32_RR_AND_LT_U = 0x23,
1013 OPC2_32_RR_AND_NE = 0x21,
1014 OPC2_32_RR_EQ = 0x10,
1015 OPC2_32_RR_EQ_B = 0x50,
1016 OPC2_32_RR_EQ_H = 0x70,
1017 OPC2_32_RR_EQ_W = 0x90,
1018 OPC2_32_RR_EQANY_B = 0x56,
1019 OPC2_32_RR_EQANY_H = 0x76,
1020 OPC2_32_RR_GE = 0x14,
1021 OPC2_32_RR_GE_U = 0x15,
1022 OPC2_32_RR_LT = 0x12,
1023 OPC2_32_RR_LT_U = 0x13,
1024 OPC2_32_RR_LT_B = 0x52,
1025 OPC2_32_RR_LT_BU = 0x53,
1026 OPC2_32_RR_LT_H = 0x72,
1027 OPC2_32_RR_LT_HU = 0x73,
1028 OPC2_32_RR_LT_W = 0x92,
1029 OPC2_32_RR_LT_WU = 0x93,
1030 OPC2_32_RR_MAX = 0x1a,
1031 OPC2_32_RR_MAX_U = 0x1b,
1032 OPC2_32_RR_MAX_B = 0x5a,
1033 OPC2_32_RR_MAX_BU = 0x5b,
1034 OPC2_32_RR_MAX_H = 0x7a,
1035 OPC2_32_RR_MAX_HU = 0x7b,
1036 OPC2_32_RR_MIN = 0x19,
1037 OPC2_32_RR_MIN_U = 0x18,
1038 OPC2_32_RR_MIN_B = 0x58,
1039 OPC2_32_RR_MIN_BU = 0x59,
1040 OPC2_32_RR_MIN_H = 0x78,
1041 OPC2_32_RR_MIN_HU = 0x79,
1042 OPC2_32_RR_MOV = 0x1f,
1043 OPC2_32_RR_NE = 0x11,
1044 OPC2_32_RR_OR_EQ = 0x27,
1045 OPC2_32_RR_OR_GE = 0x2b,
1046 OPC2_32_RR_OR_GE_U = 0x2c,
1047 OPC2_32_RR_OR_LT = 0x29,
1048 OPC2_32_RR_OR_LT_U = 0x2a,
1049 OPC2_32_RR_OR_NE = 0x28,
1050 OPC2_32_RR_SAT_B = 0x5e,
1051 OPC2_32_RR_SAT_BU = 0x5f,
1052 OPC2_32_RR_SAT_H = 0x7e,
1053 OPC2_32_RR_SAT_HU = 0x7f,
1054 OPC2_32_RR_SH_EQ = 0x37,
1055 OPC2_32_RR_SH_GE = 0x3b,
1056 OPC2_32_RR_SH_GE_U = 0x3c,
1057 OPC2_32_RR_SH_LT = 0x39,
1058 OPC2_32_RR_SH_LT_U = 0x3a,
1059 OPC2_32_RR_SH_NE = 0x38,
1060 OPC2_32_RR_SUB = 0x08,
1061 OPC2_32_RR_SUB_B = 0x48,
1062 OPC2_32_RR_SUB_H = 0x68,
1063 OPC2_32_RR_SUBC = 0x0d,
1064 OPC2_32_RR_SUBS = 0x0a,
1065 OPC2_32_RR_SUBS_U = 0x0b,
1066 OPC2_32_RR_SUBS_H = 0x6a,
1067 OPC2_32_RR_SUBS_HU = 0x6b,
1068 OPC2_32_RR_SUBX = 0x0c,
1069 OPC2_32_RR_XOR_EQ = 0x2f,
1070 OPC2_32_RR_XOR_GE = 0x33,
1071 OPC2_32_RR_XOR_GE_U = 0x34,
1072 OPC2_32_RR_XOR_LT = 0x31,
1073 OPC2_32_RR_XOR_LT_U = 0x32,
1074 OPC2_32_RR_XOR_NE = 0x30,
1075 };
1076 /* OPCM_32_RR_ADRESS */
1077 enum {
1078 OPC2_32_RR_ADD_A = 0x01,
1079 OPC2_32_RR_ADDSC_A = 0x60,
1080 OPC2_32_RR_ADDSC_AT = 0x62,
1081 OPC2_32_RR_EQ_A = 0x40,
1082 OPC2_32_RR_EQZ = 0x48,
1083 OPC2_32_RR_GE_A = 0x43,
1084 OPC2_32_RR_LT_A = 0x42,
1085 OPC2_32_RR_MOV_A = 0x63,
1086 OPC2_32_RR_MOV_AA = 0x00,
1087 OPC2_32_RR_MOV_D = 0x4c,
1088 OPC2_32_RR_NE_A = 0x41,
1089 OPC2_32_RR_NEZ_A = 0x49,
1090 OPC2_32_RR_SUB_A = 0x02,
1091 };
1092 /* OPCM_32_RR_FLOAT */
1093 enum {
1094 OPC2_32_RR_BMERGE = 0x01,
1095 OPC2_32_RR_BSPLIT = 0x09,
1096 OPC2_32_RR_DVINIT_B = 0x5a,
1097 OPC2_32_RR_DVINIT_BU = 0x4a,
1098 OPC2_32_RR_DVINIT_H = 0x3a,
1099 OPC2_32_RR_DVINIT_HU = 0x2a,
1100 OPC2_32_RR_DVINIT = 0x1a,
1101 OPC2_32_RR_DVINIT_U = 0x0a,
1102 OPC2_32_RR_PARITY = 0x02,
1103 OPC2_32_RR_UNPACK = 0x08,
1104 };
1105 /* OPCM_32_RR_IDIRECT */
1106 enum {
1107 OPC2_32_RR_JI = 0x03,
1108 OPC2_32_RR_JLI = 0x02,
1109 OPC2_32_RR_CALLI = 0x00,
1110 };
1111 /*
1112 * RR1 Format
1113 */
1114 /* OPCM_32_RR1_MUL */
1115 enum {
1116 OPC2_32_RR1_MUL_H_32_LL = 0x1a,
1117 OPC2_32_RR1_MUL_H_32_LU = 0x19,
1118 OPC2_32_RR1_MUL_H_32_UL = 0x18,
1119 OPC2_32_RR1_MUL_H_32_UU = 0x1b,
1120 OPC2_32_RR1_MULM_H_64_LL = 0x1e,
1121 OPC2_32_RR1_MULM_H_64_LU = 0x1d,
1122 OPC2_32_RR1_MULM_H_64_UL = 0x1c,
1123 OPC2_32_RR1_MULM_H_64_UU = 0x1f,
1124 OPC2_32_RR1_MULR_H_16_LL = 0x0e,
1125 OPC2_32_RR1_MULR_H_16_LU = 0x0d,
1126 OPC2_32_RR1_MULR_H_16_UL = 0x0c,
1127 OPC2_32_RR1_MULR_H_16_UU = 0x0f,
1128 };
1129 /* OPCM_32_RR1_MULQ */
1130 enum {
1131 OPC2_32_RR1_MUL_Q_32 = 0x02,
1132 OPC2_32_RR1_MUL_Q_64 = 0x1b,
1133 OPC2_32_RR1_MUL_Q_32_L = 0x01,
1134 OPC2_32_RR1_MUL_Q_64_L = 0x19,
1135 OPC2_32_RR1_MUL_Q_32_U = 0x00,
1136 OPC2_32_RR1_MUL_Q_64_U = 0x18,
1137 OPC2_32_RR1_MUL_Q_32_LL = 0x05,
1138 OPC2_32_RR1_MUL_Q_32_UU = 0x04,
1139 OPC2_32_RR1_MULR_Q_32_L = 0x07,
1140 OPC2_32_RR1_MULR_Q_32_U = 0x06,
1141 };
1142 /*
1143 * RR2 Format
1144 */
1145 /* OPCM_32_RR2_MUL */
1146 enum {
1147 OPC2_32_RR2_MUL_32 = 0x0a,
1148 OPC2_32_RR2_MUL_64 = 0x6a,
1149 OPC2_32_RR2_MULS_32 = 0x8a,
1150 OPC2_32_RR2_MUL_U_64 = 0x68,
1151 OPC2_32_RR2_MULS_U_32 = 0x88,
1152 };
1153 /*
1154 * RRPW Format
1155 */
1156 /* OPCM_32_RRPW_EXTRACT_INSERT */
1157 enum {
1158
1159 OPC2_32_RRPW_EXTR = 0x02,
1160 OPC2_32_RRPW_EXTR_U = 0x03,
1161 OPC2_32_RRPW_IMASK = 0x01,
1162 OPC2_32_RRPW_INSERT = 0x00,
1163 };
1164 /*
1165 * RRR Format
1166 */
1167 /* OPCM_32_RRR_COND_SELECT */
1168 enum {
1169 OPC2_32_RRR_CADD = 0x00,
1170 OPC2_32_RRR_CADDN = 0x01,
1171 OPC2_32_RRR_CSUB = 0x02,
1172 OPC2_32_RRR_CSUBN = 0x03,
1173 OPC2_32_RRR_SEL = 0x04,
1174 OPC2_32_RRR_SELN = 0x05,
1175 };
1176 /* OPCM_32_RRR_FLOAT */
1177 enum {
1178 OPC2_32_RRR_DVADJ = 0x0d,
1179 OPC2_32_RRR_DVSTEP = 0x0f,
1180 OPC2_32_RRR_DVSTEP_U = 0x0e,
1181 OPC2_32_RRR_IXMAX = 0x0a,
1182 OPC2_32_RRR_IXMAX_U = 0x0b,
1183 OPC2_32_RRR_IXMIN = 0x08,
1184 OPC2_32_RRR_IXMIN_U = 0x09,
1185 OPC2_32_RRR_PACK = 0x00,
1186 };
1187 /*
1188 * RRR1 Format
1189 */
1190 /* OPCM_32_RRR1_MADD */
1191 enum {
1192 OPC2_32_RRR1_MADD_H_LL = 0x1a,
1193 OPC2_32_RRR1_MADD_H_LU = 0x19,
1194 OPC2_32_RRR1_MADD_H_UL = 0x18,
1195 OPC2_32_RRR1_MADD_H_UU = 0x1b,
1196 OPC2_32_RRR1_MADDS_H_LL = 0x3a,
1197 OPC2_32_RRR1_MADDS_H_LU = 0x39,
1198 OPC2_32_RRR1_MADDS_H_UL = 0x38,
1199 OPC2_32_RRR1_MADDS_H_UU = 0x3b,
1200 OPC2_32_RRR1_MADDM_H_LL = 0x1e,
1201 OPC2_32_RRR1_MADDM_H_LU = 0x1d,
1202 OPC2_32_RRR1_MADDM_H_UL = 0x1c,
1203 OPC2_32_RRR1_MADDM_H_UU = 0x1f,
1204 OPC2_32_RRR1_MADDMS_H_LL = 0x3e,
1205 OPC2_32_RRR1_MADDMS_H_LU = 0x3d,
1206 OPC2_32_RRR1_MADDMS_H_UL = 0x3c,
1207 OPC2_32_RRR1_MADDMS_H_UU = 0x3f,
1208 OPC2_32_RRR1_MADDR_H_LL = 0x0e,
1209 OPC2_32_RRR1_MADDR_H_LU = 0x0d,
1210 OPC2_32_RRR1_MADDR_H_UL = 0x0c,
1211 OPC2_32_RRR1_MADDR_H_UU = 0x0f,
1212 OPC2_32_RRR1_MADDRS_H_LL = 0x2e,
1213 OPC2_32_RRR1_MADDRS_H_LU = 0x2d,
1214 OPC2_32_RRR1_MADDRS_H_UL = 0x2c,
1215 OPC2_32_RRR1_MADDRS_H_UU = 0x2f,
1216 };
1217 /* OPCM_32_RRR1_MADDQ_H */
1218 enum {
1219 OPC2_32_RRR1_MADD_Q_32 = 0x02,
1220 OPC2_32_RRR1_MADD_Q_64 = 0x1b,
1221 OPC2_32_RRR1_MADD_Q_32_L = 0x01,
1222 OPC2_32_RRR1_MADD_Q_64_L = 0x19,
1223 OPC2_32_RRR1_MADD_Q_32_U = 0x00,
1224 OPC2_32_RRR1_MADD_Q_64_U = 0x18,
1225 OPC2_32_RRR1_MADD_Q_32_LL = 0x05,
1226 OPC2_32_RRR1_MADD_Q_64_LL = 0x1d,
1227 OPC2_32_RRR1_MADD_Q_32_UU = 0x04,
1228 OPC2_32_RRR1_MADD_Q_64_UU = 0x1c,
1229 OPC2_32_RRR1_MADDS_Q_32 = 0x22,
1230 OPC2_32_RRR1_MADDS_Q_64 = 0x3b,
1231 OPC2_32_RRR1_MADDS_Q_32_L = 0x21,
1232 OPC2_32_RRR1_MADDS_Q_64_L = 0x39,
1233 OPC2_32_RRR1_MADDS_Q_32_U = 0x20,
1234 OPC2_32_RRR1_MADDS_Q_64_U = 0x38,
1235 OPC2_32_RRR1_MADDS_Q_32_LL = 0x25,
1236 OPC2_32_RRR1_MADDS_Q_64_LL = 0x3d,
1237 OPC2_32_RRR1_MADDS_Q_32_UU = 0x24,
1238 OPC2_32_RRR1_MADDS_Q_64_UU = 0x3c,
1239 OPC2_32_RRR1_MADDR_H_16_UL = 0x1e,
1240 OPC2_32_RRR1_MADDRS_H_16_UL = 0x3e,
1241 OPC2_32_RRR1_MADDR_Q_32_L = 0x07,
1242 OPC2_32_RRR1_MADDR_Q_32_U = 0x06,
1243 OPC2_32_RRR1_MADDRS_Q_32_LL = 0x27,
1244 OPC2_32_RRR1_MADDRS_Q_32_UU = 0x26,
1245 };
1246 /* OPCM_32_RRR1_MADDSU_H */
1247 enum {
1248 OPC2_32_RRR1_MADDSU_H_32_LL = 0x1a,
1249 OPC2_32_RRR1_MADDSU_H_32_LU = 0x19,
1250 OPC2_32_RRR1_MADDSU_H_32_UL = 0x18,
1251 OPC2_32_RRR1_MADDSU_H_32_UU = 0x1b,
1252 OPC2_32_RRR1_MADDSUS_H_32_LL = 0x3a,
1253 OPC2_32_RRR1_MADDSUS_H_32_LU = 0x39,
1254 OPC2_32_RRR1_MADDSUS_H_32_UL = 0x38,
1255 OPC2_32_RRR1_MADDSUS_H_32_UU = 0x3b,
1256 OPC2_32_RRR1_MADDSUM_H_64_LL = 0x1e,
1257 OPC2_32_RRR1_MADDSUM_H_64_LU = 0x1d,
1258 OPC2_32_RRR1_MADDSUM_H_64_UL = 0x1c,
1259 OPC2_32_RRR1_MADDSUM_H_64_UU = 0x1f,
1260 OPC2_32_RRR1_MADDSUMS_H_64_LL = 0x3e,
1261 OPC2_32_RRR1_MADDSUMS_H_64_LU = 0x3d,
1262 OPC2_32_RRR1_MADDSUMS_H_64_UL = 0x3c,
1263 OPC2_32_RRR1_MADDSUMS_H_64_UU = 0x3f,
1264 OPC2_32_RRR1_MADDSUR_H_16_LL = 0x0e,
1265 OPC2_32_RRR1_MADDSUR_H_16_LU = 0x0d,
1266 OPC2_32_RRR1_MADDSUR_H_16_UL = 0x0c,
1267 OPC2_32_RRR1_MADDSUR_H_16_UU = 0x0f,
1268 OPC2_32_RRR1_MADDSURS_H_16_LL = 0x2e,
1269 OPC2_32_RRR1_MADDSURS_H_16_LU = 0x2d,
1270 OPC2_32_RRR1_MADDSURS_H_16_UL = 0x2c,
1271 OPC2_32_RRR1_MADDSURS_H_16_UU = 0x2f,
1272 };
1273 /* OPCM_32_RRR1_MSUB_H */
1274 enum {
1275 OPC2_32_RRR1_MSUB_H_32_LL = 0x1a,
1276 OPC2_32_RRR1_MSUB_H_32_LU = 0x19,
1277 OPC2_32_RRR1_MSUB_H_32_UL = 0x18,
1278 OPC2_32_RRR1_MSUB_H_32_UU = 0x1b,
1279 OPC2_32_RRR1_MSUBS_H_32_LL = 0x3a,
1280 OPC2_32_RRR1_MSUBS_H_32_LU = 0x39,
1281 OPC2_32_RRR1_MSUBS_H_32_UL = 0x38,
1282 OPC2_32_RRR1_MSUBS_H_32_UU = 0x3b,
1283 OPC2_32_RRR1_MSUBM_H_64_LL = 0x1e,
1284 OPC2_32_RRR1_MSUBM_H_64_LU = 0x1d,
1285 OPC2_32_RRR1_MSUBM_H_64_UL = 0x1c,
1286 OPC2_32_RRR1_MSUBM_H_64_UU = 0x1f,
1287 OPC2_32_RRR1_MSUBMS_H_64_LL = 0x3e,
1288 OPC2_32_RRR1_MSUBMS_H_64_LU = 0x3d,
1289 OPC2_32_RRR1_MSUBMS_H_64_UL = 0x3c,
1290 OPC2_32_RRR1_MSUBMS_H_64_UU = 0x3f,
1291 OPC2_32_RRR1_MSUBR_H_16_LL = 0x0e,
1292 OPC2_32_RRR1_MSUBR_H_16_LU = 0x0d,
1293 OPC2_32_RRR1_MSUBR_H_16_UL = 0x0c,
1294 OPC2_32_RRR1_MSUBR_H_16_UU = 0x0f,
1295 OPC2_32_RRR1_MSUBRS_H_16_LL = 0x2e,
1296 OPC2_32_RRR1_MSUBRS_H_16_LU = 0x2d,
1297 OPC2_32_RRR1_MSUBRS_H_16_UL = 0x2c,
1298 OPC2_32_RRR1_MSUBRS_H_16_UU = 0x2f,
1299 };
1300 /* OPCM_32_RRR1_MSUB_Q */
1301 enum {
1302 OPC2_32_RRR1_MSUB_Q_32 = 0x02,
1303 OPC2_32_RRR1_MSUB_Q_64 = 0x1b,
1304 OPC2_32_RRR1_MSUB_Q_32_L = 0x01,
1305 OPC2_32_RRR1_MSUB_Q_64_L = 0x19,
1306 OPC2_32_RRR1_MSUB_Q_32_U = 0x00,
1307 OPC2_32_RRR1_MSUB_Q_64_U = 0x18,
1308 OPC2_32_RRR1_MSUB_Q_32_LL = 0x05,
1309 OPC2_32_RRR1_MSUB_Q_64_LL = 0x1d,
1310 OPC2_32_RRR1_MSUB_Q_32_UU = 0x04,
1311 OPC2_32_RRR1_MSUB_Q_64_UU = 0x1c,
1312 OPC2_32_RRR1_MSUBS_Q_32 = 0x22,
1313 OPC2_32_RRR1_MSUBS_Q_64 = 0x3b,
1314 OPC2_32_RRR1_MSUBS_Q_32_L = 0x21,
1315 OPC2_32_RRR1_MSUBS_Q_64_L = 0x39,
1316 OPC2_32_RRR1_MSUBS_Q_32_U = 0x20,
1317 OPC2_32_RRR1_MSUBS_Q_64_U = 0x38,
1318 OPC2_32_RRR1_MSUBS_Q_32_LL = 0x25,
1319 OPC2_32_RRR1_MSUBS_Q_64_LL = 0x3d,
1320 OPC2_32_RRR1_MSUBS_Q_32_UU = 0x24,
1321 OPC2_32_RRR1_MSUBS_Q_64_UU = 0x3c,
1322 OPC2_32_RRR1_MSUBR_H_32_UL = 0x1e,
1323 OPC2_32_RRR1_MSUBRS_H_32_UL = 0x3e,
1324 OPC2_32_RRR1_MSUBR_Q_32_LL = 0x07,
1325 OPC2_32_RRR1_MSUBR_Q_32_UU = 0x06,
1326 OPC2_32_RRR1_MSUBRS_Q_32_LL = 0x27,
1327 OPC2_32_RRR1_MSUBRS_Q_32_UU = 0x26,
1328 };
1329 /* OPCM_32_RRR1_MSUBADS_H */
1330 enum {
1331 OPC2_32_RRR1_MSUBAD_H_32_LL = 0x1a,
1332 OPC2_32_RRR1_MSUBAD_H_32_LU = 0x19,
1333 OPC2_32_RRR1_MSUBAD_H_32_UL = 0x18,
1334 OPC2_32_RRR1_MSUBAD_H_32_UU = 0x1b,
1335 OPC2_32_RRR1_MSUBADS_H_32_LL = 0x3a,
1336 OPC2_32_RRR1_MSUBADS_H_32_LU = 0x39,
1337 OPC2_32_RRR1_MSUBADS_H_32_UL = 0x38,
1338 OPC2_32_RRR1_MSUBADS_H_32_UU = 0x3b,
1339 OPC2_32_RRR1_MSUBADM_H_64_LL = 0x1e,
1340 OPC2_32_RRR1_MSUBADM_H_64_LU = 0x1d,
1341 OPC2_32_RRR1_MSUBADM_H_64_UL = 0x1c,
1342 OPC2_32_RRR1_MSUBADM_H_64_UU = 0x1f,
1343 OPC2_32_RRR1_MSUBADMS_H_64_LL = 0x3e,
1344 OPC2_32_RRR1_MSUBADMS_H_64_LU = 0x3d,
1345 OPC2_32_RRR1_MSUBADMS_H_64_UL = 0x3c,
1346 OPC2_32_RRR1_MSUBADMS_H_16_UU = 0x3f,
1347 OPC2_32_RRR1_MSUBADR_H_16_LL = 0x0e,
1348 OPC2_32_RRR1_MSUBADR_H_16_LU = 0x0d,
1349 OPC2_32_RRR1_MSUBADR_H_16_UL = 0x0c,
1350 OPC2_32_RRR1_MSUBADR_H_16_UU = 0x0f,
1351 OPC2_32_RRR1_MSUBADRS_H_16_LL = 0x2e,
1352 OPC2_32_RRR1_MSUBADRS_H_16_LU = 0x2d,
1353 OPC2_32_RRR1_MSUBADRS_H_16_UL = 0x2c,
1354 OPC2_32_RRR1_MSUBADRS_H_16_UU = 0x2f,
1355 };
1356 /*
1357 * RRR2 Format
1358 */
1359 /* OPCM_32_RRR2_MADD */
1360 enum {
1361 OPC2_32_RRR2_MADD_32 = 0x0a,
1362 OPC2_32_RRR2_MADD_64 = 0x6a,
1363 OPC2_32_RRR2_MADDS_32 = 0x8a,
1364 OPC2_32_RRR2_MADDS_64 = 0xea,
1365 OPC2_32_RRR2_MADD_U_32 = 0x68,
1366 OPC2_32_RRR2_MADDS_U_32 = 0x88,
1367 OPC2_32_RRR2_MADDS_U_64 = 0xe8,
1368 };
1369 /* OPCM_32_RRR2_MSUB */
1370 enum {
1371 OPC2_32_RRR2_MSUB_32 = 0x0a,
1372 OPC2_32_RRR2_MSUB_64 = 0x6a,
1373 OPC2_32_RRR2_MSUBS_32 = 0x8a,
1374 OPC2_32_RRR2_MSUBS_64 = 0xea,
1375 OPC2_32_RRR2_MSUB_U_64 = 0x68,
1376 OPC2_32_RRR2_MSUBS_U_32 = 0x88,
1377 OPC2_32_RRR2_MSUBS_U_64 = 0xe8,
1378 };
1379 /*
1380 * RRRR Format
1381 */
1382 /* OPCM_32_RRRR_EXTRACT_INSERT */
1383 enum {
1384 OPC2_32_RRRR_DEXTR = 0x04,
1385 OPC2_32_RRRR_EXTR = 0x02,
1386 OPC2_32_RRRR_EXTR_U = 0x03,
1387 OPC2_32_RRRR_INSERT = 0x00,
1388 };
1389 /*
1390 * RRRW Format
1391 */
1392 /* OPCM_32_RRRW_EXTRACT_INSERT */
1393 enum {
1394 OPC2_32_RRRW_EXTR = 0x02,
1395 OPC2_32_RRRW_EXTR_U = 0x03,
1396 OPC2_32_RRRW_IMASK = 0x01,
1397 OPC2_32_RRRW_INSERT = 0x00,
1398 };
1399 /*
1400 * SYS Format
1401 */
1402 /* OPCM_32_SYS_INTERRUPTS */
1403 enum {
1404 OPC2_32_SYS_DEBUG = 0x04,
1405 OPC2_32_SYS_DISABLE = 0x0d,
1406 OPC2_32_SYS_DSYNC = 0x12,
1407 OPC2_32_SYS_ENABLE = 0x0c,
1408 OPC2_32_SYS_ISYNC = 0x13,
1409 OPC2_32_SYS_NOP = 0x00,
1410 OPC2_32_SYS_RET = 0x06,
1411 OPC2_32_SYS_RFE = 0x07,
1412 OPC2_32_SYS_RFM = 0x05,
1413 OPC2_32_SYS_RSLCX = 0x09,
1414 OPC2_32_SYS_SVLCX = 0x08,
1415 OPC2_32_SYS_TRAPSV = 0x15,
1416 OPC2_32_SYS_TRAPV = 0x14,
1417 };
Mirror of https://git.qemu.org/git/qemu.git