3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
11 #define MAX_HW_CFG_SIZE_V2 121 /* Max number of registers imx can set for v2 */
12 #define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */
13 #define APP_CODE_BARKER 0xB1
14 #define DCD_BARKER 0xB17219E9
17 * NOTE: This file must be kept in sync with arch/arm/include/asm/\
18 * imx-common/imximage.cfg because tools/imximage.c can not
19 * cross-include headers from arch/arm/ and vice-versa.
21 #define CMD_DATA_STR "DATA"
23 /* Initial Vector Table Offset */
24 #define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
25 #define FLASH_OFFSET_STANDARD 0x400
26 #define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD
27 #define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD
28 #define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD
29 #define FLASH_OFFSET_ONENAND 0x100
30 #define FLASH_OFFSET_NOR 0x1000
31 #define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD
33 /* Initial Load Region Size */
34 #define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF
35 #define FLASH_LOADSIZE_STANDARD 0x1000
36 #define FLASH_LOADSIZE_NAND FLASH_LOADSIZE_STANDARD
37 #define FLASH_LOADSIZE_SD FLASH_LOADSIZE_STANDARD
38 #define FLASH_LOADSIZE_SPI FLASH_LOADSIZE_STANDARD
39 #define FLASH_LOADSIZE_ONENAND 0x400
40 #define FLASH_LOADSIZE_NOR 0x0 /* entire image */
41 #define FLASH_LOADSIZE_SATA FLASH_LOADSIZE_STANDARD
43 #define IVT_HEADER_TAG 0xD1
44 #define IVT_VERSION 0x40
45 #define DCD_HEADER_TAG 0xD2
46 #define DCD_COMMAND_TAG 0xCC
47 #define DCD_VERSION 0x40
48 #define DCD_COMMAND_PARAM 0x4
59 enum imximage_fld_types
{
67 enum imximage_version
{
68 IMXIMAGE_VER_INVALID
= -1,
74 uint32_t type
; /* Type of pointer (byte, halfword, word, wait/read) */
75 uint32_t addr
; /* Address to write to */
76 uint32_t value
; /* Data to write */
77 } dcd_type_addr_data_t
;
80 uint32_t barker
; /* Barker for sanity check */
81 uint32_t length
; /* Device configuration length (without preamble) */
85 dcd_preamble_t preamble
;
86 dcd_type_addr_data_t addr_data
[MAX_HW_CFG_SIZE_V1
];
90 uint32_t app_code_jump_vector
;
91 uint32_t app_code_barker
;
92 uint32_t app_code_csf
;
94 uint32_t super_root_key
;
96 uint32_t app_dest_ptr
;
100 uint32_t length
; /* Length of data to be read from flash */
104 flash_header_v1_t fhdr
;
106 flash_cfg_parms_t ext_header
;
118 } __attribute__((packed
)) ivt_header_t
;
124 } __attribute__((packed
)) write_dcd_command_t
;
128 write_dcd_command_t write_dcd_command
;
129 dcd_addr_data_t addr_data
[MAX_HW_CFG_SIZE_V2
];
143 uint32_t boot_data_ptr
;
150 flash_header_v2_t fhdr
;
151 boot_data_t boot_data
;
155 /* The header must be aligned to 4k on MX53 for NAND boot */
158 imx_header_v1_t hdr_v1
;
159 imx_header_v2_t hdr_v2
;
163 typedef void (*set_dcd_val_t
)(struct imx_header
*imxhdr
,
164 char *name
, int lineno
,
165 int fld
, uint32_t value
,
168 typedef void (*set_dcd_rst_t
)(struct imx_header
*imxhdr
,
170 char *name
, int lineno
);
172 typedef void (*set_imx_hdr_t
)(struct imx_header
*imxhdr
, uint32_t dcd_len
,
173 uint32_t entry_point
, uint32_t flash_offset
);
175 #endif /* _IMXIMAGE_H_ */