3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
11 #define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 */
12 #define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */
13 #define APP_CODE_BARKER 0xB1
14 #define DCD_BARKER 0xB17219E9
17 * NOTE: This file must be kept in sync with arch/arm/include/asm/\
18 * imx-common/imximage.cfg because tools/imximage.c can not
19 * cross-include headers from arch/arm/ and vice-versa.
21 #define CMD_DATA_STR "DATA"
23 /* Initial Vector Table Offset */
24 #define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
25 #define FLASH_OFFSET_STANDARD 0x400
26 #define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD
27 #define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD
28 #define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD
29 #define FLASH_OFFSET_ONENAND 0x100
30 #define FLASH_OFFSET_NOR 0x1000
31 #define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD
32 #define FLASH_OFFSET_QSPI 0x1000
34 /* Initial Load Region Size */
35 #define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF
36 #define FLASH_LOADSIZE_STANDARD 0x1000
37 #define FLASH_LOADSIZE_NAND FLASH_LOADSIZE_STANDARD
38 #define FLASH_LOADSIZE_SD FLASH_LOADSIZE_STANDARD
39 #define FLASH_LOADSIZE_SPI FLASH_LOADSIZE_STANDARD
40 #define FLASH_LOADSIZE_ONENAND 0x400
41 #define FLASH_LOADSIZE_NOR 0x0 /* entire image */
42 #define FLASH_LOADSIZE_SATA FLASH_LOADSIZE_STANDARD
43 #define FLASH_LOADSIZE_QSPI 0x0 /* entire image */
45 #define IVT_HEADER_TAG 0xD1
46 #define IVT_VERSION 0x40
47 #define DCD_HEADER_TAG 0xD2
48 #define DCD_COMMAND_TAG 0xCC
49 #define DCD_VERSION 0x40
50 #define DCD_COMMAND_PARAM 0x4
61 enum imximage_fld_types
{
69 enum imximage_version
{
70 IMXIMAGE_VER_INVALID
= -1,
76 uint32_t type
; /* Type of pointer (byte, halfword, word, wait/read) */
77 uint32_t addr
; /* Address to write to */
78 uint32_t value
; /* Data to write */
79 } dcd_type_addr_data_t
;
82 uint32_t barker
; /* Barker for sanity check */
83 uint32_t length
; /* Device configuration length (without preamble) */
87 dcd_preamble_t preamble
;
88 dcd_type_addr_data_t addr_data
[MAX_HW_CFG_SIZE_V1
];
92 uint32_t app_code_jump_vector
;
93 uint32_t app_code_barker
;
94 uint32_t app_code_csf
;
96 uint32_t super_root_key
;
98 uint32_t app_dest_ptr
;
102 uint32_t length
; /* Length of data to be read from flash */
106 flash_header_v1_t fhdr
;
108 flash_cfg_parms_t ext_header
;
120 } __attribute__((packed
)) ivt_header_t
;
126 } __attribute__((packed
)) write_dcd_command_t
;
130 write_dcd_command_t write_dcd_command
;
131 dcd_addr_data_t addr_data
[MAX_HW_CFG_SIZE_V2
];
145 uint32_t boot_data_ptr
;
152 flash_header_v2_t fhdr
;
153 boot_data_t boot_data
;
157 /* The header must be aligned to 4k on MX53 for NAND boot */
160 imx_header_v1_t hdr_v1
;
161 imx_header_v2_t hdr_v2
;
165 typedef void (*set_dcd_val_t
)(struct imx_header
*imxhdr
,
166 char *name
, int lineno
,
167 int fld
, uint32_t value
,
170 typedef void (*set_dcd_rst_t
)(struct imx_header
*imxhdr
,
172 char *name
, int lineno
);
174 typedef void (*set_imx_hdr_t
)(struct imx_header
*imxhdr
, uint32_t dcd_len
,
175 uint32_t entry_point
, uint32_t flash_offset
);
177 #endif /* _IMXIMAGE_H_ */