tools/kwbimage.h

   1 /*
   2  * (C) Copyright 2008
   3  * Marvell Semiconductor <www.marvell.com>
   4  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef _KWBIMAGE_H_
  10 #define _KWBIMAGE_H_
  11
  12 #include <stdint.h>
  13
  14 #define KWBIMAGE_MAX_CONFIG     ((0x1dc - 0x20)/sizeof(struct reg_config))
  15 #define MAX_TEMPBUF_LEN         32
  16
  17 /* NAND ECC Mode */
  18 #define IBR_HDR_ECC_DEFAULT             0x00
  19 #define IBR_HDR_ECC_FORCED_HAMMING      0x01
  20 #define IBR_HDR_ECC_FORCED_RS           0x02
  21 #define IBR_HDR_ECC_DISABLED            0x03
  22
  23 /* Boot Type - block ID */
  24 #define IBR_HDR_I2C_ID                  0x4D
  25 #define IBR_HDR_SPI_ID                  0x5A
  26 #define IBR_HDR_NAND_ID                 0x8B
  27 #define IBR_HDR_SATA_ID                 0x78
  28 #define IBR_HDR_PEX_ID                  0x9C
  29 #define IBR_HDR_UART_ID                 0x69
  30 #define IBR_DEF_ATTRIB                  0x00
  31
  32 #define ALIGN_SUP(x, a) (((x) + (a - 1)) & ~(a - 1))
  33
  34 /* Structure of the main header, version 0 (Kirkwood, Dove) */
  35 struct main_hdr_v0 {
  36         uint8_t  blockid;               /*0     */
  37         uint8_t  nandeccmode;           /*1     */
  38         uint16_t nandpagesize;          /*2-3   */
  39         uint32_t blocksize;             /*4-7   */
  40         uint32_t rsvd1;                 /*8-11  */
  41         uint32_t srcaddr;               /*12-15 */
  42         uint32_t destaddr;              /*16-19 */
  43         uint32_t execaddr;              /*20-23 */
  44         uint8_t  satapiomode;           /*24    */
  45         uint8_t  rsvd3;                 /*25    */
  46         uint16_t ddrinitdelay;          /*26-27 */
  47         uint16_t rsvd2;                 /*28-29 */
  48         uint8_t  ext;                   /*30    */
  49         uint8_t  checksum;              /*31    */
  50 };
  51
  52 struct ext_hdr_v0_reg {
  53         uint32_t raddr;
  54         uint32_t rdata;
  55 };
  56
  57 #define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg))
  58
  59 struct ext_hdr_v0 {
  60         uint32_t              offset;
  61         uint8_t               reserved[0x20 - sizeof(uint32_t)];
  62         struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT];
  63         uint8_t               reserved2[7];
  64         uint8_t               checksum;
  65 };
  66
  67 struct kwb_header {
  68         struct main_hdr_v0      kwb_hdr;
  69         struct ext_hdr_v0       kwb_exthdr;
  70 };
  71
  72 /* Structure of the main header, version 1 (Armada 370, Armada XP) */
  73 struct main_hdr_v1 {
  74         uint8_t  blockid;               /* 0 */
  75         uint8_t  reserved1;             /* 1 */
  76         uint16_t reserved2;             /* 2-3 */
  77         uint32_t blocksize;             /* 4-7 */
  78         uint8_t  version;               /* 8 */
  79         uint8_t  headersz_msb;          /* 9 */
  80         uint16_t headersz_lsb;          /* A-B */
  81         uint32_t srcaddr;               /* C-F */
  82         uint32_t destaddr;              /* 10-13 */
  83         uint32_t execaddr;              /* 14-17 */
  84         uint8_t  reserved3;             /* 18 */
  85         uint8_t  nandblocksize;         /* 19 */
  86         uint8_t  nandbadblklocation;    /* 1A */
  87         uint8_t  reserved4;             /* 1B */
  88         uint16_t reserved5;             /* 1C-1D */
  89         uint8_t  ext;                   /* 1E */
  90         uint8_t  checksum;              /* 1F */
  91 };
  92
  93 /*
  94  * Header for the optional headers, version 1 (Armada 370, Armada XP)
  95  */
  96 struct opt_hdr_v1 {
  97         uint8_t  headertype;
  98         uint8_t  headersz_msb;
  99         uint16_t headersz_lsb;
 100         char     data[0];
 101 };
 102
 103 /*
 104  * Various values for the opt_hdr_v1->headertype field, describing the
 105  * different types of optional headers. The "secure" header contains
 106  * informations related to secure boot (encryption keys, etc.). The
 107  * "binary" header contains ARM binary code to be executed prior to
 108  * executing the main payload (usually the bootloader). This is
 109  * typically used to execute DDR3 training code. The "register" header
 110  * allows to describe a set of (address, value) tuples that are
 111  * generally used to configure the DRAM controller.
 112  */
 113 #define OPT_HDR_V1_SECURE_TYPE   0x1
 114 #define OPT_HDR_V1_BINARY_TYPE   0x2
 115 #define OPT_HDR_V1_REGISTER_TYPE 0x3
 116
 117 #define KWBHEADER_V1_SIZE(hdr) \
 118         (((hdr)->headersz_msb << 16) | (hdr)->headersz_lsb)
 119
 120 enum kwbimage_cmd {
 121         CMD_INVALID,
 122         CMD_BOOT_FROM,
 123         CMD_NAND_ECC_MODE,
 124         CMD_NAND_PAGE_SIZE,
 125         CMD_SATA_PIO_MODE,
 126         CMD_DDR_INIT_DELAY,
 127         CMD_DATA
 128 };
 129
 130 enum kwbimage_cmd_types {
 131         CFG_INVALID = -1,
 132         CFG_COMMAND,
 133         CFG_DATA0,
 134         CFG_DATA1
 135 };
 136
 137 /*
 138  * functions
 139  */
 140 void init_kwb_image_type (void);
 141
 142 /*
 143  * Byte 8 of the image header contains the version number. In the v0
 144  * header, byte 8 was reserved, and always set to 0. In the v1 header,
 145  * byte 8 has been changed to a proper field, set to 1.
 146  */
 147 static inline unsigned int image_version(void *header)
 148 {
 149         unsigned char *ptr = header;
 150         return ptr[8];
 151 }
 152
 153 #endif /* _KWBIMAGE_H_ */