tools/perf/Documentation/perf-c2c.txt

   1 perf-c2c(1)
   2 ===========
   3
   4 NAME
   5 ----
   6 perf-c2c - Shared Data C2C/HITM Analyzer.
   7
   8 SYNOPSIS
   9 --------
  10 [verse]
  11 'perf c2c record' [<options>] <command>
  12 'perf c2c record' [<options>] -- [<record command options>] <command>
  13 'perf c2c report' [<options>]
  14
  15 DESCRIPTION
  16 -----------
  17 C2C stands for Cache To Cache.
  18
  19 The perf c2c tool provides means for Shared Data C2C/HITM analysis. It allows
  20 you to track down the cacheline contentions.
  21
  22 On x86, the tool is based on load latency and precise store facility events
  23 provided by Intel CPUs. On PowerPC, the tool uses random instruction sampling
  24 with thresholding feature.
  25
  26 These events provide:
  27   - memory address of the access
  28   - type of the access (load and store details)
  29   - latency (in cycles) of the load access
  30
  31 The c2c tool provide means to record this data and report back access details
  32 for cachelines with highest contention - highest number of HITM accesses.
  33
  34 The basic workflow with this tool follows the standard record/report phase.
  35 User uses the record command to record events data and report command to
  36 display it.
  37
  38
  39 RECORD OPTIONS
  40 --------------
  41 -e::
  42 --event=::
  43         Select the PMU event. Use 'perf mem record -e list'
  44         to list available events.
  45
  46 -v::
  47 --verbose::
  48         Be more verbose (show counter open errors, etc).
  49
  50 -l::
  51 --ldlat::
  52         Configure mem-loads latency. (x86 only)
  53
  54 -k::
  55 --all-kernel::
  56         Configure all used events to run in kernel space.
  57
  58 -u::
  59 --all-user::
  60         Configure all used events to run in user space.
  61
  62 REPORT OPTIONS
  63 --------------
  64 -k::
  65 --vmlinux=<file>::
  66         vmlinux pathname
  67
  68 -v::
  69 --verbose::
  70         Be more verbose (show counter open errors, etc).
  71
  72 -i::
  73 --input::
  74         Specify the input file to process.
  75
  76 -N::
  77 --node-info::
  78         Show extra node info in report (see NODE INFO section)
  79
  80 -c::
  81 --coalesce::
  82         Specify sorting fields for single cacheline display.
  83         Following fields are available: tid,pid,iaddr,dso
  84         (see COALESCE)
  85
  86 -g::
  87 --call-graph::
  88         Setup callchains parameters.
  89         Please refer to perf-report man page for details.
  90
  91 --stdio::
  92         Force the stdio output (see STDIO OUTPUT)
  93
  94 --stats::
  95         Display only statistic tables and force stdio mode.
  96
  97 --full-symbols::
  98         Display full length of symbols.
  99
 100 --no-source::
 101         Do not display Source:Line column.
 102
 103 --show-all::
 104         Show all captured HITM lines, with no regard to HITM % 0.0005 limit.
 105
 106 -f::
 107 --force::
 108         Don't do ownership validation.
 109
 110 -d::
 111 --display::
 112         Switch to HITM type (rmt, lcl) to display and sort on. Total HITMs as default.
 113
 114 --stitch-lbr::
 115         Show callgraph with stitched LBRs, which may have more complete
 116         callgraph. The perf.data file must have been obtained using
 117         perf c2c record --call-graph lbr.
 118         Disabled by default. In common cases with call stack overflows,
 119         it can recreate better call stacks than the default lbr call stack
 120         output. But this approach is not full proof. There can be cases
 121         where it creates incorrect call stacks from incorrect matches.
 122         The known limitations include exception handing such as
 123         setjmp/longjmp will have calls/returns not match.
 124
 125 C2C RECORD
 126 ----------
 127 The perf c2c record command setup options related to HITM cacheline analysis
 128 and calls standard perf record command.
 129
 130 Following perf record options are configured by default:
 131 (check perf record man page for details)
 132
 133   -W,-d,--phys-data,--sample-cpu
 134
 135 Unless specified otherwise with '-e' option, following events are monitored by
 136 default on x86:
 137
 138   cpu/mem-loads,ldlat=30/P
 139   cpu/mem-stores/P
 140
 141 and following on PowerPC:
 142
 143   cpu/mem-loads/
 144   cpu/mem-stores/
 145
 146 User can pass any 'perf record' option behind '--' mark, like (to enable
 147 callchains and system wide monitoring):
 148
 149   $ perf c2c record -- -g -a
 150
 151 Please check RECORD OPTIONS section for specific c2c record options.
 152
 153 C2C REPORT
 154 ----------
 155 The perf c2c report command displays shared data analysis.  It comes in two
 156 display modes: stdio and tui (default).
 157
 158 The report command workflow is following:
 159   - sort all the data based on the cacheline address
 160   - store access details for each cacheline
 161   - sort all cachelines based on user settings
 162   - display data
 163
 164 In general perf report output consist of 2 basic views:
 165   1) most expensive cachelines list
 166   2) offsets details for each cacheline
 167
 168 For each cacheline in the 1) list we display following data:
 169 (Both stdio and TUI modes follow the same fields output)
 170
 171   Index
 172   - zero based index to identify the cacheline
 173
 174   Cacheline
 175   - cacheline address (hex number)
 176
 177   Total records
 178   - sum of all cachelines accesses
 179
 180   Rmt/Lcl Hitm
 181   - cacheline percentage of all Remote/Local HITM accesses
 182
 183   LLC Load Hitm - Total, Lcl, Rmt
 184   - count of Total/Local/Remote load HITMs
 185
 186   Store Reference - Total, L1Hit, L1Miss
 187     Total - all store accesses
 188     L1Hit - store accesses that hit L1
 189     L1Hit - store accesses that missed L1
 190
 191   Load Dram
 192   - count of local and remote DRAM accesses
 193
 194   LLC Ld Miss
 195   - count of all accesses that missed LLC
 196
 197   Total Loads
 198   - sum of all load accesses
 199
 200   Core Load Hit - FB, L1, L2
 201   - count of load hits in FB (Fill Buffer), L1 and L2 cache
 202
 203   LLC Load Hit - Llc, Rmt
 204   - count of LLC and Remote load hits
 205
 206 For each offset in the 2) list we display following data:
 207
 208   HITM - Rmt, Lcl
 209   - % of Remote/Local HITM accesses for given offset within cacheline
 210
 211   Store Refs - L1 Hit, L1 Miss
 212   - % of store accesses that hit/missed L1 for given offset within cacheline
 213
 214   Data address - Offset
 215   - offset address
 216
 217   Pid
 218   - pid of the process responsible for the accesses
 219
 220   Tid
 221   - tid of the process responsible for the accesses
 222
 223   Code address
 224   - code address responsible for the accesses
 225
 226   cycles - rmt hitm, lcl hitm, load
 227     - sum of cycles for given accesses - Remote/Local HITM and generic load
 228
 229   cpu cnt
 230     - number of cpus that participated on the access
 231
 232   Symbol
 233     - code symbol related to the 'Code address' value
 234
 235   Shared Object
 236     - shared object name related to the 'Code address' value
 237
 238   Source:Line
 239     - source information related to the 'Code address' value
 240
 241   Node
 242     - nodes participating on the access (see NODE INFO section)
 243
 244 NODE INFO
 245 ---------
 246 The 'Node' field displays nodes that accesses given cacheline
 247 offset. Its output comes in 3 flavors:
 248   - node IDs separated by ','
 249   - node IDs with stats for each ID, in following format:
 250       Node{cpus %hitms %stores}
 251   - node IDs with list of affected CPUs in following format:
 252       Node{cpu list}
 253
 254 User can switch between above flavors with -N option or
 255 use 'n' key to interactively switch in TUI mode.
 256
 257 COALESCE
 258 --------
 259 User can specify how to sort offsets for cacheline.
 260
 261 Following fields are available and governs the final
 262 output fields set for caheline offsets output:
 263
 264   tid   - coalesced by process TIDs
 265   pid   - coalesced by process PIDs
 266   iaddr - coalesced by code address, following fields are displayed:
 267              Code address, Code symbol, Shared Object, Source line
 268   dso   - coalesced by shared object
 269
 270 By default the coalescing is setup with 'pid,iaddr'.
 271
 272 STDIO OUTPUT
 273 ------------
 274 The stdio output displays data on standard output.
 275
 276 Following tables are displayed:
 277   Trace Event Information
 278   - overall statistics of memory accesses
 279
 280   Global Shared Cache Line Event Information
 281   - overall statistics on shared cachelines
 282
 283   Shared Data Cache Line Table
 284   - list of most expensive cachelines
 285
 286   Shared Cache Line Distribution Pareto
 287   - list of all accessed offsets for each cacheline
 288
 289 TUI OUTPUT
 290 ----------
 291 The TUI output provides interactive interface to navigate
 292 through cachelines list and to display offset details.
 293
 294 For details please refer to the help window by pressing '?' key.
 295
 296 CREDITS
 297 -------
 298 Although Don Zickus, Dick Fowles and Joe Mario worked together
 299 to get this implemented, we got lots of early help from Arnaldo
 300 Carvalho de Melo, Stephane Eranian, Jiri Olsa and Andi Kleen.
 301
 302 C2C BLOG
 303 --------
 304 Check Joe's blog on c2c tool for detailed use case explanation:
 305   https://joemario.github.io/blog/2016/09/01/c2c-blog/
 306
 307 SEE ALSO
 308 --------
 309 linkperf:perf-record[1], linkperf:perf-mem[1]