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tools/power turbostat: Fix added raw MSR output
[thirdparty/kernel/stable.git] / tools / power / x86 / turbostat / turbostat.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * turbostat -- show CPU frequency and C-state residency
4 * on modern Intel and AMD processors.
5 *
6 * Copyright (c) 2023 Intel Corporation.
7 * Len Brown <len.brown@intel.com>
8 */
9
10 #define _GNU_SOURCE
11 #include MSRHEADER
12 #include INTEL_FAMILY_HEADER
13 #include <stdarg.h>
14 #include <stdio.h>
15 #include <err.h>
16 #include <unistd.h>
17 #include <sys/types.h>
18 #include <sys/wait.h>
19 #include <sys/stat.h>
20 #include <sys/select.h>
21 #include <sys/resource.h>
22 #include <fcntl.h>
23 #include <signal.h>
24 #include <sys/time.h>
25 #include <stdlib.h>
26 #include <getopt.h>
27 #include <dirent.h>
28 #include <string.h>
29 #include <ctype.h>
30 #include <sched.h>
31 #include <time.h>
32 #include <cpuid.h>
33 #include <sys/capability.h>
34 #include <errno.h>
35 #include <math.h>
36 #include <linux/perf_event.h>
37 #include <asm/unistd.h>
38 #include <stdbool.h>
39
40 #define UNUSED(x) (void)(x)
41
42 /*
43 * This list matches the column headers, except
44 * 1. built-in only, the sysfs counters are not here -- we learn of those at run-time
45 * 2. Core and CPU are moved to the end, we can't have strings that contain them
46 * matching on them for --show and --hide.
47 */
48
49 /*
50 * buffer size used by sscanf() for added column names
51 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters
52 */
53 #define NAME_BYTES 20
54 #define PATH_BYTES 128
55
56 enum counter_scope { SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE };
57 enum counter_type { COUNTER_ITEMS, COUNTER_CYCLES, COUNTER_SECONDS, COUNTER_USEC };
58 enum counter_format { FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT };
59
60 struct msr_counter {
61 unsigned int msr_num;
62 char name[NAME_BYTES];
63 char path[PATH_BYTES];
64 unsigned int width;
65 enum counter_type type;
66 enum counter_format format;
67 struct msr_counter *next;
68 unsigned int flags;
69 #define FLAGS_HIDE (1 << 0)
70 #define FLAGS_SHOW (1 << 1)
71 #define SYSFS_PERCPU (1 << 1)
72 };
73
74 struct msr_counter bic[] = {
75 { 0x0, "usec", "", 0, 0, 0, NULL, 0 },
76 { 0x0, "Time_Of_Day_Seconds", "", 0, 0, 0, NULL, 0 },
77 { 0x0, "Package", "", 0, 0, 0, NULL, 0 },
78 { 0x0, "Node", "", 0, 0, 0, NULL, 0 },
79 { 0x0, "Avg_MHz", "", 0, 0, 0, NULL, 0 },
80 { 0x0, "Busy%", "", 0, 0, 0, NULL, 0 },
81 { 0x0, "Bzy_MHz", "", 0, 0, 0, NULL, 0 },
82 { 0x0, "TSC_MHz", "", 0, 0, 0, NULL, 0 },
83 { 0x0, "IRQ", "", 0, 0, 0, NULL, 0 },
84 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL, 0 },
85 { 0x0, "sysfs", "", 0, 0, 0, NULL, 0 },
86 { 0x0, "CPU%c1", "", 0, 0, 0, NULL, 0 },
87 { 0x0, "CPU%c3", "", 0, 0, 0, NULL, 0 },
88 { 0x0, "CPU%c6", "", 0, 0, 0, NULL, 0 },
89 { 0x0, "CPU%c7", "", 0, 0, 0, NULL, 0 },
90 { 0x0, "ThreadC", "", 0, 0, 0, NULL, 0 },
91 { 0x0, "CoreTmp", "", 0, 0, 0, NULL, 0 },
92 { 0x0, "CoreCnt", "", 0, 0, 0, NULL, 0 },
93 { 0x0, "PkgTmp", "", 0, 0, 0, NULL, 0 },
94 { 0x0, "GFX%rc6", "", 0, 0, 0, NULL, 0 },
95 { 0x0, "GFXMHz", "", 0, 0, 0, NULL, 0 },
96 { 0x0, "Pkg%pc2", "", 0, 0, 0, NULL, 0 },
97 { 0x0, "Pkg%pc3", "", 0, 0, 0, NULL, 0 },
98 { 0x0, "Pkg%pc6", "", 0, 0, 0, NULL, 0 },
99 { 0x0, "Pkg%pc7", "", 0, 0, 0, NULL, 0 },
100 { 0x0, "Pkg%pc8", "", 0, 0, 0, NULL, 0 },
101 { 0x0, "Pkg%pc9", "", 0, 0, 0, NULL, 0 },
102 { 0x0, "Pk%pc10", "", 0, 0, 0, NULL, 0 },
103 { 0x0, "CPU%LPI", "", 0, 0, 0, NULL, 0 },
104 { 0x0, "SYS%LPI", "", 0, 0, 0, NULL, 0 },
105 { 0x0, "PkgWatt", "", 0, 0, 0, NULL, 0 },
106 { 0x0, "CorWatt", "", 0, 0, 0, NULL, 0 },
107 { 0x0, "GFXWatt", "", 0, 0, 0, NULL, 0 },
108 { 0x0, "PkgCnt", "", 0, 0, 0, NULL, 0 },
109 { 0x0, "RAMWatt", "", 0, 0, 0, NULL, 0 },
110 { 0x0, "PKG_%", "", 0, 0, 0, NULL, 0 },
111 { 0x0, "RAM_%", "", 0, 0, 0, NULL, 0 },
112 { 0x0, "Pkg_J", "", 0, 0, 0, NULL, 0 },
113 { 0x0, "Cor_J", "", 0, 0, 0, NULL, 0 },
114 { 0x0, "GFX_J", "", 0, 0, 0, NULL, 0 },
115 { 0x0, "RAM_J", "", 0, 0, 0, NULL, 0 },
116 { 0x0, "Mod%c6", "", 0, 0, 0, NULL, 0 },
117 { 0x0, "Totl%C0", "", 0, 0, 0, NULL, 0 },
118 { 0x0, "Any%C0", "", 0, 0, 0, NULL, 0 },
119 { 0x0, "GFX%C0", "", 0, 0, 0, NULL, 0 },
120 { 0x0, "CPUGFX%", "", 0, 0, 0, NULL, 0 },
121 { 0x0, "Core", "", 0, 0, 0, NULL, 0 },
122 { 0x0, "CPU", "", 0, 0, 0, NULL, 0 },
123 { 0x0, "APIC", "", 0, 0, 0, NULL, 0 },
124 { 0x0, "X2APIC", "", 0, 0, 0, NULL, 0 },
125 { 0x0, "Die", "", 0, 0, 0, NULL, 0 },
126 { 0x0, "GFXAMHz", "", 0, 0, 0, NULL, 0 },
127 { 0x0, "IPC", "", 0, 0, 0, NULL, 0 },
128 { 0x0, "CoreThr", "", 0, 0, 0, NULL, 0 },
129 { 0x0, "UncMHz", "", 0, 0, 0, NULL, 0 },
130 };
131
132 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter))
133 #define BIC_USEC (1ULL << 0)
134 #define BIC_TOD (1ULL << 1)
135 #define BIC_Package (1ULL << 2)
136 #define BIC_Node (1ULL << 3)
137 #define BIC_Avg_MHz (1ULL << 4)
138 #define BIC_Busy (1ULL << 5)
139 #define BIC_Bzy_MHz (1ULL << 6)
140 #define BIC_TSC_MHz (1ULL << 7)
141 #define BIC_IRQ (1ULL << 8)
142 #define BIC_SMI (1ULL << 9)
143 #define BIC_sysfs (1ULL << 10)
144 #define BIC_CPU_c1 (1ULL << 11)
145 #define BIC_CPU_c3 (1ULL << 12)
146 #define BIC_CPU_c6 (1ULL << 13)
147 #define BIC_CPU_c7 (1ULL << 14)
148 #define BIC_ThreadC (1ULL << 15)
149 #define BIC_CoreTmp (1ULL << 16)
150 #define BIC_CoreCnt (1ULL << 17)
151 #define BIC_PkgTmp (1ULL << 18)
152 #define BIC_GFX_rc6 (1ULL << 19)
153 #define BIC_GFXMHz (1ULL << 20)
154 #define BIC_Pkgpc2 (1ULL << 21)
155 #define BIC_Pkgpc3 (1ULL << 22)
156 #define BIC_Pkgpc6 (1ULL << 23)
157 #define BIC_Pkgpc7 (1ULL << 24)
158 #define BIC_Pkgpc8 (1ULL << 25)
159 #define BIC_Pkgpc9 (1ULL << 26)
160 #define BIC_Pkgpc10 (1ULL << 27)
161 #define BIC_CPU_LPI (1ULL << 28)
162 #define BIC_SYS_LPI (1ULL << 29)
163 #define BIC_PkgWatt (1ULL << 30)
164 #define BIC_CorWatt (1ULL << 31)
165 #define BIC_GFXWatt (1ULL << 32)
166 #define BIC_PkgCnt (1ULL << 33)
167 #define BIC_RAMWatt (1ULL << 34)
168 #define BIC_PKG__ (1ULL << 35)
169 #define BIC_RAM__ (1ULL << 36)
170 #define BIC_Pkg_J (1ULL << 37)
171 #define BIC_Cor_J (1ULL << 38)
172 #define BIC_GFX_J (1ULL << 39)
173 #define BIC_RAM_J (1ULL << 40)
174 #define BIC_Mod_c6 (1ULL << 41)
175 #define BIC_Totl_c0 (1ULL << 42)
176 #define BIC_Any_c0 (1ULL << 43)
177 #define BIC_GFX_c0 (1ULL << 44)
178 #define BIC_CPUGFX (1ULL << 45)
179 #define BIC_Core (1ULL << 46)
180 #define BIC_CPU (1ULL << 47)
181 #define BIC_APIC (1ULL << 48)
182 #define BIC_X2APIC (1ULL << 49)
183 #define BIC_Die (1ULL << 50)
184 #define BIC_GFXACTMHz (1ULL << 51)
185 #define BIC_IPC (1ULL << 52)
186 #define BIC_CORE_THROT_CNT (1ULL << 53)
187 #define BIC_UNCORE_MHZ (1ULL << 54)
188
189 #define BIC_TOPOLOGY (BIC_Package | BIC_Node | BIC_CoreCnt | BIC_PkgCnt | BIC_Core | BIC_CPU | BIC_Die )
190 #define BIC_THERMAL_PWR ( BIC_CoreTmp | BIC_PkgTmp | BIC_PkgWatt | BIC_CorWatt | BIC_GFXWatt | BIC_RAMWatt | BIC_PKG__ | BIC_RAM__)
191 #define BIC_FREQUENCY ( BIC_Avg_MHz | BIC_Busy | BIC_Bzy_MHz | BIC_TSC_MHz | BIC_GFXMHz | BIC_GFXACTMHz | BIC_UNCORE_MHZ)
192 #define BIC_IDLE ( BIC_sysfs | BIC_CPU_c1 | BIC_CPU_c3 | BIC_CPU_c6 | BIC_CPU_c7 | BIC_GFX_rc6 | BIC_Pkgpc2 | BIC_Pkgpc3 | BIC_Pkgpc6 | BIC_Pkgpc7 | BIC_Pkgpc8 | BIC_Pkgpc9 | BIC_Pkgpc10 | BIC_CPU_LPI | BIC_SYS_LPI | BIC_Mod_c6 | BIC_Totl_c0 | BIC_Any_c0 | BIC_GFX_c0 | BIC_CPUGFX)
193 #define BIC_OTHER ( BIC_IRQ | BIC_SMI | BIC_ThreadC | BIC_CoreTmp | BIC_IPC)
194
195 #define BIC_DISABLED_BY_DEFAULT (BIC_USEC | BIC_TOD | BIC_APIC | BIC_X2APIC)
196
197 unsigned long long bic_enabled = (0xFFFFFFFFFFFFFFFFULL & ~BIC_DISABLED_BY_DEFAULT);
198 unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_sysfs | BIC_APIC | BIC_X2APIC;
199
200 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME)
201 #define DO_BIC_READ(COUNTER_NAME) (bic_present & COUNTER_NAME)
202 #define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME)
203 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT)
204 #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT)
205 #define BIC_IS_ENABLED(COUNTER_BIT) (bic_enabled & COUNTER_BIT)
206
207 char *proc_stat = "/proc/stat";
208 FILE *outf;
209 int *fd_percpu;
210 int *fd_instr_count_percpu;
211 struct timeval interval_tv = { 5, 0 };
212 struct timespec interval_ts = { 5, 0 };
213
214 unsigned int num_iterations;
215 unsigned int header_iterations;
216 unsigned int debug;
217 unsigned int quiet;
218 unsigned int shown;
219 unsigned int sums_need_wide_columns;
220 unsigned int rapl_joules;
221 unsigned int summary_only;
222 unsigned int list_header_only;
223 unsigned int dump_only;
224 unsigned int has_aperf;
225 unsigned int has_epb;
226 unsigned int has_turbo;
227 unsigned int is_hybrid;
228 unsigned int units = 1000000; /* MHz etc */
229 unsigned int genuine_intel;
230 unsigned int authentic_amd;
231 unsigned int hygon_genuine;
232 unsigned int max_level, max_extended_level;
233 unsigned int has_invariant_tsc;
234 unsigned int aperf_mperf_multiplier = 1;
235 double bclk;
236 double base_hz;
237 unsigned int has_base_hz;
238 double tsc_tweak = 1.0;
239 unsigned int show_pkg_only;
240 unsigned int show_core_only;
241 char *output_buffer, *outp;
242 unsigned int do_dts;
243 unsigned int do_ptm;
244 unsigned int do_ipc;
245 unsigned long long gfx_cur_rc6_ms;
246 unsigned long long cpuidle_cur_cpu_lpi_us;
247 unsigned long long cpuidle_cur_sys_lpi_us;
248 unsigned int gfx_cur_mhz;
249 unsigned int gfx_act_mhz;
250 unsigned int tj_max;
251 unsigned int tj_max_override;
252 double rapl_power_units, rapl_time_units;
253 double rapl_dram_energy_units, rapl_energy_units;
254 double rapl_joule_counter_range;
255 unsigned int crystal_hz;
256 unsigned long long tsc_hz;
257 int base_cpu;
258 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */
259 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */
260 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */
261 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */
262 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */
263 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */
264 unsigned int first_counter_read = 1;
265 int ignore_stdin;
266
267 int get_msr(int cpu, off_t offset, unsigned long long *msr);
268
269 /* Model specific support Start */
270
271 /* List of features that may diverge among different platforms */
272 struct platform_features {
273 bool has_msr_misc_feature_control; /* MSR_MISC_FEATURE_CONTROL */
274 bool has_msr_misc_pwr_mgmt; /* MSR_MISC_PWR_MGMT */
275 bool has_nhm_msrs; /* MSR_PLATFORM_INFO, MSR_IA32_TEMPERATURE_TARGET, MSR_SMI_COUNT, MSR_PKG_CST_CONFIG_CONTROL, MSR_IA32_POWER_CTL, TRL MSRs */
276 bool has_config_tdp; /* MSR_CONFIG_TDP_NOMINAL/LEVEL_1/LEVEL_2/CONTROL, MSR_TURBO_ACTIVATION_RATIO */
277 int bclk_freq; /* CPU base clock */
278 int crystal_freq; /* Crystal clock to use when not available from CPUID.15 */
279 int supported_cstates; /* Core cstates and Package cstates supported */
280 int cst_limit; /* MSR_PKG_CST_CONFIG_CONTROL */
281 bool has_cst_auto_convension; /* AUTOMATIC_CSTATE_CONVERSION bit in MSR_PKG_CST_CONFIG_CONTROL */
282 bool has_irtl_msrs; /* MSR_PKGC3/PKGC6/PKGC7/PKGC8/PKGC9/PKGC10_IRTL */
283 bool has_msr_core_c1_res; /* MSR_CORE_C1_RES */
284 bool has_msr_module_c6_res_ms; /* MSR_MODULE_C6_RES_MS */
285 bool has_msr_c6_demotion_policy_config; /* MSR_CC6_DEMOTION_POLICY_CONFIG/MSR_MC6_DEMOTION_POLICY_CONFIG */
286 bool has_msr_atom_pkg_c6_residency; /* MSR_ATOM_PKG_C6_RESIDENCY */
287 bool has_msr_knl_core_c6_residency; /* MSR_KNL_CORE_C6_RESIDENCY */
288 bool has_ext_cst_msrs; /* MSR_PKG_WEIGHTED_CORE_C0_RES/MSR_PKG_ANY_CORE_C0_RES/MSR_PKG_ANY_GFXE_C0_RES/MSR_PKG_BOTH_CORE_GFXE_C0_RES */
289 bool has_cst_prewake_bit; /* Cstate prewake bit in MSR_IA32_POWER_CTL */
290 int trl_msrs; /* MSR_TURBO_RATIO_LIMIT/LIMIT1/LIMIT2/SECONDARY, Atom TRL MSRs */
291 int plr_msrs; /* MSR_CORE/GFX/RING_PERF_LIMIT_REASONS */
292 int rapl_msrs; /* RAPL PKG/DRAM/CORE/GFX MSRs, AMD RAPL MSRs */
293 bool has_per_core_rapl; /* Indicates cores energy collection is per-core, not per-package. AMD specific for now */
294 bool has_rapl_divisor; /* Divisor for Energy unit raw value from MSR_RAPL_POWER_UNIT */
295 bool has_fixed_rapl_unit; /* Fixed Energy Unit used for DRAM RAPL Domain */
296 int rapl_quirk_tdp; /* Hardcoded TDP value when cannot be retrieved from hardware */
297 int tcc_offset_bits; /* TCC Offset bits in MSR_IA32_TEMPERATURE_TARGET */
298 bool enable_tsc_tweak; /* Use CPU Base freq instead of TSC freq for aperf/mperf counter */
299 bool need_perf_multiplier; /* mperf/aperf multiplier */
300 };
301
302 struct platform_data {
303 unsigned int model;
304 const struct platform_features *features;
305 };
306
307 /* For BCLK */
308 enum bclk_freq {
309 BCLK_100MHZ = 1,
310 BCLK_133MHZ,
311 BCLK_SLV,
312 };
313
314 #define SLM_BCLK_FREQS 5
315 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0 };
316
317 double slm_bclk(void)
318 {
319 unsigned long long msr = 3;
320 unsigned int i;
321 double freq;
322
323 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr))
324 fprintf(outf, "SLM BCLK: unknown\n");
325
326 i = msr & 0xf;
327 if (i >= SLM_BCLK_FREQS) {
328 fprintf(outf, "SLM BCLK[%d] invalid\n", i);
329 i = 3;
330 }
331 freq = slm_freq_table[i];
332
333 if (!quiet)
334 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq);
335
336 return freq;
337 }
338
339 /* For Package cstate limit */
340 enum package_cstate_limit {
341 CST_LIMIT_NHM = 1,
342 CST_LIMIT_SNB,
343 CST_LIMIT_HSW,
344 CST_LIMIT_SKX,
345 CST_LIMIT_ICX,
346 CST_LIMIT_SLV,
347 CST_LIMIT_AMT,
348 CST_LIMIT_KNL,
349 CST_LIMIT_GMT,
350 };
351
352 /* For Turbo Ratio Limit MSRs */
353 enum turbo_ratio_limit_msrs {
354 TRL_BASE = BIT(0),
355 TRL_LIMIT1 = BIT(1),
356 TRL_LIMIT2 = BIT(2),
357 TRL_ATOM = BIT(3),
358 TRL_KNL = BIT(4),
359 TRL_CORECOUNT = BIT(5),
360 };
361
362 /* For Perf Limit Reason MSRs */
363 enum perf_limit_reason_msrs {
364 PLR_CORE = BIT(0),
365 PLR_GFX = BIT(1),
366 PLR_RING = BIT(2),
367 };
368
369 /* For RAPL MSRs */
370 enum rapl_msrs {
371 RAPL_PKG_POWER_LIMIT = BIT(0), /* 0x610 MSR_PKG_POWER_LIMIT */
372 RAPL_PKG_ENERGY_STATUS = BIT(1), /* 0x611 MSR_PKG_ENERGY_STATUS */
373 RAPL_PKG_PERF_STATUS = BIT(2), /* 0x613 MSR_PKG_PERF_STATUS */
374 RAPL_PKG_POWER_INFO = BIT(3), /* 0x614 MSR_PKG_POWER_INFO */
375 RAPL_DRAM_POWER_LIMIT = BIT(4), /* 0x618 MSR_DRAM_POWER_LIMIT */
376 RAPL_DRAM_ENERGY_STATUS = BIT(5), /* 0x619 MSR_DRAM_ENERGY_STATUS */
377 RAPL_DRAM_PERF_STATUS = BIT(6), /* 0x61b MSR_DRAM_PERF_STATUS */
378 RAPL_DRAM_POWER_INFO = BIT(7), /* 0x61c MSR_DRAM_POWER_INFO */
379 RAPL_CORE_POWER_LIMIT = BIT(8), /* 0x638 MSR_PP0_POWER_LIMIT */
380 RAPL_CORE_ENERGY_STATUS = BIT(9), /* 0x639 MSR_PP0_ENERGY_STATUS */
381 RAPL_CORE_POLICY = BIT(10), /* 0x63a MSR_PP0_POLICY */
382 RAPL_GFX_POWER_LIMIT = BIT(11), /* 0x640 MSR_PP1_POWER_LIMIT */
383 RAPL_GFX_ENERGY_STATUS = BIT(12), /* 0x641 MSR_PP1_ENERGY_STATUS */
384 RAPL_GFX_POLICY = BIT(13), /* 0x642 MSR_PP1_POLICY */
385 RAPL_AMD_PWR_UNIT = BIT(14), /* 0xc0010299 MSR_AMD_RAPL_POWER_UNIT */
386 RAPL_AMD_CORE_ENERGY_STAT = BIT(15), /* 0xc001029a MSR_AMD_CORE_ENERGY_STATUS */
387 RAPL_AMD_PKG_ENERGY_STAT = BIT(16), /* 0xc001029b MSR_AMD_PKG_ENERGY_STATUS */
388 };
389
390 #define RAPL_PKG (RAPL_PKG_ENERGY_STATUS | RAPL_PKG_POWER_LIMIT)
391 #define RAPL_DRAM (RAPL_DRAM_ENERGY_STATUS | RAPL_DRAM_POWER_LIMIT)
392 #define RAPL_CORE (RAPL_CORE_ENERGY_STATUS | RAPL_CORE_POWER_LIMIT)
393 #define RAPL_GFX (RAPL_GFX_POWER_LIMIT | RAPL_GFX_ENERGY_STATUS)
394
395 #define RAPL_PKG_ALL (RAPL_PKG | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO)
396 #define RAPL_DRAM_ALL (RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_DRAM_POWER_INFO)
397 #define RAPL_CORE_ALL (RAPL_CORE | RAPL_CORE_POLICY)
398 #define RAPL_GFX_ALL (RAPL_GFX | RAPL_GFX_POLIGY)
399
400 #define RAPL_AMD_F17H (RAPL_AMD_PWR_UNIT | RAPL_AMD_CORE_ENERGY_STAT | RAPL_AMD_PKG_ENERGY_STAT)
401
402 /* For Cstates */
403 enum cstates {
404 CC1 = BIT(0),
405 CC3 = BIT(1),
406 CC6 = BIT(2),
407 CC7 = BIT(3),
408 PC2 = BIT(4),
409 PC3 = BIT(5),
410 PC6 = BIT(6),
411 PC7 = BIT(7),
412 PC8 = BIT(8),
413 PC9 = BIT(9),
414 PC10 = BIT(10),
415 };
416
417 static const struct platform_features nhm_features = {
418 .has_msr_misc_pwr_mgmt = 1,
419 .has_nhm_msrs = 1,
420 .bclk_freq = BCLK_133MHZ,
421 .supported_cstates = CC1 | CC3 | CC6 | PC3 | PC6,
422 .cst_limit = CST_LIMIT_NHM,
423 .trl_msrs = TRL_BASE,
424 };
425
426 static const struct platform_features nhx_features = {
427 .has_msr_misc_pwr_mgmt = 1,
428 .has_nhm_msrs = 1,
429 .bclk_freq = BCLK_133MHZ,
430 .supported_cstates = CC1 | CC3 | CC6 | PC3 | PC6,
431 .cst_limit = CST_LIMIT_NHM,
432 };
433
434 static const struct platform_features snb_features = {
435 .has_msr_misc_feature_control = 1,
436 .has_msr_misc_pwr_mgmt = 1,
437 .has_nhm_msrs = 1,
438 .bclk_freq = BCLK_100MHZ,
439 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7,
440 .cst_limit = CST_LIMIT_SNB,
441 .has_irtl_msrs = 1,
442 .trl_msrs = TRL_BASE,
443 .rapl_msrs = RAPL_PKG | RAPL_CORE_ALL | RAPL_GFX | RAPL_PKG_POWER_INFO,
444 };
445
446 static const struct platform_features snx_features = {
447 .has_msr_misc_feature_control = 1,
448 .has_msr_misc_pwr_mgmt = 1,
449 .has_nhm_msrs = 1,
450 .bclk_freq = BCLK_100MHZ,
451 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7,
452 .cst_limit = CST_LIMIT_SNB,
453 .has_irtl_msrs = 1,
454 .trl_msrs = TRL_BASE,
455 .rapl_msrs = RAPL_PKG_ALL | RAPL_CORE_ALL | RAPL_DRAM_ALL,
456 };
457
458 static const struct platform_features ivb_features = {
459 .has_msr_misc_feature_control = 1,
460 .has_msr_misc_pwr_mgmt = 1,
461 .has_nhm_msrs = 1,
462 .has_config_tdp = 1,
463 .bclk_freq = BCLK_100MHZ,
464 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7,
465 .cst_limit = CST_LIMIT_SNB,
466 .has_irtl_msrs = 1,
467 .trl_msrs = TRL_BASE,
468 .rapl_msrs = RAPL_PKG | RAPL_CORE_ALL | RAPL_GFX | RAPL_PKG_POWER_INFO,
469 };
470
471 static const struct platform_features ivx_features = {
472 .has_msr_misc_feature_control = 1,
473 .has_msr_misc_pwr_mgmt = 1,
474 .has_nhm_msrs = 1,
475 .bclk_freq = BCLK_100MHZ,
476 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7,
477 .cst_limit = CST_LIMIT_SNB,
478 .has_irtl_msrs = 1,
479 .trl_msrs = TRL_BASE | TRL_LIMIT1,
480 .rapl_msrs = RAPL_PKG_ALL | RAPL_CORE_ALL | RAPL_DRAM_ALL,
481 };
482
483 static const struct platform_features hsw_features = {
484 .has_msr_misc_feature_control = 1,
485 .has_msr_misc_pwr_mgmt = 1,
486 .has_nhm_msrs = 1,
487 .has_config_tdp = 1,
488 .bclk_freq = BCLK_100MHZ,
489 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7,
490 .cst_limit = CST_LIMIT_HSW,
491 .has_irtl_msrs = 1,
492 .trl_msrs = TRL_BASE,
493 .plr_msrs = PLR_CORE | PLR_GFX | PLR_RING,
494 .rapl_msrs = RAPL_PKG | RAPL_CORE_ALL | RAPL_GFX | RAPL_PKG_POWER_INFO,
495 };
496
497 static const struct platform_features hsx_features = {
498 .has_msr_misc_feature_control = 1,
499 .has_msr_misc_pwr_mgmt = 1,
500 .has_nhm_msrs = 1,
501 .has_config_tdp = 1,
502 .bclk_freq = BCLK_100MHZ,
503 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7,
504 .cst_limit = CST_LIMIT_HSW,
505 .has_irtl_msrs = 1,
506 .trl_msrs = TRL_BASE | TRL_LIMIT1 | TRL_LIMIT2,
507 .plr_msrs = PLR_CORE | PLR_RING,
508 .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL,
509 .has_fixed_rapl_unit = 1,
510 };
511
512 static const struct platform_features hswl_features = {
513 .has_msr_misc_feature_control = 1,
514 .has_msr_misc_pwr_mgmt = 1,
515 .has_nhm_msrs = 1,
516 .has_config_tdp = 1,
517 .bclk_freq = BCLK_100MHZ,
518 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7 | PC8 | PC9 | PC10,
519 .cst_limit = CST_LIMIT_HSW,
520 .has_irtl_msrs = 1,
521 .trl_msrs = TRL_BASE,
522 .plr_msrs = PLR_CORE | PLR_GFX | PLR_RING,
523 .rapl_msrs = RAPL_PKG | RAPL_CORE_ALL | RAPL_GFX | RAPL_PKG_POWER_INFO,
524 };
525
526 static const struct platform_features hswg_features = {
527 .has_msr_misc_feature_control = 1,
528 .has_msr_misc_pwr_mgmt = 1,
529 .has_nhm_msrs = 1,
530 .has_config_tdp = 1,
531 .bclk_freq = BCLK_100MHZ,
532 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7,
533 .cst_limit = CST_LIMIT_HSW,
534 .has_irtl_msrs = 1,
535 .trl_msrs = TRL_BASE,
536 .plr_msrs = PLR_CORE | PLR_GFX | PLR_RING,
537 .rapl_msrs = RAPL_PKG | RAPL_CORE_ALL | RAPL_GFX | RAPL_PKG_POWER_INFO,
538 };
539
540 static const struct platform_features bdw_features = {
541 .has_msr_misc_feature_control = 1,
542 .has_msr_misc_pwr_mgmt = 1,
543 .has_nhm_msrs = 1,
544 .has_config_tdp = 1,
545 .bclk_freq = BCLK_100MHZ,
546 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7 | PC8 | PC9 | PC10,
547 .cst_limit = CST_LIMIT_HSW,
548 .has_irtl_msrs = 1,
549 .trl_msrs = TRL_BASE,
550 .rapl_msrs = RAPL_PKG | RAPL_CORE_ALL | RAPL_GFX | RAPL_PKG_POWER_INFO,
551 };
552
553 static const struct platform_features bdwg_features = {
554 .has_msr_misc_feature_control = 1,
555 .has_msr_misc_pwr_mgmt = 1,
556 .has_nhm_msrs = 1,
557 .has_config_tdp = 1,
558 .bclk_freq = BCLK_100MHZ,
559 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7,
560 .cst_limit = CST_LIMIT_HSW,
561 .has_irtl_msrs = 1,
562 .trl_msrs = TRL_BASE,
563 .rapl_msrs = RAPL_PKG | RAPL_CORE_ALL | RAPL_GFX | RAPL_PKG_POWER_INFO,
564 };
565
566 static const struct platform_features bdx_features = {
567 .has_msr_misc_feature_control = 1,
568 .has_msr_misc_pwr_mgmt = 1,
569 .has_nhm_msrs = 1,
570 .has_config_tdp = 1,
571 .bclk_freq = BCLK_100MHZ,
572 .supported_cstates = CC1 | CC3 | CC6 | PC2 | PC3 | PC6,
573 .cst_limit = CST_LIMIT_HSW,
574 .has_irtl_msrs = 1,
575 .has_cst_auto_convension = 1,
576 .trl_msrs = TRL_BASE,
577 .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL,
578 .has_fixed_rapl_unit = 1,
579 };
580
581 static const struct platform_features skl_features = {
582 .has_msr_misc_feature_control = 1,
583 .has_msr_misc_pwr_mgmt = 1,
584 .has_nhm_msrs = 1,
585 .has_config_tdp = 1,
586 .bclk_freq = BCLK_100MHZ,
587 .crystal_freq = 24000000,
588 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7 | PC8 | PC9 | PC10,
589 .cst_limit = CST_LIMIT_HSW,
590 .has_irtl_msrs = 1,
591 .has_ext_cst_msrs = 1,
592 .trl_msrs = TRL_BASE,
593 .tcc_offset_bits = 6,
594 .rapl_msrs = RAPL_PKG_ALL | RAPL_CORE_ALL | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_GFX,
595 .enable_tsc_tweak = 1,
596 };
597
598 static const struct platform_features cnl_features = {
599 .has_msr_misc_feature_control = 1,
600 .has_msr_misc_pwr_mgmt = 1,
601 .has_nhm_msrs = 1,
602 .has_config_tdp = 1,
603 .bclk_freq = BCLK_100MHZ,
604 .supported_cstates = CC1 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7 | PC8 | PC9 | PC10,
605 .cst_limit = CST_LIMIT_HSW,
606 .has_irtl_msrs = 1,
607 .has_msr_core_c1_res = 1,
608 .has_ext_cst_msrs = 1,
609 .trl_msrs = TRL_BASE,
610 .tcc_offset_bits = 6,
611 .rapl_msrs = RAPL_PKG_ALL | RAPL_CORE_ALL | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_GFX,
612 .enable_tsc_tweak = 1,
613 };
614
615 static const struct platform_features adl_features = {
616 .has_msr_misc_feature_control = 1,
617 .has_msr_misc_pwr_mgmt = 1,
618 .has_nhm_msrs = 1,
619 .has_config_tdp = 1,
620 .bclk_freq = BCLK_100MHZ,
621 .supported_cstates = CC1 | CC6 | CC7 | PC2 | PC3 | PC6 | PC8 | PC10,
622 .cst_limit = CST_LIMIT_HSW,
623 .has_irtl_msrs = 1,
624 .has_msr_core_c1_res = 1,
625 .has_ext_cst_msrs = 1,
626 .trl_msrs = TRL_BASE,
627 .tcc_offset_bits = 6,
628 .rapl_msrs = RAPL_PKG_ALL | RAPL_CORE_ALL | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_GFX,
629 .enable_tsc_tweak = 1,
630 };
631
632 static const struct platform_features skx_features = {
633 .has_msr_misc_feature_control = 1,
634 .has_msr_misc_pwr_mgmt = 1,
635 .has_nhm_msrs = 1,
636 .has_config_tdp = 1,
637 .bclk_freq = BCLK_100MHZ,
638 .supported_cstates = CC1 | CC6 | PC2 | PC6,
639 .cst_limit = CST_LIMIT_SKX,
640 .has_irtl_msrs = 1,
641 .has_cst_auto_convension = 1,
642 .trl_msrs = TRL_BASE | TRL_CORECOUNT,
643 .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL,
644 .has_fixed_rapl_unit = 1,
645 };
646
647 static const struct platform_features icx_features = {
648 .has_msr_misc_feature_control = 1,
649 .has_msr_misc_pwr_mgmt = 1,
650 .has_nhm_msrs = 1,
651 .has_config_tdp = 1,
652 .bclk_freq = BCLK_100MHZ,
653 .supported_cstates = CC1 | CC6 | PC2 | PC6,
654 .cst_limit = CST_LIMIT_ICX,
655 .has_irtl_msrs = 1,
656 .has_cst_prewake_bit = 1,
657 .trl_msrs = TRL_BASE | TRL_CORECOUNT,
658 .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL,
659 .has_fixed_rapl_unit = 1,
660 };
661
662 static const struct platform_features spr_features = {
663 .has_msr_misc_feature_control = 1,
664 .has_msr_misc_pwr_mgmt = 1,
665 .has_nhm_msrs = 1,
666 .has_config_tdp = 1,
667 .bclk_freq = BCLK_100MHZ,
668 .supported_cstates = CC1 | CC6 | PC2 | PC6,
669 .cst_limit = CST_LIMIT_SKX,
670 .has_msr_core_c1_res = 1,
671 .has_irtl_msrs = 1,
672 .has_cst_prewake_bit = 1,
673 .trl_msrs = TRL_BASE | TRL_CORECOUNT,
674 .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL,
675 };
676
677 static const struct platform_features srf_features = {
678 .has_msr_misc_feature_control = 1,
679 .has_msr_misc_pwr_mgmt = 1,
680 .has_nhm_msrs = 1,
681 .has_config_tdp = 1,
682 .bclk_freq = BCLK_100MHZ,
683 .supported_cstates = CC1 | CC6 | PC2 | PC6,
684 .cst_limit = CST_LIMIT_SKX,
685 .has_msr_core_c1_res = 1,
686 .has_msr_module_c6_res_ms = 1,
687 .has_irtl_msrs = 1,
688 .has_cst_prewake_bit = 1,
689 .trl_msrs = TRL_BASE | TRL_CORECOUNT,
690 .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL,
691 };
692
693 static const struct platform_features grr_features = {
694 .has_msr_misc_feature_control = 1,
695 .has_msr_misc_pwr_mgmt = 1,
696 .has_nhm_msrs = 1,
697 .has_config_tdp = 1,
698 .bclk_freq = BCLK_100MHZ,
699 .supported_cstates = CC1 | CC6,
700 .cst_limit = CST_LIMIT_SKX,
701 .has_msr_core_c1_res = 1,
702 .has_msr_module_c6_res_ms = 1,
703 .has_irtl_msrs = 1,
704 .has_cst_prewake_bit = 1,
705 .trl_msrs = TRL_BASE | TRL_CORECOUNT,
706 .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL,
707 };
708
709 static const struct platform_features slv_features = {
710 .has_nhm_msrs = 1,
711 .bclk_freq = BCLK_SLV,
712 .supported_cstates = CC1 | CC6 | PC6,
713 .cst_limit = CST_LIMIT_SLV,
714 .has_msr_core_c1_res = 1,
715 .has_msr_module_c6_res_ms = 1,
716 .has_msr_c6_demotion_policy_config = 1,
717 .has_msr_atom_pkg_c6_residency = 1,
718 .trl_msrs = TRL_ATOM,
719 .rapl_msrs = RAPL_PKG | RAPL_CORE,
720 .has_rapl_divisor = 1,
721 .rapl_quirk_tdp = 30,
722 };
723
724 static const struct platform_features slvd_features = {
725 .has_msr_misc_pwr_mgmt = 1,
726 .has_nhm_msrs = 1,
727 .bclk_freq = BCLK_SLV,
728 .supported_cstates = CC1 | CC6 | PC3 | PC6,
729 .cst_limit = CST_LIMIT_SLV,
730 .has_msr_atom_pkg_c6_residency = 1,
731 .trl_msrs = TRL_BASE,
732 .rapl_msrs = RAPL_PKG | RAPL_CORE,
733 .rapl_quirk_tdp = 30,
734 };
735
736 static const struct platform_features amt_features = {
737 .has_nhm_msrs = 1,
738 .bclk_freq = BCLK_133MHZ,
739 .supported_cstates = CC1 | CC3 | CC6 | PC3 | PC6,
740 .cst_limit = CST_LIMIT_AMT,
741 .trl_msrs = TRL_BASE,
742 };
743
744 static const struct platform_features gmt_features = {
745 .has_msr_misc_pwr_mgmt = 1,
746 .has_nhm_msrs = 1,
747 .bclk_freq = BCLK_100MHZ,
748 .crystal_freq = 19200000,
749 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7 | PC8 | PC9 | PC10,
750 .cst_limit = CST_LIMIT_GMT,
751 .has_irtl_msrs = 1,
752 .trl_msrs = TRL_BASE | TRL_CORECOUNT,
753 .rapl_msrs = RAPL_PKG | RAPL_PKG_POWER_INFO,
754 };
755
756 static const struct platform_features gmtd_features = {
757 .has_msr_misc_pwr_mgmt = 1,
758 .has_nhm_msrs = 1,
759 .bclk_freq = BCLK_100MHZ,
760 .crystal_freq = 25000000,
761 .supported_cstates = CC1 | CC6 | PC2 | PC6,
762 .cst_limit = CST_LIMIT_GMT,
763 .has_irtl_msrs = 1,
764 .has_msr_core_c1_res = 1,
765 .trl_msrs = TRL_BASE | TRL_CORECOUNT,
766 .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL | RAPL_CORE_ENERGY_STATUS,
767 };
768
769 static const struct platform_features gmtp_features = {
770 .has_msr_misc_pwr_mgmt = 1,
771 .has_nhm_msrs = 1,
772 .bclk_freq = BCLK_100MHZ,
773 .crystal_freq = 19200000,
774 .supported_cstates = CC1 | CC3 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7 | PC8 | PC9 | PC10,
775 .cst_limit = CST_LIMIT_GMT,
776 .has_irtl_msrs = 1,
777 .trl_msrs = TRL_BASE,
778 .rapl_msrs = RAPL_PKG | RAPL_PKG_POWER_INFO,
779 };
780
781 static const struct platform_features tmt_features = {
782 .has_msr_misc_pwr_mgmt = 1,
783 .has_nhm_msrs = 1,
784 .bclk_freq = BCLK_100MHZ,
785 .supported_cstates = CC1 | CC6 | CC7 | PC2 | PC3 | PC6 | PC7 | PC8 | PC9 | PC10,
786 .cst_limit = CST_LIMIT_GMT,
787 .has_irtl_msrs = 1,
788 .trl_msrs = TRL_BASE,
789 .rapl_msrs = RAPL_PKG_ALL | RAPL_CORE_ALL | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_GFX,
790 .enable_tsc_tweak = 1,
791 };
792
793 static const struct platform_features tmtd_features = {
794 .has_msr_misc_pwr_mgmt = 1,
795 .has_nhm_msrs = 1,
796 .bclk_freq = BCLK_100MHZ,
797 .supported_cstates = CC1 | CC6,
798 .cst_limit = CST_LIMIT_GMT,
799 .has_irtl_msrs = 1,
800 .trl_msrs = TRL_BASE | TRL_CORECOUNT,
801 .rapl_msrs = RAPL_PKG_ALL,
802 };
803
804 static const struct platform_features knl_features = {
805 .has_msr_misc_pwr_mgmt = 1,
806 .has_nhm_msrs = 1,
807 .has_config_tdp = 1,
808 .bclk_freq = BCLK_100MHZ,
809 .supported_cstates = CC1 | CC6 | PC3 | PC6,
810 .cst_limit = CST_LIMIT_KNL,
811 .has_msr_knl_core_c6_residency = 1,
812 .trl_msrs = TRL_KNL,
813 .rapl_msrs = RAPL_PKG_ALL | RAPL_DRAM_ALL,
814 .has_fixed_rapl_unit = 1,
815 .need_perf_multiplier = 1,
816 };
817
818 static const struct platform_features default_features = {
819 };
820
821 static const struct platform_features amd_features_with_rapl = {
822 .rapl_msrs = RAPL_AMD_F17H,
823 .has_per_core_rapl = 1,
824 .rapl_quirk_tdp = 280, /* This is the max stock TDP of HEDT/Server Fam17h+ chips */
825 };
826
827 static const struct platform_data turbostat_pdata[] = {
828 { INTEL_FAM6_NEHALEM, &nhm_features },
829 { INTEL_FAM6_NEHALEM_G, &nhm_features },
830 { INTEL_FAM6_NEHALEM_EP, &nhm_features },
831 { INTEL_FAM6_NEHALEM_EX, &nhx_features },
832 { INTEL_FAM6_WESTMERE, &nhm_features },
833 { INTEL_FAM6_WESTMERE_EP, &nhm_features },
834 { INTEL_FAM6_WESTMERE_EX, &nhx_features },
835 { INTEL_FAM6_SANDYBRIDGE, &snb_features },
836 { INTEL_FAM6_SANDYBRIDGE_X, &snx_features },
837 { INTEL_FAM6_IVYBRIDGE, &ivb_features },
838 { INTEL_FAM6_IVYBRIDGE_X, &ivx_features },
839 { INTEL_FAM6_HASWELL, &hsw_features },
840 { INTEL_FAM6_HASWELL_X, &hsx_features },
841 { INTEL_FAM6_HASWELL_L, &hswl_features },
842 { INTEL_FAM6_HASWELL_G, &hswg_features },
843 { INTEL_FAM6_BROADWELL, &bdw_features },
844 { INTEL_FAM6_BROADWELL_G, &bdwg_features },
845 { INTEL_FAM6_BROADWELL_X, &bdx_features },
846 { INTEL_FAM6_BROADWELL_D, &bdx_features },
847 { INTEL_FAM6_SKYLAKE_L, &skl_features },
848 { INTEL_FAM6_SKYLAKE, &skl_features },
849 { INTEL_FAM6_SKYLAKE_X, &skx_features },
850 { INTEL_FAM6_KABYLAKE_L, &skl_features },
851 { INTEL_FAM6_KABYLAKE, &skl_features },
852 { INTEL_FAM6_COMETLAKE, &skl_features },
853 { INTEL_FAM6_COMETLAKE_L, &skl_features },
854 { INTEL_FAM6_CANNONLAKE_L, &cnl_features },
855 { INTEL_FAM6_ICELAKE_X, &icx_features },
856 { INTEL_FAM6_ICELAKE_D, &icx_features },
857 { INTEL_FAM6_ICELAKE_L, &cnl_features },
858 { INTEL_FAM6_ICELAKE_NNPI, &cnl_features },
859 { INTEL_FAM6_ROCKETLAKE, &cnl_features },
860 { INTEL_FAM6_TIGERLAKE_L, &cnl_features },
861 { INTEL_FAM6_TIGERLAKE, &cnl_features },
862 { INTEL_FAM6_SAPPHIRERAPIDS_X, &spr_features },
863 { INTEL_FAM6_EMERALDRAPIDS_X, &spr_features },
864 { INTEL_FAM6_GRANITERAPIDS_X, &spr_features },
865 { INTEL_FAM6_LAKEFIELD, &cnl_features },
866 { INTEL_FAM6_ALDERLAKE, &adl_features },
867 { INTEL_FAM6_ALDERLAKE_L, &adl_features },
868 { INTEL_FAM6_RAPTORLAKE, &adl_features },
869 { INTEL_FAM6_RAPTORLAKE_P, &adl_features },
870 { INTEL_FAM6_RAPTORLAKE_S, &adl_features },
871 { INTEL_FAM6_METEORLAKE, &cnl_features },
872 { INTEL_FAM6_METEORLAKE_L, &cnl_features },
873 { INTEL_FAM6_ARROWLAKE, &cnl_features },
874 { INTEL_FAM6_LUNARLAKE_M, &cnl_features },
875 { INTEL_FAM6_ATOM_SILVERMONT, &slv_features },
876 { INTEL_FAM6_ATOM_SILVERMONT_D, &slvd_features },
877 { INTEL_FAM6_ATOM_AIRMONT, &amt_features },
878 { INTEL_FAM6_ATOM_GOLDMONT, &gmt_features },
879 { INTEL_FAM6_ATOM_GOLDMONT_D, &gmtd_features },
880 { INTEL_FAM6_ATOM_GOLDMONT_PLUS, &gmtp_features },
881 { INTEL_FAM6_ATOM_TREMONT_D, &tmtd_features },
882 { INTEL_FAM6_ATOM_TREMONT, &tmt_features },
883 { INTEL_FAM6_ATOM_TREMONT_L, &tmt_features },
884 { INTEL_FAM6_ATOM_GRACEMONT, &adl_features },
885 { INTEL_FAM6_ATOM_CRESTMONT_X, &srf_features },
886 { INTEL_FAM6_ATOM_CRESTMONT, &grr_features },
887 { INTEL_FAM6_XEON_PHI_KNL, &knl_features },
888 { INTEL_FAM6_XEON_PHI_KNM, &knl_features },
889 /*
890 * Missing support for
891 * INTEL_FAM6_ICELAKE
892 * INTEL_FAM6_ATOM_SILVERMONT_MID
893 * INTEL_FAM6_ATOM_AIRMONT_MID
894 * INTEL_FAM6_ATOM_AIRMONT_NP
895 */
896 { 0, NULL },
897 };
898
899 static const struct platform_features *platform;
900
901 void probe_platform_features(unsigned int family, unsigned int model)
902 {
903 int i;
904
905 platform = &default_features;
906
907 if (authentic_amd || hygon_genuine) {
908 if (max_extended_level >= 0x80000007) {
909 unsigned int eax, ebx, ecx, edx;
910
911 __cpuid(0x80000007, eax, ebx, ecx, edx);
912 /* RAPL (Fam 17h+) */
913 if ((edx & (1 << 14)) && family >= 0x17)
914 platform = &amd_features_with_rapl;
915 }
916 return;
917 }
918
919 if (!genuine_intel || family != 6)
920 return;
921
922 for (i = 0; turbostat_pdata[i].features; i++) {
923 if (turbostat_pdata[i].model == model) {
924 platform = turbostat_pdata[i].features;
925 return;
926 }
927 }
928 }
929
930 /* Model specific support End */
931
932 #define TJMAX_DEFAULT 100
933
934 /* MSRs that are not yet in the kernel-provided header. */
935 #define MSR_RAPL_PWR_UNIT 0xc0010299
936 #define MSR_CORE_ENERGY_STAT 0xc001029a
937 #define MSR_PKG_ENERGY_STAT 0xc001029b
938
939 #define MAX(a, b) ((a) > (b) ? (a) : (b))
940
941 int backwards_count;
942 char *progname;
943
944 #define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */
945 cpu_set_t *cpu_present_set, *cpu_effective_set, *cpu_allowed_set, *cpu_affinity_set, *cpu_subset;
946 size_t cpu_present_setsize, cpu_effective_setsize, cpu_allowed_setsize, cpu_affinity_setsize, cpu_subset_size;
947 #define MAX_ADDED_COUNTERS 8
948 #define MAX_ADDED_THREAD_COUNTERS 24
949 #define BITMASK_SIZE 32
950
951 struct thread_data {
952 struct timeval tv_begin;
953 struct timeval tv_end;
954 struct timeval tv_delta;
955 unsigned long long tsc;
956 unsigned long long aperf;
957 unsigned long long mperf;
958 unsigned long long c1;
959 unsigned long long instr_count;
960 unsigned long long irq_count;
961 unsigned int smi_count;
962 unsigned int cpu_id;
963 unsigned int apic_id;
964 unsigned int x2apic_id;
965 unsigned int flags;
966 bool is_atom;
967 unsigned long long counter[MAX_ADDED_THREAD_COUNTERS];
968 } *thread_even, *thread_odd;
969
970 struct core_data {
971 int base_cpu;
972 unsigned long long c3;
973 unsigned long long c6;
974 unsigned long long c7;
975 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */
976 unsigned int core_temp_c;
977 unsigned int core_energy; /* MSR_CORE_ENERGY_STAT */
978 unsigned int core_id;
979 unsigned long long core_throt_cnt;
980 unsigned long long counter[MAX_ADDED_COUNTERS];
981 } *core_even, *core_odd;
982
983 struct pkg_data {
984 int base_cpu;
985 unsigned long long pc2;
986 unsigned long long pc3;
987 unsigned long long pc6;
988 unsigned long long pc7;
989 unsigned long long pc8;
990 unsigned long long pc9;
991 unsigned long long pc10;
992 unsigned long long cpu_lpi;
993 unsigned long long sys_lpi;
994 unsigned long long pkg_wtd_core_c0;
995 unsigned long long pkg_any_core_c0;
996 unsigned long long pkg_any_gfxe_c0;
997 unsigned long long pkg_both_core_gfxe_c0;
998 long long gfx_rc6_ms;
999 unsigned int gfx_mhz;
1000 unsigned int gfx_act_mhz;
1001 unsigned int package_id;
1002 unsigned long long energy_pkg; /* MSR_PKG_ENERGY_STATUS */
1003 unsigned long long energy_dram; /* MSR_DRAM_ENERGY_STATUS */
1004 unsigned long long energy_cores; /* MSR_PP0_ENERGY_STATUS */
1005 unsigned long long energy_gfx; /* MSR_PP1_ENERGY_STATUS */
1006 unsigned long long rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */
1007 unsigned long long rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */
1008 unsigned int pkg_temp_c;
1009 unsigned int uncore_mhz;
1010 unsigned long long counter[MAX_ADDED_COUNTERS];
1011 } *package_even, *package_odd;
1012
1013 #define ODD_COUNTERS thread_odd, core_odd, package_odd
1014 #define EVEN_COUNTERS thread_even, core_even, package_even
1015
1016 #define GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no) \
1017 ((thread_base) + \
1018 ((pkg_no) * \
1019 topo.nodes_per_pkg * topo.cores_per_node * topo.threads_per_core) + \
1020 ((node_no) * topo.cores_per_node * topo.threads_per_core) + \
1021 ((core_no) * topo.threads_per_core) + \
1022 (thread_no))
1023
1024 #define GET_CORE(core_base, core_no, node_no, pkg_no) \
1025 ((core_base) + \
1026 ((pkg_no) * topo.nodes_per_pkg * topo.cores_per_node) + \
1027 ((node_no) * topo.cores_per_node) + \
1028 (core_no))
1029
1030 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no)
1031
1032 /*
1033 * The accumulated sum of MSR is defined as a monotonic
1034 * increasing MSR, it will be accumulated periodically,
1035 * despite its register's bit width.
1036 */
1037 enum {
1038 IDX_PKG_ENERGY,
1039 IDX_DRAM_ENERGY,
1040 IDX_PP0_ENERGY,
1041 IDX_PP1_ENERGY,
1042 IDX_PKG_PERF,
1043 IDX_DRAM_PERF,
1044 IDX_COUNT,
1045 };
1046
1047 int get_msr_sum(int cpu, off_t offset, unsigned long long *msr);
1048
1049 struct msr_sum_array {
1050 /* get_msr_sum() = sum + (get_msr() - last) */
1051 struct {
1052 /*The accumulated MSR value is updated by the timer */
1053 unsigned long long sum;
1054 /*The MSR footprint recorded in last timer */
1055 unsigned long long last;
1056 } entries[IDX_COUNT];
1057 };
1058
1059 /* The percpu MSR sum array.*/
1060 struct msr_sum_array *per_cpu_msr_sum;
1061
1062 off_t idx_to_offset(int idx)
1063 {
1064 off_t offset;
1065
1066 switch (idx) {
1067 case IDX_PKG_ENERGY:
1068 if (platform->rapl_msrs & RAPL_AMD_F17H)
1069 offset = MSR_PKG_ENERGY_STAT;
1070 else
1071 offset = MSR_PKG_ENERGY_STATUS;
1072 break;
1073 case IDX_DRAM_ENERGY:
1074 offset = MSR_DRAM_ENERGY_STATUS;
1075 break;
1076 case IDX_PP0_ENERGY:
1077 offset = MSR_PP0_ENERGY_STATUS;
1078 break;
1079 case IDX_PP1_ENERGY:
1080 offset = MSR_PP1_ENERGY_STATUS;
1081 break;
1082 case IDX_PKG_PERF:
1083 offset = MSR_PKG_PERF_STATUS;
1084 break;
1085 case IDX_DRAM_PERF:
1086 offset = MSR_DRAM_PERF_STATUS;
1087 break;
1088 default:
1089 offset = -1;
1090 }
1091 return offset;
1092 }
1093
1094 int offset_to_idx(off_t offset)
1095 {
1096 int idx;
1097
1098 switch (offset) {
1099 case MSR_PKG_ENERGY_STATUS:
1100 case MSR_PKG_ENERGY_STAT:
1101 idx = IDX_PKG_ENERGY;
1102 break;
1103 case MSR_DRAM_ENERGY_STATUS:
1104 idx = IDX_DRAM_ENERGY;
1105 break;
1106 case MSR_PP0_ENERGY_STATUS:
1107 idx = IDX_PP0_ENERGY;
1108 break;
1109 case MSR_PP1_ENERGY_STATUS:
1110 idx = IDX_PP1_ENERGY;
1111 break;
1112 case MSR_PKG_PERF_STATUS:
1113 idx = IDX_PKG_PERF;
1114 break;
1115 case MSR_DRAM_PERF_STATUS:
1116 idx = IDX_DRAM_PERF;
1117 break;
1118 default:
1119 idx = -1;
1120 }
1121 return idx;
1122 }
1123
1124 int idx_valid(int idx)
1125 {
1126 switch (idx) {
1127 case IDX_PKG_ENERGY:
1128 return platform->rapl_msrs & (RAPL_PKG | RAPL_AMD_F17H);
1129 case IDX_DRAM_ENERGY:
1130 return platform->rapl_msrs & RAPL_DRAM;
1131 case IDX_PP0_ENERGY:
1132 return platform->rapl_msrs & RAPL_CORE_ENERGY_STATUS;
1133 case IDX_PP1_ENERGY:
1134 return platform->rapl_msrs & RAPL_GFX;
1135 case IDX_PKG_PERF:
1136 return platform->rapl_msrs & RAPL_PKG_PERF_STATUS;
1137 case IDX_DRAM_PERF:
1138 return platform->rapl_msrs & RAPL_DRAM_PERF_STATUS;
1139 default:
1140 return 0;
1141 }
1142 }
1143
1144 struct sys_counters {
1145 unsigned int added_thread_counters;
1146 unsigned int added_core_counters;
1147 unsigned int added_package_counters;
1148 struct msr_counter *tp;
1149 struct msr_counter *cp;
1150 struct msr_counter *pp;
1151 } sys;
1152
1153 struct system_summary {
1154 struct thread_data threads;
1155 struct core_data cores;
1156 struct pkg_data packages;
1157 } average;
1158
1159 struct cpu_topology {
1160 int physical_package_id;
1161 int die_id;
1162 int logical_cpu_id;
1163 int physical_node_id;
1164 int logical_node_id; /* 0-based count within the package */
1165 int physical_core_id;
1166 int thread_id;
1167 cpu_set_t *put_ids; /* Processing Unit/Thread IDs */
1168 } *cpus;
1169
1170 struct topo_params {
1171 int num_packages;
1172 int num_die;
1173 int num_cpus;
1174 int num_cores;
1175 int allowed_packages;
1176 int allowed_cpus;
1177 int allowed_cores;
1178 int max_cpu_num;
1179 int max_node_num;
1180 int nodes_per_pkg;
1181 int cores_per_node;
1182 int threads_per_core;
1183 } topo;
1184
1185 struct timeval tv_even, tv_odd, tv_delta;
1186
1187 int *irq_column_2_cpu; /* /proc/interrupts column numbers */
1188 int *irqs_per_cpu; /* indexed by cpu_num */
1189
1190 void setup_all_buffers(bool startup);
1191
1192 char *sys_lpi_file;
1193 char *sys_lpi_file_sysfs = "/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us";
1194 char *sys_lpi_file_debugfs = "/sys/kernel/debug/pmc_core/slp_s0_residency_usec";
1195
1196 int cpu_is_not_present(int cpu)
1197 {
1198 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set);
1199 }
1200
1201 int cpu_is_not_allowed(int cpu)
1202 {
1203 return !CPU_ISSET_S(cpu, cpu_allowed_setsize, cpu_allowed_set);
1204 }
1205
1206 /*
1207 * run func(thread, core, package) in topology order
1208 * skip non-present cpus
1209 */
1210
1211 int for_all_cpus(int (func) (struct thread_data *, struct core_data *, struct pkg_data *),
1212 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base)
1213 {
1214 int retval, pkg_no, core_no, thread_no, node_no;
1215
1216 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
1217 for (node_no = 0; node_no < topo.nodes_per_pkg; node_no++) {
1218 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) {
1219 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) {
1220 struct thread_data *t;
1221 struct core_data *c;
1222 struct pkg_data *p;
1223 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no);
1224
1225 if (cpu_is_not_allowed(t->cpu_id))
1226 continue;
1227
1228 c = GET_CORE(core_base, core_no, node_no, pkg_no);
1229 p = GET_PKG(pkg_base, pkg_no);
1230
1231 retval = func(t, c, p);
1232 if (retval)
1233 return retval;
1234 }
1235 }
1236 }
1237 }
1238 return 0;
1239 }
1240
1241 int is_cpu_first_thread_in_core(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1242 {
1243 UNUSED(p);
1244
1245 return ((int)t->cpu_id == c->base_cpu || c->base_cpu < 0);
1246 }
1247
1248 int is_cpu_first_core_in_package(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1249 {
1250 UNUSED(c);
1251
1252 return ((int)t->cpu_id == p->base_cpu || p->base_cpu < 0);
1253 }
1254
1255 int is_cpu_first_thread_in_package(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1256 {
1257 return is_cpu_first_thread_in_core(t, c, p) && is_cpu_first_core_in_package(t, c, p);
1258 }
1259
1260 int cpu_migrate(int cpu)
1261 {
1262 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
1263 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set);
1264 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1)
1265 return -1;
1266 else
1267 return 0;
1268 }
1269
1270 int get_msr_fd(int cpu)
1271 {
1272 char pathname[32];
1273 int fd;
1274
1275 fd = fd_percpu[cpu];
1276
1277 if (fd)
1278 return fd;
1279
1280 sprintf(pathname, "/dev/cpu/%d/msr", cpu);
1281 fd = open(pathname, O_RDONLY);
1282 if (fd < 0)
1283 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname);
1284
1285 fd_percpu[cpu] = fd;
1286
1287 return fd;
1288 }
1289
1290 static long perf_event_open(struct perf_event_attr *hw_event, pid_t pid, int cpu, int group_fd, unsigned long flags)
1291 {
1292 return syscall(__NR_perf_event_open, hw_event, pid, cpu, group_fd, flags);
1293 }
1294
1295 static int perf_instr_count_open(int cpu_num)
1296 {
1297 struct perf_event_attr pea;
1298 int fd;
1299
1300 memset(&pea, 0, sizeof(struct perf_event_attr));
1301 pea.type = PERF_TYPE_HARDWARE;
1302 pea.size = sizeof(struct perf_event_attr);
1303 pea.config = PERF_COUNT_HW_INSTRUCTIONS;
1304
1305 /* counter for cpu_num, including user + kernel and all processes */
1306 fd = perf_event_open(&pea, -1, cpu_num, -1, 0);
1307 if (fd == -1) {
1308 warnx("capget(CAP_PERFMON) failed, try \"# setcap cap_sys_admin=ep %s\"", progname);
1309 BIC_NOT_PRESENT(BIC_IPC);
1310 }
1311
1312 return fd;
1313 }
1314
1315 int get_instr_count_fd(int cpu)
1316 {
1317 if (fd_instr_count_percpu[cpu])
1318 return fd_instr_count_percpu[cpu];
1319
1320 fd_instr_count_percpu[cpu] = perf_instr_count_open(cpu);
1321
1322 return fd_instr_count_percpu[cpu];
1323 }
1324
1325 int get_msr(int cpu, off_t offset, unsigned long long *msr)
1326 {
1327 ssize_t retval;
1328
1329 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset);
1330
1331 if (retval != sizeof *msr)
1332 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset);
1333
1334 return 0;
1335 }
1336
1337 #define MAX_DEFERRED 16
1338 char *deferred_add_names[MAX_DEFERRED];
1339 char *deferred_skip_names[MAX_DEFERRED];
1340 int deferred_add_index;
1341 int deferred_skip_index;
1342
1343 /*
1344 * HIDE_LIST - hide this list of counters, show the rest [default]
1345 * SHOW_LIST - show this list of counters, hide the rest
1346 */
1347 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST;
1348
1349 void help(void)
1350 {
1351 fprintf(outf,
1352 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n"
1353 "\n"
1354 "Turbostat forks the specified COMMAND and prints statistics\n"
1355 "when COMMAND completes.\n"
1356 "If no COMMAND is specified, turbostat wakes every 5-seconds\n"
1357 "to print statistics, until interrupted.\n"
1358 " -a, --add add a counter\n"
1359 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n"
1360 " -c, --cpu cpu-set limit output to summary plus cpu-set:\n"
1361 " {core | package | j,k,l..m,n-p }\n"
1362 " -d, --debug displays usec, Time_Of_Day_Seconds and more debugging\n"
1363 " -D, --Dump displays the raw counter values\n"
1364 " -e, --enable [all | column]\n"
1365 " shows all or the specified disabled column\n"
1366 " -H, --hide [column|column,column,...]\n"
1367 " hide the specified column(s)\n"
1368 " -i, --interval sec.subsec\n"
1369 " Override default 5-second measurement interval\n"
1370 " -J, --Joules displays energy in Joules instead of Watts\n"
1371 " -l, --list list column headers only\n"
1372 " -n, --num_iterations num\n"
1373 " number of the measurement iterations\n"
1374 " -N, --header_iterations num\n"
1375 " print header every num iterations\n"
1376 " -o, --out file\n"
1377 " create or truncate \"file\" for all output\n"
1378 " -q, --quiet skip decoding system configuration header\n"
1379 " -s, --show [column|column,column,...]\n"
1380 " show only the specified column(s)\n"
1381 " -S, --Summary\n"
1382 " limits output to 1-line system summary per interval\n"
1383 " -T, --TCC temperature\n"
1384 " sets the Thermal Control Circuit temperature in\n"
1385 " degrees Celsius\n"
1386 " -h, --help print this help message\n"
1387 " -v, --version print version information\n" "\n" "For more help, run \"man turbostat\"\n");
1388 }
1389
1390 /*
1391 * bic_lookup
1392 * for all the strings in comma separate name_list,
1393 * set the approprate bit in return value.
1394 */
1395 unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode)
1396 {
1397 unsigned int i;
1398 unsigned long long retval = 0;
1399
1400 while (name_list) {
1401 char *comma;
1402
1403 comma = strchr(name_list, ',');
1404
1405 if (comma)
1406 *comma = '\0';
1407
1408 for (i = 0; i < MAX_BIC; ++i) {
1409 if (!strcmp(name_list, bic[i].name)) {
1410 retval |= (1ULL << i);
1411 break;
1412 }
1413 if (!strcmp(name_list, "all")) {
1414 retval |= ~0;
1415 break;
1416 } else if (!strcmp(name_list, "topology")) {
1417 retval |= BIC_TOPOLOGY;
1418 break;
1419 } else if (!strcmp(name_list, "power")) {
1420 retval |= BIC_THERMAL_PWR;
1421 break;
1422 } else if (!strcmp(name_list, "idle")) {
1423 retval |= BIC_IDLE;
1424 break;
1425 } else if (!strcmp(name_list, "frequency")) {
1426 retval |= BIC_FREQUENCY;
1427 break;
1428 } else if (!strcmp(name_list, "other")) {
1429 retval |= BIC_OTHER;
1430 break;
1431 }
1432
1433 }
1434 if (i == MAX_BIC) {
1435 if (mode == SHOW_LIST) {
1436 deferred_add_names[deferred_add_index++] = name_list;
1437 if (deferred_add_index >= MAX_DEFERRED) {
1438 fprintf(stderr, "More than max %d un-recognized --add options '%s'\n",
1439 MAX_DEFERRED, name_list);
1440 help();
1441 exit(1);
1442 }
1443 } else {
1444 deferred_skip_names[deferred_skip_index++] = name_list;
1445 if (debug)
1446 fprintf(stderr, "deferred \"%s\"\n", name_list);
1447 if (deferred_skip_index >= MAX_DEFERRED) {
1448 fprintf(stderr, "More than max %d un-recognized --skip options '%s'\n",
1449 MAX_DEFERRED, name_list);
1450 help();
1451 exit(1);
1452 }
1453 }
1454 }
1455
1456 name_list = comma;
1457 if (name_list)
1458 name_list++;
1459
1460 }
1461 return retval;
1462 }
1463
1464 void print_header(char *delim)
1465 {
1466 struct msr_counter *mp;
1467 int printed = 0;
1468
1469 if (DO_BIC(BIC_USEC))
1470 outp += sprintf(outp, "%susec", (printed++ ? delim : ""));
1471 if (DO_BIC(BIC_TOD))
1472 outp += sprintf(outp, "%sTime_Of_Day_Seconds", (printed++ ? delim : ""));
1473 if (DO_BIC(BIC_Package))
1474 outp += sprintf(outp, "%sPackage", (printed++ ? delim : ""));
1475 if (DO_BIC(BIC_Die))
1476 outp += sprintf(outp, "%sDie", (printed++ ? delim : ""));
1477 if (DO_BIC(BIC_Node))
1478 outp += sprintf(outp, "%sNode", (printed++ ? delim : ""));
1479 if (DO_BIC(BIC_Core))
1480 outp += sprintf(outp, "%sCore", (printed++ ? delim : ""));
1481 if (DO_BIC(BIC_CPU))
1482 outp += sprintf(outp, "%sCPU", (printed++ ? delim : ""));
1483 if (DO_BIC(BIC_APIC))
1484 outp += sprintf(outp, "%sAPIC", (printed++ ? delim : ""));
1485 if (DO_BIC(BIC_X2APIC))
1486 outp += sprintf(outp, "%sX2APIC", (printed++ ? delim : ""));
1487 if (DO_BIC(BIC_Avg_MHz))
1488 outp += sprintf(outp, "%sAvg_MHz", (printed++ ? delim : ""));
1489 if (DO_BIC(BIC_Busy))
1490 outp += sprintf(outp, "%sBusy%%", (printed++ ? delim : ""));
1491 if (DO_BIC(BIC_Bzy_MHz))
1492 outp += sprintf(outp, "%sBzy_MHz", (printed++ ? delim : ""));
1493 if (DO_BIC(BIC_TSC_MHz))
1494 outp += sprintf(outp, "%sTSC_MHz", (printed++ ? delim : ""));
1495
1496 if (DO_BIC(BIC_IPC))
1497 outp += sprintf(outp, "%sIPC", (printed++ ? delim : ""));
1498
1499 if (DO_BIC(BIC_IRQ)) {
1500 if (sums_need_wide_columns)
1501 outp += sprintf(outp, "%s IRQ", (printed++ ? delim : ""));
1502 else
1503 outp += sprintf(outp, "%sIRQ", (printed++ ? delim : ""));
1504 }
1505
1506 if (DO_BIC(BIC_SMI))
1507 outp += sprintf(outp, "%sSMI", (printed++ ? delim : ""));
1508
1509 for (mp = sys.tp; mp; mp = mp->next) {
1510
1511 if (mp->format == FORMAT_RAW) {
1512 if (mp->width == 64)
1513 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name);
1514 else
1515 outp += sprintf(outp, "%s%10.10s", (printed++ ? delim : ""), mp->name);
1516 } else {
1517 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1518 outp += sprintf(outp, "%s%8s", (printed++ ? delim : ""), mp->name);
1519 else
1520 outp += sprintf(outp, "%s%s", (printed++ ? delim : ""), mp->name);
1521 }
1522 }
1523
1524 if (DO_BIC(BIC_CPU_c1))
1525 outp += sprintf(outp, "%sCPU%%c1", (printed++ ? delim : ""));
1526 if (DO_BIC(BIC_CPU_c3))
1527 outp += sprintf(outp, "%sCPU%%c3", (printed++ ? delim : ""));
1528 if (DO_BIC(BIC_CPU_c6))
1529 outp += sprintf(outp, "%sCPU%%c6", (printed++ ? delim : ""));
1530 if (DO_BIC(BIC_CPU_c7))
1531 outp += sprintf(outp, "%sCPU%%c7", (printed++ ? delim : ""));
1532
1533 if (DO_BIC(BIC_Mod_c6))
1534 outp += sprintf(outp, "%sMod%%c6", (printed++ ? delim : ""));
1535
1536 if (DO_BIC(BIC_CoreTmp))
1537 outp += sprintf(outp, "%sCoreTmp", (printed++ ? delim : ""));
1538
1539 if (DO_BIC(BIC_CORE_THROT_CNT))
1540 outp += sprintf(outp, "%sCoreThr", (printed++ ? delim : ""));
1541
1542 if (platform->rapl_msrs && !rapl_joules) {
1543 if (DO_BIC(BIC_CorWatt) && platform->has_per_core_rapl)
1544 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : ""));
1545 } else if (platform->rapl_msrs && rapl_joules) {
1546 if (DO_BIC(BIC_Cor_J) && platform->has_per_core_rapl)
1547 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : ""));
1548 }
1549
1550 for (mp = sys.cp; mp; mp = mp->next) {
1551 if (mp->format == FORMAT_RAW) {
1552 if (mp->width == 64)
1553 outp += sprintf(outp, "%s%18.18s", delim, mp->name);
1554 else
1555 outp += sprintf(outp, "%s%10.10s", delim, mp->name);
1556 } else {
1557 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1558 outp += sprintf(outp, "%s%8s", delim, mp->name);
1559 else
1560 outp += sprintf(outp, "%s%s", delim, mp->name);
1561 }
1562 }
1563
1564 if (DO_BIC(BIC_PkgTmp))
1565 outp += sprintf(outp, "%sPkgTmp", (printed++ ? delim : ""));
1566
1567 if (DO_BIC(BIC_GFX_rc6))
1568 outp += sprintf(outp, "%sGFX%%rc6", (printed++ ? delim : ""));
1569
1570 if (DO_BIC(BIC_GFXMHz))
1571 outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : ""));
1572
1573 if (DO_BIC(BIC_GFXACTMHz))
1574 outp += sprintf(outp, "%sGFXAMHz", (printed++ ? delim : ""));
1575
1576 if (DO_BIC(BIC_Totl_c0))
1577 outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : ""));
1578 if (DO_BIC(BIC_Any_c0))
1579 outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : ""));
1580 if (DO_BIC(BIC_GFX_c0))
1581 outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : ""));
1582 if (DO_BIC(BIC_CPUGFX))
1583 outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : ""));
1584
1585 if (DO_BIC(BIC_Pkgpc2))
1586 outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : ""));
1587 if (DO_BIC(BIC_Pkgpc3))
1588 outp += sprintf(outp, "%sPkg%%pc3", (printed++ ? delim : ""));
1589 if (DO_BIC(BIC_Pkgpc6))
1590 outp += sprintf(outp, "%sPkg%%pc6", (printed++ ? delim : ""));
1591 if (DO_BIC(BIC_Pkgpc7))
1592 outp += sprintf(outp, "%sPkg%%pc7", (printed++ ? delim : ""));
1593 if (DO_BIC(BIC_Pkgpc8))
1594 outp += sprintf(outp, "%sPkg%%pc8", (printed++ ? delim : ""));
1595 if (DO_BIC(BIC_Pkgpc9))
1596 outp += sprintf(outp, "%sPkg%%pc9", (printed++ ? delim : ""));
1597 if (DO_BIC(BIC_Pkgpc10))
1598 outp += sprintf(outp, "%sPk%%pc10", (printed++ ? delim : ""));
1599 if (DO_BIC(BIC_CPU_LPI))
1600 outp += sprintf(outp, "%sCPU%%LPI", (printed++ ? delim : ""));
1601 if (DO_BIC(BIC_SYS_LPI))
1602 outp += sprintf(outp, "%sSYS%%LPI", (printed++ ? delim : ""));
1603
1604 if (platform->rapl_msrs && !rapl_joules) {
1605 if (DO_BIC(BIC_PkgWatt))
1606 outp += sprintf(outp, "%sPkgWatt", (printed++ ? delim : ""));
1607 if (DO_BIC(BIC_CorWatt) && !platform->has_per_core_rapl)
1608 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : ""));
1609 if (DO_BIC(BIC_GFXWatt))
1610 outp += sprintf(outp, "%sGFXWatt", (printed++ ? delim : ""));
1611 if (DO_BIC(BIC_RAMWatt))
1612 outp += sprintf(outp, "%sRAMWatt", (printed++ ? delim : ""));
1613 if (DO_BIC(BIC_PKG__))
1614 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : ""));
1615 if (DO_BIC(BIC_RAM__))
1616 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : ""));
1617 } else if (platform->rapl_msrs && rapl_joules) {
1618 if (DO_BIC(BIC_Pkg_J))
1619 outp += sprintf(outp, "%sPkg_J", (printed++ ? delim : ""));
1620 if (DO_BIC(BIC_Cor_J) && !platform->has_per_core_rapl)
1621 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : ""));
1622 if (DO_BIC(BIC_GFX_J))
1623 outp += sprintf(outp, "%sGFX_J", (printed++ ? delim : ""));
1624 if (DO_BIC(BIC_RAM_J))
1625 outp += sprintf(outp, "%sRAM_J", (printed++ ? delim : ""));
1626 if (DO_BIC(BIC_PKG__))
1627 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : ""));
1628 if (DO_BIC(BIC_RAM__))
1629 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : ""));
1630 }
1631 if (DO_BIC(BIC_UNCORE_MHZ))
1632 outp += sprintf(outp, "%sUncMHz", (printed++ ? delim : ""));
1633
1634 for (mp = sys.pp; mp; mp = mp->next) {
1635 if (mp->format == FORMAT_RAW) {
1636 if (mp->width == 64)
1637 outp += sprintf(outp, "%s%18.18s", delim, mp->name);
1638 else
1639 outp += sprintf(outp, "%s%10.10s", delim, mp->name);
1640 } else {
1641 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1642 outp += sprintf(outp, "%s%8s", delim, mp->name);
1643 else
1644 outp += sprintf(outp, "%s%s", delim, mp->name);
1645 }
1646 }
1647
1648 outp += sprintf(outp, "\n");
1649 }
1650
1651 int dump_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1652 {
1653 int i;
1654 struct msr_counter *mp;
1655
1656 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p);
1657
1658 if (t) {
1659 outp += sprintf(outp, "CPU: %d flags 0x%x\n", t->cpu_id, t->flags);
1660 outp += sprintf(outp, "TSC: %016llX\n", t->tsc);
1661 outp += sprintf(outp, "aperf: %016llX\n", t->aperf);
1662 outp += sprintf(outp, "mperf: %016llX\n", t->mperf);
1663 outp += sprintf(outp, "c1: %016llX\n", t->c1);
1664
1665 if (DO_BIC(BIC_IPC))
1666 outp += sprintf(outp, "IPC: %lld\n", t->instr_count);
1667
1668 if (DO_BIC(BIC_IRQ))
1669 outp += sprintf(outp, "IRQ: %lld\n", t->irq_count);
1670 if (DO_BIC(BIC_SMI))
1671 outp += sprintf(outp, "SMI: %d\n", t->smi_count);
1672
1673 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1674 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, t->counter[i]);
1675 }
1676 }
1677
1678 if (c) {
1679 outp += sprintf(outp, "core: %d\n", c->core_id);
1680 outp += sprintf(outp, "c3: %016llX\n", c->c3);
1681 outp += sprintf(outp, "c6: %016llX\n", c->c6);
1682 outp += sprintf(outp, "c7: %016llX\n", c->c7);
1683 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c);
1684 outp += sprintf(outp, "cpu_throt_count: %016llX\n", c->core_throt_cnt);
1685 outp += sprintf(outp, "Joules: %0X\n", c->core_energy);
1686
1687 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1688 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, c->counter[i]);
1689 }
1690 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us);
1691 }
1692
1693 if (p) {
1694 outp += sprintf(outp, "package: %d\n", p->package_id);
1695
1696 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0);
1697 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0);
1698 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0);
1699 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0);
1700
1701 outp += sprintf(outp, "pc2: %016llX\n", p->pc2);
1702 if (DO_BIC(BIC_Pkgpc3))
1703 outp += sprintf(outp, "pc3: %016llX\n", p->pc3);
1704 if (DO_BIC(BIC_Pkgpc6))
1705 outp += sprintf(outp, "pc6: %016llX\n", p->pc6);
1706 if (DO_BIC(BIC_Pkgpc7))
1707 outp += sprintf(outp, "pc7: %016llX\n", p->pc7);
1708 outp += sprintf(outp, "pc8: %016llX\n", p->pc8);
1709 outp += sprintf(outp, "pc9: %016llX\n", p->pc9);
1710 outp += sprintf(outp, "pc10: %016llX\n", p->pc10);
1711 outp += sprintf(outp, "cpu_lpi: %016llX\n", p->cpu_lpi);
1712 outp += sprintf(outp, "sys_lpi: %016llX\n", p->sys_lpi);
1713 outp += sprintf(outp, "Joules PKG: %0llX\n", p->energy_pkg);
1714 outp += sprintf(outp, "Joules COR: %0llX\n", p->energy_cores);
1715 outp += sprintf(outp, "Joules GFX: %0llX\n", p->energy_gfx);
1716 outp += sprintf(outp, "Joules RAM: %0llX\n", p->energy_dram);
1717 outp += sprintf(outp, "Throttle PKG: %0llX\n", p->rapl_pkg_perf_status);
1718 outp += sprintf(outp, "Throttle RAM: %0llX\n", p->rapl_dram_perf_status);
1719 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c);
1720
1721 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1722 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, p->counter[i]);
1723 }
1724 }
1725
1726 outp += sprintf(outp, "\n");
1727
1728 return 0;
1729 }
1730
1731 /*
1732 * column formatting convention & formats
1733 */
1734 int format_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1735 {
1736 double interval_float, tsc;
1737 char *fmt8;
1738 int i;
1739 struct msr_counter *mp;
1740 char *delim = "\t";
1741 int printed = 0;
1742
1743 /* if showing only 1st thread in core and this isn't one, bail out */
1744 if (show_core_only && !is_cpu_first_thread_in_core(t, c, p))
1745 return 0;
1746
1747 /* if showing only 1st thread in pkg and this isn't one, bail out */
1748 if (show_pkg_only && !is_cpu_first_core_in_package(t, c, p))
1749 return 0;
1750
1751 /*if not summary line and --cpu is used */
1752 if ((t != &average.threads) && (cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset)))
1753 return 0;
1754
1755 if (DO_BIC(BIC_USEC)) {
1756 /* on each row, print how many usec each timestamp took to gather */
1757 struct timeval tv;
1758
1759 timersub(&t->tv_end, &t->tv_begin, &tv);
1760 outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec);
1761 }
1762
1763 /* Time_Of_Day_Seconds: on each row, print sec.usec last timestamp taken */
1764 if (DO_BIC(BIC_TOD))
1765 outp += sprintf(outp, "%10ld.%06ld\t", t->tv_end.tv_sec, t->tv_end.tv_usec);
1766
1767 interval_float = t->tv_delta.tv_sec + t->tv_delta.tv_usec / 1000000.0;
1768
1769 tsc = t->tsc * tsc_tweak;
1770
1771 /* topo columns, print blanks on 1st (average) line */
1772 if (t == &average.threads) {
1773 if (DO_BIC(BIC_Package))
1774 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1775 if (DO_BIC(BIC_Die))
1776 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1777 if (DO_BIC(BIC_Node))
1778 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1779 if (DO_BIC(BIC_Core))
1780 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1781 if (DO_BIC(BIC_CPU))
1782 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1783 if (DO_BIC(BIC_APIC))
1784 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1785 if (DO_BIC(BIC_X2APIC))
1786 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1787 } else {
1788 if (DO_BIC(BIC_Package)) {
1789 if (p)
1790 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->package_id);
1791 else
1792 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1793 }
1794 if (DO_BIC(BIC_Die)) {
1795 if (c)
1796 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), cpus[t->cpu_id].die_id);
1797 else
1798 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1799 }
1800 if (DO_BIC(BIC_Node)) {
1801 if (t)
1802 outp += sprintf(outp, "%s%d",
1803 (printed++ ? delim : ""), cpus[t->cpu_id].physical_node_id);
1804 else
1805 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1806 }
1807 if (DO_BIC(BIC_Core)) {
1808 if (c)
1809 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_id);
1810 else
1811 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1812 }
1813 if (DO_BIC(BIC_CPU))
1814 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->cpu_id);
1815 if (DO_BIC(BIC_APIC))
1816 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->apic_id);
1817 if (DO_BIC(BIC_X2APIC))
1818 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->x2apic_id);
1819 }
1820
1821 if (DO_BIC(BIC_Avg_MHz))
1822 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 / units * t->aperf / interval_float);
1823
1824 if (DO_BIC(BIC_Busy))
1825 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->mperf / tsc);
1826
1827 if (DO_BIC(BIC_Bzy_MHz)) {
1828 if (has_base_hz)
1829 outp +=
1830 sprintf(outp, "%s%.0f", (printed++ ? delim : ""), base_hz / units * t->aperf / t->mperf);
1831 else
1832 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""),
1833 tsc / units * t->aperf / t->mperf / interval_float);
1834 }
1835
1836 if (DO_BIC(BIC_TSC_MHz))
1837 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 * t->tsc / units / interval_float);
1838
1839 if (DO_BIC(BIC_IPC))
1840 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1.0 * t->instr_count / t->aperf);
1841
1842 /* IRQ */
1843 if (DO_BIC(BIC_IRQ)) {
1844 if (sums_need_wide_columns)
1845 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->irq_count);
1846 else
1847 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->irq_count);
1848 }
1849
1850 /* SMI */
1851 if (DO_BIC(BIC_SMI))
1852 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->smi_count);
1853
1854 /* Added counters */
1855 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1856 if (mp->format == FORMAT_RAW) {
1857 if (mp->width == 32)
1858 outp +=
1859 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)t->counter[i]);
1860 else
1861 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), t->counter[i]);
1862 } else if (mp->format == FORMAT_DELTA) {
1863 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1864 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->counter[i]);
1865 else
1866 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->counter[i]);
1867 } else if (mp->format == FORMAT_PERCENT) {
1868 if (mp->type == COUNTER_USEC)
1869 outp +=
1870 sprintf(outp, "%s%.2f", (printed++ ? delim : ""),
1871 t->counter[i] / interval_float / 10000);
1872 else
1873 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->counter[i] / tsc);
1874 }
1875 }
1876
1877 /* C1 */
1878 if (DO_BIC(BIC_CPU_c1))
1879 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->c1 / tsc);
1880
1881 /* print per-core data only for 1st thread in core */
1882 if (!is_cpu_first_thread_in_core(t, c, p))
1883 goto done;
1884
1885 if (DO_BIC(BIC_CPU_c3))
1886 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c3 / tsc);
1887 if (DO_BIC(BIC_CPU_c6))
1888 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c6 / tsc);
1889 if (DO_BIC(BIC_CPU_c7))
1890 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c7 / tsc);
1891
1892 /* Mod%c6 */
1893 if (DO_BIC(BIC_Mod_c6))
1894 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->mc6_us / tsc);
1895
1896 if (DO_BIC(BIC_CoreTmp))
1897 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_temp_c);
1898
1899 /* Core throttle count */
1900 if (DO_BIC(BIC_CORE_THROT_CNT))
1901 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->core_throt_cnt);
1902
1903 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1904 if (mp->format == FORMAT_RAW) {
1905 if (mp->width == 32)
1906 outp +=
1907 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)c->counter[i]);
1908 else
1909 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), c->counter[i]);
1910 } else if (mp->format == FORMAT_DELTA) {
1911 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1912 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), c->counter[i]);
1913 else
1914 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->counter[i]);
1915 } else if (mp->format == FORMAT_PERCENT) {
1916 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->counter[i] / tsc);
1917 }
1918 }
1919
1920 fmt8 = "%s%.2f";
1921
1922 if (DO_BIC(BIC_CorWatt) && platform->has_per_core_rapl)
1923 outp +=
1924 sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units / interval_float);
1925 if (DO_BIC(BIC_Cor_J) && platform->has_per_core_rapl)
1926 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units);
1927
1928 /* print per-package data only for 1st core in package */
1929 if (!is_cpu_first_core_in_package(t, c, p))
1930 goto done;
1931
1932 /* PkgTmp */
1933 if (DO_BIC(BIC_PkgTmp))
1934 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->pkg_temp_c);
1935
1936 /* GFXrc6 */
1937 if (DO_BIC(BIC_GFX_rc6)) {
1938 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */
1939 outp += sprintf(outp, "%s**.**", (printed++ ? delim : ""));
1940 } else {
1941 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""),
1942 p->gfx_rc6_ms / 10.0 / interval_float);
1943 }
1944 }
1945
1946 /* GFXMHz */
1947 if (DO_BIC(BIC_GFXMHz))
1948 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz);
1949
1950 /* GFXACTMHz */
1951 if (DO_BIC(BIC_GFXACTMHz))
1952 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_act_mhz);
1953
1954 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */
1955 if (DO_BIC(BIC_Totl_c0))
1956 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0 / tsc);
1957 if (DO_BIC(BIC_Any_c0))
1958 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0 / tsc);
1959 if (DO_BIC(BIC_GFX_c0))
1960 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0 / tsc);
1961 if (DO_BIC(BIC_CPUGFX))
1962 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0 / tsc);
1963
1964 if (DO_BIC(BIC_Pkgpc2))
1965 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2 / tsc);
1966 if (DO_BIC(BIC_Pkgpc3))
1967 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc3 / tsc);
1968 if (DO_BIC(BIC_Pkgpc6))
1969 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc6 / tsc);
1970 if (DO_BIC(BIC_Pkgpc7))
1971 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc7 / tsc);
1972 if (DO_BIC(BIC_Pkgpc8))
1973 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc8 / tsc);
1974 if (DO_BIC(BIC_Pkgpc9))
1975 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc9 / tsc);
1976 if (DO_BIC(BIC_Pkgpc10))
1977 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc10 / tsc);
1978
1979 if (DO_BIC(BIC_CPU_LPI))
1980 outp +=
1981 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->cpu_lpi / 1000000.0 / interval_float);
1982 if (DO_BIC(BIC_SYS_LPI))
1983 outp +=
1984 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->sys_lpi / 1000000.0 / interval_float);
1985
1986 if (DO_BIC(BIC_PkgWatt))
1987 outp +=
1988 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units / interval_float);
1989
1990 if (DO_BIC(BIC_CorWatt) && !platform->has_per_core_rapl)
1991 outp +=
1992 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units / interval_float);
1993 if (DO_BIC(BIC_GFXWatt))
1994 outp +=
1995 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units / interval_float);
1996 if (DO_BIC(BIC_RAMWatt))
1997 outp +=
1998 sprintf(outp, fmt8, (printed++ ? delim : ""),
1999 p->energy_dram * rapl_dram_energy_units / interval_float);
2000 if (DO_BIC(BIC_Pkg_J))
2001 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units);
2002 if (DO_BIC(BIC_Cor_J) && !platform->has_per_core_rapl)
2003 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units);
2004 if (DO_BIC(BIC_GFX_J))
2005 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units);
2006 if (DO_BIC(BIC_RAM_J))
2007 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units);
2008 if (DO_BIC(BIC_PKG__))
2009 outp +=
2010 sprintf(outp, fmt8, (printed++ ? delim : ""),
2011 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
2012 if (DO_BIC(BIC_RAM__))
2013 outp +=
2014 sprintf(outp, fmt8, (printed++ ? delim : ""),
2015 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
2016 /* UncMHz */
2017 if (DO_BIC(BIC_UNCORE_MHZ))
2018 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->uncore_mhz);
2019
2020 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
2021 if (mp->format == FORMAT_RAW) {
2022 if (mp->width == 32)
2023 outp +=
2024 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)p->counter[i]);
2025 else
2026 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), p->counter[i]);
2027 } else if (mp->format == FORMAT_DELTA) {
2028 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
2029 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), p->counter[i]);
2030 else
2031 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), p->counter[i]);
2032 } else if (mp->format == FORMAT_PERCENT) {
2033 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->counter[i] / tsc);
2034 }
2035 }
2036
2037 done:
2038 if (*(outp - 1) != '\n')
2039 outp += sprintf(outp, "\n");
2040
2041 return 0;
2042 }
2043
2044 void flush_output_stdout(void)
2045 {
2046 FILE *filep;
2047
2048 if (outf == stderr)
2049 filep = stdout;
2050 else
2051 filep = outf;
2052
2053 fputs(output_buffer, filep);
2054 fflush(filep);
2055
2056 outp = output_buffer;
2057 }
2058
2059 void flush_output_stderr(void)
2060 {
2061 fputs(output_buffer, outf);
2062 fflush(outf);
2063 outp = output_buffer;
2064 }
2065
2066 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2067 {
2068 static int count;
2069
2070 if ((!count || (header_iterations && !(count % header_iterations))) || !summary_only)
2071 print_header("\t");
2072
2073 format_counters(&average.threads, &average.cores, &average.packages);
2074
2075 count++;
2076
2077 if (summary_only)
2078 return;
2079
2080 for_all_cpus(format_counters, t, c, p);
2081 }
2082
2083 #define DELTA_WRAP32(new, old) \
2084 old = ((((unsigned long long)new << 32) - ((unsigned long long)old << 32)) >> 32);
2085
2086 int delta_package(struct pkg_data *new, struct pkg_data *old)
2087 {
2088 int i;
2089 struct msr_counter *mp;
2090
2091 if (DO_BIC(BIC_Totl_c0))
2092 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0;
2093 if (DO_BIC(BIC_Any_c0))
2094 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0;
2095 if (DO_BIC(BIC_GFX_c0))
2096 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0;
2097 if (DO_BIC(BIC_CPUGFX))
2098 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0;
2099
2100 old->pc2 = new->pc2 - old->pc2;
2101 if (DO_BIC(BIC_Pkgpc3))
2102 old->pc3 = new->pc3 - old->pc3;
2103 if (DO_BIC(BIC_Pkgpc6))
2104 old->pc6 = new->pc6 - old->pc6;
2105 if (DO_BIC(BIC_Pkgpc7))
2106 old->pc7 = new->pc7 - old->pc7;
2107 old->pc8 = new->pc8 - old->pc8;
2108 old->pc9 = new->pc9 - old->pc9;
2109 old->pc10 = new->pc10 - old->pc10;
2110 old->cpu_lpi = new->cpu_lpi - old->cpu_lpi;
2111 old->sys_lpi = new->sys_lpi - old->sys_lpi;
2112 old->pkg_temp_c = new->pkg_temp_c;
2113
2114 /* flag an error when rc6 counter resets/wraps */
2115 if (old->gfx_rc6_ms > new->gfx_rc6_ms)
2116 old->gfx_rc6_ms = -1;
2117 else
2118 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms;
2119
2120 old->uncore_mhz = new->uncore_mhz;
2121 old->gfx_mhz = new->gfx_mhz;
2122 old->gfx_act_mhz = new->gfx_act_mhz;
2123
2124 old->energy_pkg = new->energy_pkg - old->energy_pkg;
2125 old->energy_cores = new->energy_cores - old->energy_cores;
2126 old->energy_gfx = new->energy_gfx - old->energy_gfx;
2127 old->energy_dram = new->energy_dram - old->energy_dram;
2128 old->rapl_pkg_perf_status = new->rapl_pkg_perf_status - old->rapl_pkg_perf_status;
2129 old->rapl_dram_perf_status = new->rapl_dram_perf_status - old->rapl_dram_perf_status;
2130
2131 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
2132 if (mp->format == FORMAT_RAW)
2133 old->counter[i] = new->counter[i];
2134 else
2135 old->counter[i] = new->counter[i] - old->counter[i];
2136 }
2137
2138 return 0;
2139 }
2140
2141 void delta_core(struct core_data *new, struct core_data *old)
2142 {
2143 int i;
2144 struct msr_counter *mp;
2145
2146 old->c3 = new->c3 - old->c3;
2147 old->c6 = new->c6 - old->c6;
2148 old->c7 = new->c7 - old->c7;
2149 old->core_temp_c = new->core_temp_c;
2150 old->core_throt_cnt = new->core_throt_cnt;
2151 old->mc6_us = new->mc6_us - old->mc6_us;
2152
2153 DELTA_WRAP32(new->core_energy, old->core_energy);
2154
2155 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
2156 if (mp->format == FORMAT_RAW)
2157 old->counter[i] = new->counter[i];
2158 else
2159 old->counter[i] = new->counter[i] - old->counter[i];
2160 }
2161 }
2162
2163 int soft_c1_residency_display(int bic)
2164 {
2165 if (!DO_BIC(BIC_CPU_c1) || platform->has_msr_core_c1_res)
2166 return 0;
2167
2168 return DO_BIC_READ(bic);
2169 }
2170
2171 /*
2172 * old = new - old
2173 */
2174 int delta_thread(struct thread_data *new, struct thread_data *old, struct core_data *core_delta)
2175 {
2176 int i;
2177 struct msr_counter *mp;
2178
2179 /* we run cpuid just the 1st time, copy the results */
2180 if (DO_BIC(BIC_APIC))
2181 new->apic_id = old->apic_id;
2182 if (DO_BIC(BIC_X2APIC))
2183 new->x2apic_id = old->x2apic_id;
2184
2185 /*
2186 * the timestamps from start of measurement interval are in "old"
2187 * the timestamp from end of measurement interval are in "new"
2188 * over-write old w/ new so we can print end of interval values
2189 */
2190
2191 timersub(&new->tv_begin, &old->tv_begin, &old->tv_delta);
2192 old->tv_begin = new->tv_begin;
2193 old->tv_end = new->tv_end;
2194
2195 old->tsc = new->tsc - old->tsc;
2196
2197 /* check for TSC < 1 Mcycles over interval */
2198 if (old->tsc < (1000 * 1000))
2199 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n"
2200 "You can disable all c-states by booting with \"idle=poll\"\n"
2201 "or just the deep ones with \"processor.max_cstate=1\"");
2202
2203 old->c1 = new->c1 - old->c1;
2204
2205 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || DO_BIC(BIC_IPC)
2206 || soft_c1_residency_display(BIC_Avg_MHz)) {
2207 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) {
2208 old->aperf = new->aperf - old->aperf;
2209 old->mperf = new->mperf - old->mperf;
2210 } else {
2211 return -1;
2212 }
2213 }
2214
2215 if (platform->has_msr_core_c1_res) {
2216 /*
2217 * Some models have a dedicated C1 residency MSR,
2218 * which should be more accurate than the derivation below.
2219 */
2220 } else {
2221 /*
2222 * As counter collection is not atomic,
2223 * it is possible for mperf's non-halted cycles + idle states
2224 * to exceed TSC's all cycles: show c1 = 0% in that case.
2225 */
2226 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak))
2227 old->c1 = 0;
2228 else {
2229 /* normal case, derive c1 */
2230 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3
2231 - core_delta->c6 - core_delta->c7;
2232 }
2233 }
2234
2235 if (old->mperf == 0) {
2236 if (debug > 1)
2237 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id);
2238 old->mperf = 1; /* divide by 0 protection */
2239 }
2240
2241 if (DO_BIC(BIC_IPC))
2242 old->instr_count = new->instr_count - old->instr_count;
2243
2244 if (DO_BIC(BIC_IRQ))
2245 old->irq_count = new->irq_count - old->irq_count;
2246
2247 if (DO_BIC(BIC_SMI))
2248 old->smi_count = new->smi_count - old->smi_count;
2249
2250 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
2251 if (mp->format == FORMAT_RAW)
2252 old->counter[i] = new->counter[i];
2253 else
2254 old->counter[i] = new->counter[i] - old->counter[i];
2255 }
2256 return 0;
2257 }
2258
2259 int delta_cpu(struct thread_data *t, struct core_data *c,
2260 struct pkg_data *p, struct thread_data *t2, struct core_data *c2, struct pkg_data *p2)
2261 {
2262 int retval = 0;
2263
2264 /* calculate core delta only for 1st thread in core */
2265 if (is_cpu_first_thread_in_core(t, c, p))
2266 delta_core(c, c2);
2267
2268 /* always calculate thread delta */
2269 retval = delta_thread(t, t2, c2); /* c2 is core delta */
2270 if (retval)
2271 return retval;
2272
2273 /* calculate package delta only for 1st core in package */
2274 if (is_cpu_first_core_in_package(t, c, p))
2275 retval = delta_package(p, p2);
2276
2277 return retval;
2278 }
2279
2280 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2281 {
2282 int i;
2283 struct msr_counter *mp;
2284
2285 t->tv_begin.tv_sec = 0;
2286 t->tv_begin.tv_usec = 0;
2287 t->tv_end.tv_sec = 0;
2288 t->tv_end.tv_usec = 0;
2289 t->tv_delta.tv_sec = 0;
2290 t->tv_delta.tv_usec = 0;
2291
2292 t->tsc = 0;
2293 t->aperf = 0;
2294 t->mperf = 0;
2295 t->c1 = 0;
2296
2297 t->instr_count = 0;
2298
2299 t->irq_count = 0;
2300 t->smi_count = 0;
2301
2302 c->c3 = 0;
2303 c->c6 = 0;
2304 c->c7 = 0;
2305 c->mc6_us = 0;
2306 c->core_temp_c = 0;
2307 c->core_energy = 0;
2308 c->core_throt_cnt = 0;
2309
2310 p->pkg_wtd_core_c0 = 0;
2311 p->pkg_any_core_c0 = 0;
2312 p->pkg_any_gfxe_c0 = 0;
2313 p->pkg_both_core_gfxe_c0 = 0;
2314
2315 p->pc2 = 0;
2316 if (DO_BIC(BIC_Pkgpc3))
2317 p->pc3 = 0;
2318 if (DO_BIC(BIC_Pkgpc6))
2319 p->pc6 = 0;
2320 if (DO_BIC(BIC_Pkgpc7))
2321 p->pc7 = 0;
2322 p->pc8 = 0;
2323 p->pc9 = 0;
2324 p->pc10 = 0;
2325 p->cpu_lpi = 0;
2326 p->sys_lpi = 0;
2327
2328 p->energy_pkg = 0;
2329 p->energy_dram = 0;
2330 p->energy_cores = 0;
2331 p->energy_gfx = 0;
2332 p->rapl_pkg_perf_status = 0;
2333 p->rapl_dram_perf_status = 0;
2334 p->pkg_temp_c = 0;
2335
2336 p->gfx_rc6_ms = 0;
2337 p->uncore_mhz = 0;
2338 p->gfx_mhz = 0;
2339 p->gfx_act_mhz = 0;
2340 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next)
2341 t->counter[i] = 0;
2342
2343 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next)
2344 c->counter[i] = 0;
2345
2346 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next)
2347 p->counter[i] = 0;
2348 }
2349
2350 int sum_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2351 {
2352 int i;
2353 struct msr_counter *mp;
2354
2355 /* copy un-changing apic_id's */
2356 if (DO_BIC(BIC_APIC))
2357 average.threads.apic_id = t->apic_id;
2358 if (DO_BIC(BIC_X2APIC))
2359 average.threads.x2apic_id = t->x2apic_id;
2360
2361 /* remember first tv_begin */
2362 if (average.threads.tv_begin.tv_sec == 0)
2363 average.threads.tv_begin = t->tv_begin;
2364
2365 /* remember last tv_end */
2366 average.threads.tv_end = t->tv_end;
2367
2368 average.threads.tsc += t->tsc;
2369 average.threads.aperf += t->aperf;
2370 average.threads.mperf += t->mperf;
2371 average.threads.c1 += t->c1;
2372
2373 average.threads.instr_count += t->instr_count;
2374
2375 average.threads.irq_count += t->irq_count;
2376 average.threads.smi_count += t->smi_count;
2377
2378 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
2379 if (mp->format == FORMAT_RAW)
2380 continue;
2381 average.threads.counter[i] += t->counter[i];
2382 }
2383
2384 /* sum per-core values only for 1st thread in core */
2385 if (!is_cpu_first_thread_in_core(t, c, p))
2386 return 0;
2387
2388 average.cores.c3 += c->c3;
2389 average.cores.c6 += c->c6;
2390 average.cores.c7 += c->c7;
2391 average.cores.mc6_us += c->mc6_us;
2392
2393 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c);
2394 average.cores.core_throt_cnt = MAX(average.cores.core_throt_cnt, c->core_throt_cnt);
2395
2396 average.cores.core_energy += c->core_energy;
2397
2398 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
2399 if (mp->format == FORMAT_RAW)
2400 continue;
2401 average.cores.counter[i] += c->counter[i];
2402 }
2403
2404 /* sum per-pkg values only for 1st core in pkg */
2405 if (!is_cpu_first_core_in_package(t, c, p))
2406 return 0;
2407
2408 if (DO_BIC(BIC_Totl_c0))
2409 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0;
2410 if (DO_BIC(BIC_Any_c0))
2411 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0;
2412 if (DO_BIC(BIC_GFX_c0))
2413 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0;
2414 if (DO_BIC(BIC_CPUGFX))
2415 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0;
2416
2417 average.packages.pc2 += p->pc2;
2418 if (DO_BIC(BIC_Pkgpc3))
2419 average.packages.pc3 += p->pc3;
2420 if (DO_BIC(BIC_Pkgpc6))
2421 average.packages.pc6 += p->pc6;
2422 if (DO_BIC(BIC_Pkgpc7))
2423 average.packages.pc7 += p->pc7;
2424 average.packages.pc8 += p->pc8;
2425 average.packages.pc9 += p->pc9;
2426 average.packages.pc10 += p->pc10;
2427
2428 average.packages.cpu_lpi = p->cpu_lpi;
2429 average.packages.sys_lpi = p->sys_lpi;
2430
2431 average.packages.energy_pkg += p->energy_pkg;
2432 average.packages.energy_dram += p->energy_dram;
2433 average.packages.energy_cores += p->energy_cores;
2434 average.packages.energy_gfx += p->energy_gfx;
2435
2436 average.packages.gfx_rc6_ms = p->gfx_rc6_ms;
2437 average.packages.uncore_mhz = p->uncore_mhz;
2438 average.packages.gfx_mhz = p->gfx_mhz;
2439 average.packages.gfx_act_mhz = p->gfx_act_mhz;
2440
2441 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c);
2442
2443 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status;
2444 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status;
2445
2446 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
2447 if ((mp->format == FORMAT_RAW) && (topo.num_packages == 0))
2448 average.packages.counter[i] = p->counter[i];
2449 else
2450 average.packages.counter[i] += p->counter[i];
2451 }
2452 return 0;
2453 }
2454
2455 /*
2456 * sum the counters for all cpus in the system
2457 * compute the weighted average
2458 */
2459 void compute_average(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2460 {
2461 int i;
2462 struct msr_counter *mp;
2463
2464 clear_counters(&average.threads, &average.cores, &average.packages);
2465
2466 for_all_cpus(sum_counters, t, c, p);
2467
2468 /* Use the global time delta for the average. */
2469 average.threads.tv_delta = tv_delta;
2470
2471 average.threads.tsc /= topo.allowed_cpus;
2472 average.threads.aperf /= topo.allowed_cpus;
2473 average.threads.mperf /= topo.allowed_cpus;
2474 average.threads.instr_count /= topo.allowed_cpus;
2475 average.threads.c1 /= topo.allowed_cpus;
2476
2477 if (average.threads.irq_count > 9999999)
2478 sums_need_wide_columns = 1;
2479
2480 average.cores.c3 /= topo.allowed_cores;
2481 average.cores.c6 /= topo.allowed_cores;
2482 average.cores.c7 /= topo.allowed_cores;
2483 average.cores.mc6_us /= topo.allowed_cores;
2484
2485 if (DO_BIC(BIC_Totl_c0))
2486 average.packages.pkg_wtd_core_c0 /= topo.allowed_packages;
2487 if (DO_BIC(BIC_Any_c0))
2488 average.packages.pkg_any_core_c0 /= topo.allowed_packages;
2489 if (DO_BIC(BIC_GFX_c0))
2490 average.packages.pkg_any_gfxe_c0 /= topo.allowed_packages;
2491 if (DO_BIC(BIC_CPUGFX))
2492 average.packages.pkg_both_core_gfxe_c0 /= topo.allowed_packages;
2493
2494 average.packages.pc2 /= topo.allowed_packages;
2495 if (DO_BIC(BIC_Pkgpc3))
2496 average.packages.pc3 /= topo.allowed_packages;
2497 if (DO_BIC(BIC_Pkgpc6))
2498 average.packages.pc6 /= topo.allowed_packages;
2499 if (DO_BIC(BIC_Pkgpc7))
2500 average.packages.pc7 /= topo.allowed_packages;
2501
2502 average.packages.pc8 /= topo.allowed_packages;
2503 average.packages.pc9 /= topo.allowed_packages;
2504 average.packages.pc10 /= topo.allowed_packages;
2505
2506 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
2507 if (mp->format == FORMAT_RAW)
2508 continue;
2509 if (mp->type == COUNTER_ITEMS) {
2510 if (average.threads.counter[i] > 9999999)
2511 sums_need_wide_columns = 1;
2512 continue;
2513 }
2514 average.threads.counter[i] /= topo.allowed_cpus;
2515 }
2516 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
2517 if (mp->format == FORMAT_RAW)
2518 continue;
2519 if (mp->type == COUNTER_ITEMS) {
2520 if (average.cores.counter[i] > 9999999)
2521 sums_need_wide_columns = 1;
2522 }
2523 average.cores.counter[i] /= topo.allowed_cores;
2524 }
2525 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
2526 if (mp->format == FORMAT_RAW)
2527 continue;
2528 if (mp->type == COUNTER_ITEMS) {
2529 if (average.packages.counter[i] > 9999999)
2530 sums_need_wide_columns = 1;
2531 }
2532 average.packages.counter[i] /= topo.allowed_packages;
2533 }
2534 }
2535
2536 static unsigned long long rdtsc(void)
2537 {
2538 unsigned int low, high;
2539
2540 asm volatile ("rdtsc":"=a" (low), "=d"(high));
2541
2542 return low | ((unsigned long long)high) << 32;
2543 }
2544
2545 /*
2546 * Open a file, and exit on failure
2547 */
2548 FILE *fopen_or_die(const char *path, const char *mode)
2549 {
2550 FILE *filep = fopen(path, mode);
2551
2552 if (!filep)
2553 err(1, "%s: open failed", path);
2554 return filep;
2555 }
2556
2557 /*
2558 * snapshot_sysfs_counter()
2559 *
2560 * return snapshot of given counter
2561 */
2562 unsigned long long snapshot_sysfs_counter(char *path)
2563 {
2564 FILE *fp;
2565 int retval;
2566 unsigned long long counter;
2567
2568 fp = fopen_or_die(path, "r");
2569
2570 retval = fscanf(fp, "%lld", &counter);
2571 if (retval != 1)
2572 err(1, "snapshot_sysfs_counter(%s)", path);
2573
2574 fclose(fp);
2575
2576 return counter;
2577 }
2578
2579 int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp)
2580 {
2581 if (mp->msr_num != 0) {
2582 if (get_msr(cpu, mp->msr_num, counterp))
2583 return -1;
2584 } else {
2585 char path[128 + PATH_BYTES];
2586
2587 if (mp->flags & SYSFS_PERCPU) {
2588 sprintf(path, "/sys/devices/system/cpu/cpu%d/%s", cpu, mp->path);
2589
2590 *counterp = snapshot_sysfs_counter(path);
2591 } else {
2592 *counterp = snapshot_sysfs_counter(mp->path);
2593 }
2594 }
2595
2596 return 0;
2597 }
2598
2599 unsigned long long get_uncore_mhz(int package, int die)
2600 {
2601 char path[128];
2602
2603 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/current_freq_khz", package,
2604 die);
2605
2606 return (snapshot_sysfs_counter(path) / 1000);
2607 }
2608
2609 int get_epb(int cpu)
2610 {
2611 char path[128 + PATH_BYTES];
2612 unsigned long long msr;
2613 int ret, epb = -1;
2614 FILE *fp;
2615
2616 sprintf(path, "/sys/devices/system/cpu/cpu%d/power/energy_perf_bias", cpu);
2617
2618 fp = fopen(path, "r");
2619 if (!fp)
2620 goto msr_fallback;
2621
2622 ret = fscanf(fp, "%d", &epb);
2623 if (ret != 1)
2624 err(1, "%s(%s)", __func__, path);
2625
2626 fclose(fp);
2627
2628 return epb;
2629
2630 msr_fallback:
2631 get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr);
2632
2633 return msr & 0xf;
2634 }
2635
2636 void get_apic_id(struct thread_data *t)
2637 {
2638 unsigned int eax, ebx, ecx, edx;
2639
2640 if (DO_BIC(BIC_APIC)) {
2641 eax = ebx = ecx = edx = 0;
2642 __cpuid(1, eax, ebx, ecx, edx);
2643
2644 t->apic_id = (ebx >> 24) & 0xff;
2645 }
2646
2647 if (!DO_BIC(BIC_X2APIC))
2648 return;
2649
2650 if (authentic_amd || hygon_genuine) {
2651 unsigned int topology_extensions;
2652
2653 if (max_extended_level < 0x8000001e)
2654 return;
2655
2656 eax = ebx = ecx = edx = 0;
2657 __cpuid(0x80000001, eax, ebx, ecx, edx);
2658 topology_extensions = ecx & (1 << 22);
2659
2660 if (topology_extensions == 0)
2661 return;
2662
2663 eax = ebx = ecx = edx = 0;
2664 __cpuid(0x8000001e, eax, ebx, ecx, edx);
2665
2666 t->x2apic_id = eax;
2667 return;
2668 }
2669
2670 if (!genuine_intel)
2671 return;
2672
2673 if (max_level < 0xb)
2674 return;
2675
2676 ecx = 0;
2677 __cpuid(0xb, eax, ebx, ecx, edx);
2678 t->x2apic_id = edx;
2679
2680 if (debug && (t->apic_id != (t->x2apic_id & 0xff)))
2681 fprintf(outf, "cpu%d: BIOS BUG: apic 0x%x x2apic 0x%x\n", t->cpu_id, t->apic_id, t->x2apic_id);
2682 }
2683
2684 int get_core_throt_cnt(int cpu, unsigned long long *cnt)
2685 {
2686 char path[128 + PATH_BYTES];
2687 unsigned long long tmp;
2688 FILE *fp;
2689 int ret;
2690
2691 sprintf(path, "/sys/devices/system/cpu/cpu%d/thermal_throttle/core_throttle_count", cpu);
2692 fp = fopen(path, "r");
2693 if (!fp)
2694 return -1;
2695 ret = fscanf(fp, "%lld", &tmp);
2696 fclose(fp);
2697 if (ret != 1)
2698 return -1;
2699 *cnt = tmp;
2700
2701 return 0;
2702 }
2703
2704 /*
2705 * get_counters(...)
2706 * migrate to cpu
2707 * acquire and record local counters for that cpu
2708 */
2709 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2710 {
2711 int cpu = t->cpu_id;
2712 unsigned long long msr;
2713 int aperf_mperf_retry_count = 0;
2714 struct msr_counter *mp;
2715 int i;
2716
2717 if (cpu_migrate(cpu)) {
2718 fprintf(outf, "get_counters: Could not migrate to CPU %d\n", cpu);
2719 return -1;
2720 }
2721
2722 gettimeofday(&t->tv_begin, (struct timezone *)NULL);
2723
2724 if (first_counter_read)
2725 get_apic_id(t);
2726 retry:
2727 t->tsc = rdtsc(); /* we are running on local CPU of interest */
2728
2729 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || DO_BIC(BIC_IPC)
2730 || soft_c1_residency_display(BIC_Avg_MHz)) {
2731 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time;
2732
2733 /*
2734 * The TSC, APERF and MPERF must be read together for
2735 * APERF/MPERF and MPERF/TSC to give accurate results.
2736 *
2737 * Unfortunately, APERF and MPERF are read by
2738 * individual system call, so delays may occur
2739 * between them. If the time to read them
2740 * varies by a large amount, we re-read them.
2741 */
2742
2743 /*
2744 * This initial dummy APERF read has been seen to
2745 * reduce jitter in the subsequent reads.
2746 */
2747
2748 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
2749 return -3;
2750
2751 t->tsc = rdtsc(); /* re-read close to APERF */
2752
2753 tsc_before = t->tsc;
2754
2755 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
2756 return -3;
2757
2758 tsc_between = rdtsc();
2759
2760 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf))
2761 return -4;
2762
2763 tsc_after = rdtsc();
2764
2765 aperf_time = tsc_between - tsc_before;
2766 mperf_time = tsc_after - tsc_between;
2767
2768 /*
2769 * If the system call latency to read APERF and MPERF
2770 * differ by more than 2x, then try again.
2771 */
2772 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) {
2773 aperf_mperf_retry_count++;
2774 if (aperf_mperf_retry_count < 5)
2775 goto retry;
2776 else
2777 warnx("cpu%d jitter %lld %lld", cpu, aperf_time, mperf_time);
2778 }
2779 aperf_mperf_retry_count = 0;
2780
2781 t->aperf = t->aperf * aperf_mperf_multiplier;
2782 t->mperf = t->mperf * aperf_mperf_multiplier;
2783 }
2784
2785 if (DO_BIC(BIC_IPC))
2786 if (read(get_instr_count_fd(cpu), &t->instr_count, sizeof(long long)) != sizeof(long long))
2787 return -4;
2788
2789 if (DO_BIC(BIC_IRQ))
2790 t->irq_count = irqs_per_cpu[cpu];
2791 if (DO_BIC(BIC_SMI)) {
2792 if (get_msr(cpu, MSR_SMI_COUNT, &msr))
2793 return -5;
2794 t->smi_count = msr & 0xFFFFFFFF;
2795 }
2796 if (DO_BIC(BIC_CPU_c1) && platform->has_msr_core_c1_res) {
2797 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1))
2798 return -6;
2799 }
2800
2801 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
2802 if (get_mp(cpu, mp, &t->counter[i]))
2803 return -10;
2804 }
2805
2806 /* collect core counters only for 1st thread in core */
2807 if (!is_cpu_first_thread_in_core(t, c, p))
2808 goto done;
2809
2810 if (DO_BIC(BIC_CPU_c3) || soft_c1_residency_display(BIC_CPU_c3)) {
2811 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3))
2812 return -6;
2813 }
2814
2815 if ((DO_BIC(BIC_CPU_c6) || soft_c1_residency_display(BIC_CPU_c6)) && !platform->has_msr_knl_core_c6_residency) {
2816 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6))
2817 return -7;
2818 } else if (platform->has_msr_knl_core_c6_residency && soft_c1_residency_display(BIC_CPU_c6)) {
2819 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6))
2820 return -7;
2821 }
2822
2823 if (DO_BIC(BIC_CPU_c7) || soft_c1_residency_display(BIC_CPU_c7)) {
2824 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7))
2825 return -8;
2826 else if (t->is_atom) {
2827 /*
2828 * For Atom CPUs that has core cstate deeper than c6,
2829 * MSR_CORE_C6_RESIDENCY returns residency of cc6 and deeper.
2830 * Minus CC7 (and deeper cstates) residency to get
2831 * accturate cc6 residency.
2832 */
2833 c->c6 -= c->c7;
2834 }
2835 }
2836
2837 if (DO_BIC(BIC_Mod_c6))
2838 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us))
2839 return -8;
2840
2841 if (DO_BIC(BIC_CoreTmp)) {
2842 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
2843 return -9;
2844 c->core_temp_c = tj_max - ((msr >> 16) & 0x7F);
2845 }
2846
2847 if (DO_BIC(BIC_CORE_THROT_CNT))
2848 get_core_throt_cnt(cpu, &c->core_throt_cnt);
2849
2850 if (platform->rapl_msrs & RAPL_AMD_F17H) {
2851 if (get_msr(cpu, MSR_CORE_ENERGY_STAT, &msr))
2852 return -14;
2853 c->core_energy = msr & 0xFFFFFFFF;
2854 }
2855
2856 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
2857 if (get_mp(cpu, mp, &c->counter[i]))
2858 return -10;
2859 }
2860
2861 /* collect package counters only for 1st core in package */
2862 if (!is_cpu_first_core_in_package(t, c, p))
2863 goto done;
2864
2865 if (DO_BIC(BIC_Totl_c0)) {
2866 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0))
2867 return -10;
2868 }
2869 if (DO_BIC(BIC_Any_c0)) {
2870 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0))
2871 return -11;
2872 }
2873 if (DO_BIC(BIC_GFX_c0)) {
2874 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0))
2875 return -12;
2876 }
2877 if (DO_BIC(BIC_CPUGFX)) {
2878 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0))
2879 return -13;
2880 }
2881 if (DO_BIC(BIC_Pkgpc3))
2882 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3))
2883 return -9;
2884 if (DO_BIC(BIC_Pkgpc6)) {
2885 if (platform->has_msr_atom_pkg_c6_residency) {
2886 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6))
2887 return -10;
2888 } else {
2889 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6))
2890 return -10;
2891 }
2892 }
2893
2894 if (DO_BIC(BIC_Pkgpc2))
2895 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2))
2896 return -11;
2897 if (DO_BIC(BIC_Pkgpc7))
2898 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7))
2899 return -12;
2900 if (DO_BIC(BIC_Pkgpc8))
2901 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8))
2902 return -13;
2903 if (DO_BIC(BIC_Pkgpc9))
2904 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9))
2905 return -13;
2906 if (DO_BIC(BIC_Pkgpc10))
2907 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10))
2908 return -13;
2909
2910 if (DO_BIC(BIC_CPU_LPI))
2911 p->cpu_lpi = cpuidle_cur_cpu_lpi_us;
2912 if (DO_BIC(BIC_SYS_LPI))
2913 p->sys_lpi = cpuidle_cur_sys_lpi_us;
2914
2915 if (platform->rapl_msrs & RAPL_PKG) {
2916 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STATUS, &msr))
2917 return -13;
2918 p->energy_pkg = msr;
2919 }
2920 if (platform->rapl_msrs & RAPL_CORE_ENERGY_STATUS) {
2921 if (get_msr_sum(cpu, MSR_PP0_ENERGY_STATUS, &msr))
2922 return -14;
2923 p->energy_cores = msr;
2924 }
2925 if (platform->rapl_msrs & RAPL_DRAM) {
2926 if (get_msr_sum(cpu, MSR_DRAM_ENERGY_STATUS, &msr))
2927 return -15;
2928 p->energy_dram = msr;
2929 }
2930 if (platform->rapl_msrs & RAPL_GFX) {
2931 if (get_msr_sum(cpu, MSR_PP1_ENERGY_STATUS, &msr))
2932 return -16;
2933 p->energy_gfx = msr;
2934 }
2935 if (platform->rapl_msrs & RAPL_PKG_PERF_STATUS) {
2936 if (get_msr_sum(cpu, MSR_PKG_PERF_STATUS, &msr))
2937 return -16;
2938 p->rapl_pkg_perf_status = msr;
2939 }
2940 if (platform->rapl_msrs & RAPL_DRAM_PERF_STATUS) {
2941 if (get_msr_sum(cpu, MSR_DRAM_PERF_STATUS, &msr))
2942 return -16;
2943 p->rapl_dram_perf_status = msr;
2944 }
2945 if (platform->rapl_msrs & RAPL_AMD_F17H) {
2946 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STAT, &msr))
2947 return -13;
2948 p->energy_pkg = msr;
2949 }
2950 if (DO_BIC(BIC_PkgTmp)) {
2951 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
2952 return -17;
2953 p->pkg_temp_c = tj_max - ((msr >> 16) & 0x7F);
2954 }
2955
2956 if (DO_BIC(BIC_GFX_rc6))
2957 p->gfx_rc6_ms = gfx_cur_rc6_ms;
2958
2959 /* n.b. assume die0 uncore frequency applies to whole package */
2960 if (DO_BIC(BIC_UNCORE_MHZ))
2961 p->uncore_mhz = get_uncore_mhz(p->package_id, 0);
2962
2963 if (DO_BIC(BIC_GFXMHz))
2964 p->gfx_mhz = gfx_cur_mhz;
2965
2966 if (DO_BIC(BIC_GFXACTMHz))
2967 p->gfx_act_mhz = gfx_act_mhz;
2968
2969 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
2970 if (get_mp(cpu, mp, &p->counter[i]))
2971 return -10;
2972 }
2973 done:
2974 gettimeofday(&t->tv_end, (struct timezone *)NULL);
2975
2976 return 0;
2977 }
2978
2979 /*
2980 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit:
2981 * If you change the values, note they are used both in comparisons
2982 * (>= PCL__7) and to index pkg_cstate_limit_strings[].
2983 */
2984
2985 #define PCLUKN 0 /* Unknown */
2986 #define PCLRSV 1 /* Reserved */
2987 #define PCL__0 2 /* PC0 */
2988 #define PCL__1 3 /* PC1 */
2989 #define PCL__2 4 /* PC2 */
2990 #define PCL__3 5 /* PC3 */
2991 #define PCL__4 6 /* PC4 */
2992 #define PCL__6 7 /* PC6 */
2993 #define PCL_6N 8 /* PC6 No Retention */
2994 #define PCL_6R 9 /* PC6 Retention */
2995 #define PCL__7 10 /* PC7 */
2996 #define PCL_7S 11 /* PC7 Shrink */
2997 #define PCL__8 12 /* PC8 */
2998 #define PCL__9 13 /* PC9 */
2999 #define PCL_10 14 /* PC10 */
3000 #define PCLUNL 15 /* Unlimited */
3001
3002 int pkg_cstate_limit = PCLUKN;
3003 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2",
3004 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "pc10", "unlimited"
3005 };
3006
3007 int nhm_pkg_cstate_limits[16] =
3008 { PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
3009 PCLRSV, PCLRSV
3010 };
3011
3012 int snb_pkg_cstate_limits[16] =
3013 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
3014 PCLRSV, PCLRSV
3015 };
3016
3017 int hsw_pkg_cstate_limits[16] =
3018 { PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
3019 PCLRSV, PCLRSV
3020 };
3021
3022 int slv_pkg_cstate_limits[16] =
3023 { PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
3024 PCL__6, PCL__7
3025 };
3026
3027 int amt_pkg_cstate_limits[16] =
3028 { PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
3029 PCLRSV, PCLRSV
3030 };
3031
3032 int phi_pkg_cstate_limits[16] =
3033 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
3034 PCLRSV, PCLRSV
3035 };
3036
3037 int glm_pkg_cstate_limits[16] =
3038 { PCLUNL, PCL__1, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCL_10, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
3039 PCLRSV, PCLRSV
3040 };
3041
3042 int skx_pkg_cstate_limits[16] =
3043 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
3044 PCLRSV, PCLRSV
3045 };
3046
3047 int icx_pkg_cstate_limits[16] =
3048 { PCL__0, PCL__2, PCL__6, PCL__6, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
3049 PCLRSV, PCLRSV
3050 };
3051
3052 void probe_cst_limit(void)
3053 {
3054 unsigned long long msr;
3055 int *pkg_cstate_limits;
3056
3057 if (!platform->has_nhm_msrs)
3058 return;
3059
3060 switch (platform->cst_limit) {
3061 case CST_LIMIT_NHM:
3062 pkg_cstate_limits = nhm_pkg_cstate_limits;
3063 break;
3064 case CST_LIMIT_SNB:
3065 pkg_cstate_limits = snb_pkg_cstate_limits;
3066 break;
3067 case CST_LIMIT_HSW:
3068 pkg_cstate_limits = hsw_pkg_cstate_limits;
3069 break;
3070 case CST_LIMIT_SKX:
3071 pkg_cstate_limits = skx_pkg_cstate_limits;
3072 break;
3073 case CST_LIMIT_ICX:
3074 pkg_cstate_limits = icx_pkg_cstate_limits;
3075 break;
3076 case CST_LIMIT_SLV:
3077 pkg_cstate_limits = slv_pkg_cstate_limits;
3078 break;
3079 case CST_LIMIT_AMT:
3080 pkg_cstate_limits = amt_pkg_cstate_limits;
3081 break;
3082 case CST_LIMIT_KNL:
3083 pkg_cstate_limits = phi_pkg_cstate_limits;
3084 break;
3085 case CST_LIMIT_GMT:
3086 pkg_cstate_limits = glm_pkg_cstate_limits;
3087 break;
3088 default:
3089 return;
3090 }
3091
3092 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
3093 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
3094 }
3095
3096 static void dump_platform_info(void)
3097 {
3098 unsigned long long msr;
3099 unsigned int ratio;
3100
3101 if (!platform->has_nhm_msrs)
3102 return;
3103
3104 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
3105
3106 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr);
3107
3108 ratio = (msr >> 40) & 0xFF;
3109 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", ratio, bclk, ratio * bclk);
3110
3111 ratio = (msr >> 8) & 0xFF;
3112 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk);
3113 }
3114
3115 static void dump_power_ctl(void)
3116 {
3117 unsigned long long msr;
3118
3119 if (!platform->has_nhm_msrs)
3120 return;
3121
3122 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr);
3123 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n",
3124 base_cpu, msr, msr & 0x2 ? "EN" : "DIS");
3125
3126 /* C-state Pre-wake Disable (CSTATE_PREWAKE_DISABLE) */
3127 if (platform->has_cst_prewake_bit)
3128 fprintf(outf, "C-state Pre-wake: %sabled\n", msr & 0x40000000 ? "DIS" : "EN");
3129
3130 return;
3131 }
3132
3133 static void dump_turbo_ratio_limit2(void)
3134 {
3135 unsigned long long msr;
3136 unsigned int ratio;
3137
3138 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr);
3139
3140 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr);
3141
3142 ratio = (msr >> 8) & 0xFF;
3143 if (ratio)
3144 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", ratio, bclk, ratio * bclk);
3145
3146 ratio = (msr >> 0) & 0xFF;
3147 if (ratio)
3148 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", ratio, bclk, ratio * bclk);
3149 return;
3150 }
3151
3152 static void dump_turbo_ratio_limit1(void)
3153 {
3154 unsigned long long msr;
3155 unsigned int ratio;
3156
3157 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr);
3158
3159 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr);
3160
3161 ratio = (msr >> 56) & 0xFF;
3162 if (ratio)
3163 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", ratio, bclk, ratio * bclk);
3164
3165 ratio = (msr >> 48) & 0xFF;
3166 if (ratio)
3167 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", ratio, bclk, ratio * bclk);
3168
3169 ratio = (msr >> 40) & 0xFF;
3170 if (ratio)
3171 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", ratio, bclk, ratio * bclk);
3172
3173 ratio = (msr >> 32) & 0xFF;
3174 if (ratio)
3175 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", ratio, bclk, ratio * bclk);
3176
3177 ratio = (msr >> 24) & 0xFF;
3178 if (ratio)
3179 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", ratio, bclk, ratio * bclk);
3180
3181 ratio = (msr >> 16) & 0xFF;
3182 if (ratio)
3183 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", ratio, bclk, ratio * bclk);
3184
3185 ratio = (msr >> 8) & 0xFF;
3186 if (ratio)
3187 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", ratio, bclk, ratio * bclk);
3188
3189 ratio = (msr >> 0) & 0xFF;
3190 if (ratio)
3191 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", ratio, bclk, ratio * bclk);
3192 return;
3193 }
3194
3195 static void dump_turbo_ratio_limits(int trl_msr_offset)
3196 {
3197 unsigned long long msr, core_counts;
3198 int shift;
3199
3200 get_msr(base_cpu, trl_msr_offset, &msr);
3201 fprintf(outf, "cpu%d: MSR_%sTURBO_RATIO_LIMIT: 0x%08llx\n",
3202 base_cpu, trl_msr_offset == MSR_SECONDARY_TURBO_RATIO_LIMIT ? "SECONDARY_" : "", msr);
3203
3204 if (platform->trl_msrs & TRL_CORECOUNT) {
3205 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts);
3206 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts);
3207 } else {
3208 core_counts = 0x0807060504030201;
3209 }
3210
3211 for (shift = 56; shift >= 0; shift -= 8) {
3212 unsigned int ratio, group_size;
3213
3214 ratio = (msr >> shift) & 0xFF;
3215 group_size = (core_counts >> shift) & 0xFF;
3216 if (ratio)
3217 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
3218 ratio, bclk, ratio * bclk, group_size);
3219 }
3220
3221 return;
3222 }
3223
3224 static void dump_atom_turbo_ratio_limits(void)
3225 {
3226 unsigned long long msr;
3227 unsigned int ratio;
3228
3229 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr);
3230 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
3231
3232 ratio = (msr >> 0) & 0x3F;
3233 if (ratio)
3234 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", ratio, bclk, ratio * bclk);
3235
3236 ratio = (msr >> 8) & 0x3F;
3237 if (ratio)
3238 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", ratio, bclk, ratio * bclk);
3239
3240 ratio = (msr >> 16) & 0x3F;
3241 if (ratio)
3242 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk);
3243
3244 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr);
3245 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
3246
3247 ratio = (msr >> 24) & 0x3F;
3248 if (ratio)
3249 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", ratio, bclk, ratio * bclk);
3250
3251 ratio = (msr >> 16) & 0x3F;
3252 if (ratio)
3253 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", ratio, bclk, ratio * bclk);
3254
3255 ratio = (msr >> 8) & 0x3F;
3256 if (ratio)
3257 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", ratio, bclk, ratio * bclk);
3258
3259 ratio = (msr >> 0) & 0x3F;
3260 if (ratio)
3261 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", ratio, bclk, ratio * bclk);
3262 }
3263
3264 static void dump_knl_turbo_ratio_limits(void)
3265 {
3266 const unsigned int buckets_no = 7;
3267
3268 unsigned long long msr;
3269 int delta_cores, delta_ratio;
3270 int i, b_nr;
3271 unsigned int cores[buckets_no];
3272 unsigned int ratio[buckets_no];
3273
3274 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
3275
3276 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr);
3277
3278 /*
3279 * Turbo encoding in KNL is as follows:
3280 * [0] -- Reserved
3281 * [7:1] -- Base value of number of active cores of bucket 1.
3282 * [15:8] -- Base value of freq ratio of bucket 1.
3283 * [20:16] -- +ve delta of number of active cores of bucket 2.
3284 * i.e. active cores of bucket 2 =
3285 * active cores of bucket 1 + delta
3286 * [23:21] -- Negative delta of freq ratio of bucket 2.
3287 * i.e. freq ratio of bucket 2 =
3288 * freq ratio of bucket 1 - delta
3289 * [28:24]-- +ve delta of number of active cores of bucket 3.
3290 * [31:29]-- -ve delta of freq ratio of bucket 3.
3291 * [36:32]-- +ve delta of number of active cores of bucket 4.
3292 * [39:37]-- -ve delta of freq ratio of bucket 4.
3293 * [44:40]-- +ve delta of number of active cores of bucket 5.
3294 * [47:45]-- -ve delta of freq ratio of bucket 5.
3295 * [52:48]-- +ve delta of number of active cores of bucket 6.
3296 * [55:53]-- -ve delta of freq ratio of bucket 6.
3297 * [60:56]-- +ve delta of number of active cores of bucket 7.
3298 * [63:61]-- -ve delta of freq ratio of bucket 7.
3299 */
3300
3301 b_nr = 0;
3302 cores[b_nr] = (msr & 0xFF) >> 1;
3303 ratio[b_nr] = (msr >> 8) & 0xFF;
3304
3305 for (i = 16; i < 64; i += 8) {
3306 delta_cores = (msr >> i) & 0x1F;
3307 delta_ratio = (msr >> (i + 5)) & 0x7;
3308
3309 cores[b_nr + 1] = cores[b_nr] + delta_cores;
3310 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio;
3311 b_nr++;
3312 }
3313
3314 for (i = buckets_no - 1; i >= 0; i--)
3315 if (i > 0 ? ratio[i] != ratio[i - 1] : 1)
3316 fprintf(outf,
3317 "%d * %.1f = %.1f MHz max turbo %d active cores\n",
3318 ratio[i], bclk, ratio[i] * bclk, cores[i]);
3319 }
3320
3321 static void dump_cst_cfg(void)
3322 {
3323 unsigned long long msr;
3324
3325 if (!platform->has_nhm_msrs)
3326 return;
3327
3328 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
3329
3330 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr);
3331
3332 fprintf(outf, " (%s%s%s%s%slocked, pkg-cstate-limit=%d (%s)",
3333 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "",
3334 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "",
3335 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "",
3336 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "",
3337 (msr & (1 << 15)) ? "" : "UN", (unsigned int)msr & 0xF, pkg_cstate_limit_strings[pkg_cstate_limit]);
3338
3339 #define AUTOMATIC_CSTATE_CONVERSION (1UL << 16)
3340 if (platform->has_cst_auto_convension) {
3341 fprintf(outf, ", automatic c-state conversion=%s", (msr & AUTOMATIC_CSTATE_CONVERSION) ? "on" : "off");
3342 }
3343
3344 fprintf(outf, ")\n");
3345
3346 return;
3347 }
3348
3349 static void dump_config_tdp(void)
3350 {
3351 unsigned long long msr;
3352
3353 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr);
3354 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr);
3355 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF);
3356
3357 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr);
3358 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr);
3359 if (msr) {
3360 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
3361 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
3362 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
3363 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF);
3364 }
3365 fprintf(outf, ")\n");
3366
3367 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr);
3368 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr);
3369 if (msr) {
3370 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
3371 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
3372 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
3373 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF);
3374 }
3375 fprintf(outf, ")\n");
3376
3377 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr);
3378 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr);
3379 if ((msr) & 0x3)
3380 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3);
3381 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
3382 fprintf(outf, ")\n");
3383
3384 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr);
3385 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr);
3386 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF);
3387 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
3388 fprintf(outf, ")\n");
3389 }
3390
3391 unsigned int irtl_time_units[] = { 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
3392
3393 void print_irtl(void)
3394 {
3395 unsigned long long msr;
3396
3397 if (!platform->has_irtl_msrs)
3398 return;
3399
3400 if (platform->supported_cstates & PC3) {
3401 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr);
3402 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr);
3403 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
3404 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
3405 }
3406
3407 if (platform->supported_cstates & PC6) {
3408 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr);
3409 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr);
3410 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
3411 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
3412 }
3413
3414 if (platform->supported_cstates & PC7) {
3415 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr);
3416 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr);
3417 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
3418 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
3419 }
3420
3421 if (platform->supported_cstates & PC8) {
3422 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr);
3423 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr);
3424 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
3425 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
3426 }
3427
3428 if (platform->supported_cstates & PC9) {
3429 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr);
3430 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr);
3431 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
3432 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
3433 }
3434
3435 if (platform->supported_cstates & PC10) {
3436 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr);
3437 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr);
3438 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
3439 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
3440 }
3441 }
3442
3443 void free_fd_percpu(void)
3444 {
3445 int i;
3446
3447 for (i = 0; i < topo.max_cpu_num + 1; ++i) {
3448 if (fd_percpu[i] != 0)
3449 close(fd_percpu[i]);
3450 }
3451
3452 free(fd_percpu);
3453 }
3454
3455 void free_all_buffers(void)
3456 {
3457 int i;
3458
3459 CPU_FREE(cpu_present_set);
3460 cpu_present_set = NULL;
3461 cpu_present_setsize = 0;
3462
3463 CPU_FREE(cpu_effective_set);
3464 cpu_effective_set = NULL;
3465 cpu_effective_setsize = 0;
3466
3467 CPU_FREE(cpu_allowed_set);
3468 cpu_allowed_set = NULL;
3469 cpu_allowed_setsize = 0;
3470
3471 CPU_FREE(cpu_affinity_set);
3472 cpu_affinity_set = NULL;
3473 cpu_affinity_setsize = 0;
3474
3475 free(thread_even);
3476 free(core_even);
3477 free(package_even);
3478
3479 thread_even = NULL;
3480 core_even = NULL;
3481 package_even = NULL;
3482
3483 free(thread_odd);
3484 free(core_odd);
3485 free(package_odd);
3486
3487 thread_odd = NULL;
3488 core_odd = NULL;
3489 package_odd = NULL;
3490
3491 free(output_buffer);
3492 output_buffer = NULL;
3493 outp = NULL;
3494
3495 free_fd_percpu();
3496
3497 free(irq_column_2_cpu);
3498 free(irqs_per_cpu);
3499
3500 for (i = 0; i <= topo.max_cpu_num; ++i) {
3501 if (cpus[i].put_ids)
3502 CPU_FREE(cpus[i].put_ids);
3503 }
3504 free(cpus);
3505 }
3506
3507 /*
3508 * Parse a file containing a single int.
3509 * Return 0 if file can not be opened
3510 * Exit if file can be opened, but can not be parsed
3511 */
3512 int parse_int_file(const char *fmt, ...)
3513 {
3514 va_list args;
3515 char path[PATH_MAX];
3516 FILE *filep;
3517 int value;
3518
3519 va_start(args, fmt);
3520 vsnprintf(path, sizeof(path), fmt, args);
3521 va_end(args);
3522 filep = fopen(path, "r");
3523 if (!filep)
3524 return 0;
3525 if (fscanf(filep, "%d", &value) != 1)
3526 err(1, "%s: failed to parse number from file", path);
3527 fclose(filep);
3528 return value;
3529 }
3530
3531 /*
3532 * cpu_is_first_core_in_package(cpu)
3533 * return 1 if given CPU is 1st core in package
3534 */
3535 int cpu_is_first_core_in_package(int cpu)
3536 {
3537 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu);
3538 }
3539
3540 int get_physical_package_id(int cpu)
3541 {
3542 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu);
3543 }
3544
3545 int get_die_id(int cpu)
3546 {
3547 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/die_id", cpu);
3548 }
3549
3550 int get_core_id(int cpu)
3551 {
3552 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu);
3553 }
3554
3555 void set_node_data(void)
3556 {
3557 int pkg, node, lnode, cpu, cpux;
3558 int cpu_count;
3559
3560 /* initialize logical_node_id */
3561 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu)
3562 cpus[cpu].logical_node_id = -1;
3563
3564 cpu_count = 0;
3565 for (pkg = 0; pkg < topo.num_packages; pkg++) {
3566 lnode = 0;
3567 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) {
3568 if (cpus[cpu].physical_package_id != pkg)
3569 continue;
3570 /* find a cpu with an unset logical_node_id */
3571 if (cpus[cpu].logical_node_id != -1)
3572 continue;
3573 cpus[cpu].logical_node_id = lnode;
3574 node = cpus[cpu].physical_node_id;
3575 cpu_count++;
3576 /*
3577 * find all matching cpus on this pkg and set
3578 * the logical_node_id
3579 */
3580 for (cpux = cpu; cpux <= topo.max_cpu_num; cpux++) {
3581 if ((cpus[cpux].physical_package_id == pkg) && (cpus[cpux].physical_node_id == node)) {
3582 cpus[cpux].logical_node_id = lnode;
3583 cpu_count++;
3584 }
3585 }
3586 lnode++;
3587 if (lnode > topo.nodes_per_pkg)
3588 topo.nodes_per_pkg = lnode;
3589 }
3590 if (cpu_count >= topo.max_cpu_num)
3591 break;
3592 }
3593 }
3594
3595 int get_physical_node_id(struct cpu_topology *thiscpu)
3596 {
3597 char path[80];
3598 FILE *filep;
3599 int i;
3600 int cpu = thiscpu->logical_cpu_id;
3601
3602 for (i = 0; i <= topo.max_cpu_num; i++) {
3603 sprintf(path, "/sys/devices/system/cpu/cpu%d/node%i/cpulist", cpu, i);
3604 filep = fopen(path, "r");
3605 if (!filep)
3606 continue;
3607 fclose(filep);
3608 return i;
3609 }
3610 return -1;
3611 }
3612
3613 static int parse_cpu_str(char *cpu_str, cpu_set_t *cpu_set, int cpu_set_size)
3614 {
3615 unsigned int start, end;
3616 char *next = cpu_str;
3617
3618 while (next && *next) {
3619
3620 if (*next == '-') /* no negative cpu numbers */
3621 return 1;
3622
3623 start = strtoul(next, &next, 10);
3624
3625 if (start >= CPU_SUBSET_MAXCPUS)
3626 return 1;
3627 CPU_SET_S(start, cpu_set_size, cpu_set);
3628
3629 if (*next == '\0' || *next == '\n')
3630 break;
3631
3632 if (*next == ',') {
3633 next += 1;
3634 continue;
3635 }
3636
3637 if (*next == '-') {
3638 next += 1; /* start range */
3639 } else if (*next == '.') {
3640 next += 1;
3641 if (*next == '.')
3642 next += 1; /* start range */
3643 else
3644 return 1;
3645 }
3646
3647 end = strtoul(next, &next, 10);
3648 if (end <= start)
3649 return 1;
3650
3651 while (++start <= end) {
3652 if (start >= CPU_SUBSET_MAXCPUS)
3653 return 1;
3654 CPU_SET_S(start, cpu_set_size, cpu_set);
3655 }
3656
3657 if (*next == ',')
3658 next += 1;
3659 else if (*next != '\0' && *next != '\n')
3660 return 1;
3661 }
3662
3663 return 0;
3664 }
3665
3666 int get_thread_siblings(struct cpu_topology *thiscpu)
3667 {
3668 char path[80], character;
3669 FILE *filep;
3670 unsigned long map;
3671 int so, shift, sib_core;
3672 int cpu = thiscpu->logical_cpu_id;
3673 int offset = topo.max_cpu_num + 1;
3674 size_t size;
3675 int thread_id = 0;
3676
3677 thiscpu->put_ids = CPU_ALLOC((topo.max_cpu_num + 1));
3678 if (thiscpu->thread_id < 0)
3679 thiscpu->thread_id = thread_id++;
3680 if (!thiscpu->put_ids)
3681 return -1;
3682
3683 size = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
3684 CPU_ZERO_S(size, thiscpu->put_ids);
3685
3686 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", cpu);
3687 filep = fopen(path, "r");
3688
3689 if (!filep) {
3690 warnx("%s: open failed", path);
3691 return -1;
3692 }
3693 do {
3694 offset -= BITMASK_SIZE;
3695 if (fscanf(filep, "%lx%c", &map, &character) != 2)
3696 err(1, "%s: failed to parse file", path);
3697 for (shift = 0; shift < BITMASK_SIZE; shift++) {
3698 if ((map >> shift) & 0x1) {
3699 so = shift + offset;
3700 sib_core = get_core_id(so);
3701 if (sib_core == thiscpu->physical_core_id) {
3702 CPU_SET_S(so, size, thiscpu->put_ids);
3703 if ((so != cpu) && (cpus[so].thread_id < 0))
3704 cpus[so].thread_id = thread_id++;
3705 }
3706 }
3707 }
3708 } while (character == ',');
3709 fclose(filep);
3710
3711 return CPU_COUNT_S(size, thiscpu->put_ids);
3712 }
3713
3714 /*
3715 * run func(thread, core, package) in topology order
3716 * skip non-present cpus
3717 */
3718
3719 int for_all_cpus_2(int (func) (struct thread_data *, struct core_data *,
3720 struct pkg_data *, struct thread_data *, struct core_data *,
3721 struct pkg_data *), struct thread_data *thread_base,
3722 struct core_data *core_base, struct pkg_data *pkg_base,
3723 struct thread_data *thread_base2, struct core_data *core_base2, struct pkg_data *pkg_base2)
3724 {
3725 int retval, pkg_no, node_no, core_no, thread_no;
3726
3727 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
3728 for (node_no = 0; node_no < topo.nodes_per_pkg; ++node_no) {
3729 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) {
3730 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) {
3731 struct thread_data *t, *t2;
3732 struct core_data *c, *c2;
3733 struct pkg_data *p, *p2;
3734
3735 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no);
3736
3737 if (cpu_is_not_allowed(t->cpu_id))
3738 continue;
3739
3740 t2 = GET_THREAD(thread_base2, thread_no, core_no, node_no, pkg_no);
3741
3742 c = GET_CORE(core_base, core_no, node_no, pkg_no);
3743 c2 = GET_CORE(core_base2, core_no, node_no, pkg_no);
3744
3745 p = GET_PKG(pkg_base, pkg_no);
3746 p2 = GET_PKG(pkg_base2, pkg_no);
3747
3748 retval = func(t, c, p, t2, c2, p2);
3749 if (retval)
3750 return retval;
3751 }
3752 }
3753 }
3754 }
3755 return 0;
3756 }
3757
3758 /*
3759 * run func(cpu) on every cpu in /proc/stat
3760 * return max_cpu number
3761 */
3762 int for_all_proc_cpus(int (func) (int))
3763 {
3764 FILE *fp;
3765 int cpu_num;
3766 int retval;
3767
3768 fp = fopen_or_die(proc_stat, "r");
3769
3770 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n");
3771 if (retval != 0)
3772 err(1, "%s: failed to parse format", proc_stat);
3773
3774 while (1) {
3775 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num);
3776 if (retval != 1)
3777 break;
3778
3779 retval = func(cpu_num);
3780 if (retval) {
3781 fclose(fp);
3782 return (retval);
3783 }
3784 }
3785 fclose(fp);
3786 return 0;
3787 }
3788
3789 #define PATH_EFFECTIVE_CPUS "/sys/fs/cgroup/cpuset.cpus.effective"
3790
3791 static char cpu_effective_str[1024];
3792
3793 static int update_effective_str(bool startup)
3794 {
3795 FILE *fp;
3796 char *pos;
3797 char buf[1024];
3798 int ret;
3799
3800 if (cpu_effective_str[0] == '\0' && !startup)
3801 return 0;
3802
3803 fp = fopen(PATH_EFFECTIVE_CPUS, "r");
3804 if (!fp)
3805 return 0;
3806
3807 pos = fgets(buf, 1024, fp);
3808 if (!pos)
3809 err(1, "%s: file read failed\n", PATH_EFFECTIVE_CPUS);
3810
3811 fclose(fp);
3812
3813 ret = strncmp(cpu_effective_str, buf, 1024);
3814 if (!ret)
3815 return 0;
3816
3817 strncpy(cpu_effective_str, buf, 1024);
3818 return 1;
3819 }
3820
3821 static void update_effective_set(bool startup)
3822 {
3823 update_effective_str(startup);
3824
3825 if (parse_cpu_str(cpu_effective_str, cpu_effective_set, cpu_effective_setsize))
3826 err(1, "%s: cpu str malformat %s\n", PATH_EFFECTIVE_CPUS, cpu_effective_str);
3827 }
3828
3829 void re_initialize(void)
3830 {
3831 free_all_buffers();
3832 setup_all_buffers(false);
3833 fprintf(outf, "turbostat: re-initialized with num_cpus %d, allowed_cpus %d\n", topo.num_cpus, topo.allowed_cpus);
3834 }
3835
3836 void set_max_cpu_num(void)
3837 {
3838 FILE *filep;
3839 int base_cpu;
3840 unsigned long dummy;
3841 char pathname[64];
3842
3843 base_cpu = sched_getcpu();
3844 if (base_cpu < 0)
3845 err(1, "cannot find calling cpu ID");
3846 sprintf(pathname, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", base_cpu);
3847
3848 filep = fopen_or_die(pathname, "r");
3849 topo.max_cpu_num = 0;
3850 while (fscanf(filep, "%lx,", &dummy) == 1)
3851 topo.max_cpu_num += BITMASK_SIZE;
3852 fclose(filep);
3853 topo.max_cpu_num--; /* 0 based */
3854 }
3855
3856 /*
3857 * count_cpus()
3858 * remember the last one seen, it will be the max
3859 */
3860 int count_cpus(int cpu)
3861 {
3862 UNUSED(cpu);
3863
3864 topo.num_cpus++;
3865 return 0;
3866 }
3867
3868 int mark_cpu_present(int cpu)
3869 {
3870 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set);
3871 return 0;
3872 }
3873
3874 int init_thread_id(int cpu)
3875 {
3876 cpus[cpu].thread_id = -1;
3877 return 0;
3878 }
3879
3880 /*
3881 * snapshot_proc_interrupts()
3882 *
3883 * read and record summary of /proc/interrupts
3884 *
3885 * return 1 if config change requires a restart, else return 0
3886 */
3887 int snapshot_proc_interrupts(void)
3888 {
3889 static FILE *fp;
3890 int column, retval;
3891
3892 if (fp == NULL)
3893 fp = fopen_or_die("/proc/interrupts", "r");
3894 else
3895 rewind(fp);
3896
3897 /* read 1st line of /proc/interrupts to get cpu* name for each column */
3898 for (column = 0; column < topo.num_cpus; ++column) {
3899 int cpu_number;
3900
3901 retval = fscanf(fp, " CPU%d", &cpu_number);
3902 if (retval != 1)
3903 break;
3904
3905 if (cpu_number > topo.max_cpu_num) {
3906 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num);
3907 return 1;
3908 }
3909
3910 irq_column_2_cpu[column] = cpu_number;
3911 irqs_per_cpu[cpu_number] = 0;
3912 }
3913
3914 /* read /proc/interrupt count lines and sum up irqs per cpu */
3915 while (1) {
3916 int column;
3917 char buf[64];
3918
3919 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */
3920 if (retval != 1)
3921 break;
3922
3923 /* read the count per cpu */
3924 for (column = 0; column < topo.num_cpus; ++column) {
3925
3926 int cpu_number, irq_count;
3927
3928 retval = fscanf(fp, " %d", &irq_count);
3929 if (retval != 1)
3930 break;
3931
3932 cpu_number = irq_column_2_cpu[column];
3933 irqs_per_cpu[cpu_number] += irq_count;
3934
3935 }
3936
3937 while (getc(fp) != '\n') ; /* flush interrupt description */
3938
3939 }
3940 return 0;
3941 }
3942
3943 /*
3944 * snapshot_gfx_rc6_ms()
3945 *
3946 * record snapshot of
3947 * /sys/class/drm/card0/power/rc6_residency_ms
3948 *
3949 * return 1 if config change requires a restart, else return 0
3950 */
3951 int snapshot_gfx_rc6_ms(void)
3952 {
3953 FILE *fp;
3954 int retval;
3955
3956 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r");
3957
3958 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms);
3959 if (retval != 1)
3960 err(1, "GFX rc6");
3961
3962 fclose(fp);
3963
3964 return 0;
3965 }
3966
3967 /*
3968 * snapshot_gfx_mhz()
3969 *
3970 * fall back to /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz
3971 * when /sys/class/drm/card0/gt_cur_freq_mhz is not available.
3972 *
3973 * return 1 if config change requires a restart, else return 0
3974 */
3975 int snapshot_gfx_mhz(void)
3976 {
3977 static FILE *fp;
3978 int retval;
3979
3980 if (fp == NULL) {
3981 fp = fopen("/sys/class/drm/card0/gt_cur_freq_mhz", "r");
3982 if (!fp)
3983 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r");
3984 } else {
3985 rewind(fp);
3986 fflush(fp);
3987 }
3988
3989 retval = fscanf(fp, "%d", &gfx_cur_mhz);
3990 if (retval != 1)
3991 err(1, "GFX MHz");
3992
3993 return 0;
3994 }
3995
3996 /*
3997 * snapshot_gfx_cur_mhz()
3998 *
3999 * fall back to /sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz
4000 * when /sys/class/drm/card0/gt_act_freq_mhz is not available.
4001 *
4002 * return 1 if config change requires a restart, else return 0
4003 */
4004 int snapshot_gfx_act_mhz(void)
4005 {
4006 static FILE *fp;
4007 int retval;
4008
4009 if (fp == NULL) {
4010 fp = fopen("/sys/class/drm/card0/gt_act_freq_mhz", "r");
4011 if (!fp)
4012 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", "r");
4013 } else {
4014 rewind(fp);
4015 fflush(fp);
4016 }
4017
4018 retval = fscanf(fp, "%d", &gfx_act_mhz);
4019 if (retval != 1)
4020 err(1, "GFX ACT MHz");
4021
4022 return 0;
4023 }
4024
4025 /*
4026 * snapshot_cpu_lpi()
4027 *
4028 * record snapshot of
4029 * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us
4030 */
4031 int snapshot_cpu_lpi_us(void)
4032 {
4033 FILE *fp;
4034 int retval;
4035
4036 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", "r");
4037
4038 retval = fscanf(fp, "%lld", &cpuidle_cur_cpu_lpi_us);
4039 if (retval != 1) {
4040 fprintf(stderr, "Disabling Low Power Idle CPU output\n");
4041 BIC_NOT_PRESENT(BIC_CPU_LPI);
4042 fclose(fp);
4043 return -1;
4044 }
4045
4046 fclose(fp);
4047
4048 return 0;
4049 }
4050
4051 /*
4052 * snapshot_sys_lpi()
4053 *
4054 * record snapshot of sys_lpi_file
4055 */
4056 int snapshot_sys_lpi_us(void)
4057 {
4058 FILE *fp;
4059 int retval;
4060
4061 fp = fopen_or_die(sys_lpi_file, "r");
4062
4063 retval = fscanf(fp, "%lld", &cpuidle_cur_sys_lpi_us);
4064 if (retval != 1) {
4065 fprintf(stderr, "Disabling Low Power Idle System output\n");
4066 BIC_NOT_PRESENT(BIC_SYS_LPI);
4067 fclose(fp);
4068 return -1;
4069 }
4070 fclose(fp);
4071
4072 return 0;
4073 }
4074
4075 /*
4076 * snapshot /proc and /sys files
4077 *
4078 * return 1 if configuration restart needed, else return 0
4079 */
4080 int snapshot_proc_sysfs_files(void)
4081 {
4082 if (DO_BIC(BIC_IRQ))
4083 if (snapshot_proc_interrupts())
4084 return 1;
4085
4086 if (DO_BIC(BIC_GFX_rc6))
4087 snapshot_gfx_rc6_ms();
4088
4089 if (DO_BIC(BIC_GFXMHz))
4090 snapshot_gfx_mhz();
4091
4092 if (DO_BIC(BIC_GFXACTMHz))
4093 snapshot_gfx_act_mhz();
4094
4095 if (DO_BIC(BIC_CPU_LPI))
4096 snapshot_cpu_lpi_us();
4097
4098 if (DO_BIC(BIC_SYS_LPI))
4099 snapshot_sys_lpi_us();
4100
4101 return 0;
4102 }
4103
4104 int exit_requested;
4105
4106 static void signal_handler(int signal)
4107 {
4108 switch (signal) {
4109 case SIGINT:
4110 exit_requested = 1;
4111 if (debug)
4112 fprintf(stderr, " SIGINT\n");
4113 break;
4114 case SIGUSR1:
4115 if (debug > 1)
4116 fprintf(stderr, "SIGUSR1\n");
4117 break;
4118 }
4119 }
4120
4121 void setup_signal_handler(void)
4122 {
4123 struct sigaction sa;
4124
4125 memset(&sa, 0, sizeof(sa));
4126
4127 sa.sa_handler = &signal_handler;
4128
4129 if (sigaction(SIGINT, &sa, NULL) < 0)
4130 err(1, "sigaction SIGINT");
4131 if (sigaction(SIGUSR1, &sa, NULL) < 0)
4132 err(1, "sigaction SIGUSR1");
4133 }
4134
4135 void do_sleep(void)
4136 {
4137 struct timeval tout;
4138 struct timespec rest;
4139 fd_set readfds;
4140 int retval;
4141
4142 FD_ZERO(&readfds);
4143 FD_SET(0, &readfds);
4144
4145 if (ignore_stdin) {
4146 nanosleep(&interval_ts, NULL);
4147 return;
4148 }
4149
4150 tout = interval_tv;
4151 retval = select(1, &readfds, NULL, NULL, &tout);
4152
4153 if (retval == 1) {
4154 switch (getc(stdin)) {
4155 case 'q':
4156 exit_requested = 1;
4157 break;
4158 case EOF:
4159 /*
4160 * 'stdin' is a pipe closed on the other end. There
4161 * won't be any further input.
4162 */
4163 ignore_stdin = 1;
4164 /* Sleep the rest of the time */
4165 rest.tv_sec = (tout.tv_sec + tout.tv_usec / 1000000);
4166 rest.tv_nsec = (tout.tv_usec % 1000000) * 1000;
4167 nanosleep(&rest, NULL);
4168 }
4169 }
4170 }
4171
4172 int get_msr_sum(int cpu, off_t offset, unsigned long long *msr)
4173 {
4174 int ret, idx;
4175 unsigned long long msr_cur, msr_last;
4176
4177 if (!per_cpu_msr_sum)
4178 return 1;
4179
4180 idx = offset_to_idx(offset);
4181 if (idx < 0)
4182 return idx;
4183 /* get_msr_sum() = sum + (get_msr() - last) */
4184 ret = get_msr(cpu, offset, &msr_cur);
4185 if (ret)
4186 return ret;
4187 msr_last = per_cpu_msr_sum[cpu].entries[idx].last;
4188 DELTA_WRAP32(msr_cur, msr_last);
4189 *msr = msr_last + per_cpu_msr_sum[cpu].entries[idx].sum;
4190
4191 return 0;
4192 }
4193
4194 timer_t timerid;
4195
4196 /* Timer callback, update the sum of MSRs periodically. */
4197 static int update_msr_sum(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4198 {
4199 int i, ret;
4200 int cpu = t->cpu_id;
4201
4202 UNUSED(c);
4203 UNUSED(p);
4204
4205 for (i = IDX_PKG_ENERGY; i < IDX_COUNT; i++) {
4206 unsigned long long msr_cur, msr_last;
4207 off_t offset;
4208
4209 if (!idx_valid(i))
4210 continue;
4211 offset = idx_to_offset(i);
4212 if (offset < 0)
4213 continue;
4214 ret = get_msr(cpu, offset, &msr_cur);
4215 if (ret) {
4216 fprintf(outf, "Can not update msr(0x%llx)\n", (unsigned long long)offset);
4217 continue;
4218 }
4219
4220 msr_last = per_cpu_msr_sum[cpu].entries[i].last;
4221 per_cpu_msr_sum[cpu].entries[i].last = msr_cur & 0xffffffff;
4222
4223 DELTA_WRAP32(msr_cur, msr_last);
4224 per_cpu_msr_sum[cpu].entries[i].sum += msr_last;
4225 }
4226 return 0;
4227 }
4228
4229 static void msr_record_handler(union sigval v)
4230 {
4231 UNUSED(v);
4232
4233 for_all_cpus(update_msr_sum, EVEN_COUNTERS);
4234 }
4235
4236 void msr_sum_record(void)
4237 {
4238 struct itimerspec its;
4239 struct sigevent sev;
4240
4241 per_cpu_msr_sum = calloc(topo.max_cpu_num + 1, sizeof(struct msr_sum_array));
4242 if (!per_cpu_msr_sum) {
4243 fprintf(outf, "Can not allocate memory for long time MSR.\n");
4244 return;
4245 }
4246 /*
4247 * Signal handler might be restricted, so use thread notifier instead.
4248 */
4249 memset(&sev, 0, sizeof(struct sigevent));
4250 sev.sigev_notify = SIGEV_THREAD;
4251 sev.sigev_notify_function = msr_record_handler;
4252
4253 sev.sigev_value.sival_ptr = &timerid;
4254 if (timer_create(CLOCK_REALTIME, &sev, &timerid) == -1) {
4255 fprintf(outf, "Can not create timer.\n");
4256 goto release_msr;
4257 }
4258
4259 its.it_value.tv_sec = 0;
4260 its.it_value.tv_nsec = 1;
4261 /*
4262 * A wraparound time has been calculated early.
4263 * Some sources state that the peak power for a
4264 * microprocessor is usually 1.5 times the TDP rating,
4265 * use 2 * TDP for safety.
4266 */
4267 its.it_interval.tv_sec = rapl_joule_counter_range / 2;
4268 its.it_interval.tv_nsec = 0;
4269
4270 if (timer_settime(timerid, 0, &its, NULL) == -1) {
4271 fprintf(outf, "Can not set timer.\n");
4272 goto release_timer;
4273 }
4274 return;
4275
4276 release_timer:
4277 timer_delete(timerid);
4278 release_msr:
4279 free(per_cpu_msr_sum);
4280 }
4281
4282 /*
4283 * set_my_sched_priority(pri)
4284 * return previous
4285 */
4286 int set_my_sched_priority(int priority)
4287 {
4288 int retval;
4289 int original_priority;
4290
4291 errno = 0;
4292 original_priority = getpriority(PRIO_PROCESS, 0);
4293 if (errno && (original_priority == -1))
4294 err(errno, "getpriority");
4295
4296 retval = setpriority(PRIO_PROCESS, 0, priority);
4297 if (retval)
4298 errx(retval, "capget(CAP_SYS_NICE) failed,try \"# setcap cap_sys_nice=ep %s\"", progname);
4299
4300 errno = 0;
4301 retval = getpriority(PRIO_PROCESS, 0);
4302 if (retval != priority)
4303 err(retval, "getpriority(%d) != setpriority(%d)", retval, priority);
4304
4305 return original_priority;
4306 }
4307
4308 void turbostat_loop()
4309 {
4310 int retval;
4311 int restarted = 0;
4312 unsigned int done_iters = 0;
4313
4314 setup_signal_handler();
4315
4316 /*
4317 * elevate own priority for interval mode
4318 */
4319 set_my_sched_priority(-20);
4320
4321 restart:
4322 restarted++;
4323
4324 snapshot_proc_sysfs_files();
4325 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
4326 first_counter_read = 0;
4327 if (retval < -1) {
4328 exit(retval);
4329 } else if (retval == -1) {
4330 if (restarted > 10) {
4331 exit(retval);
4332 }
4333 re_initialize();
4334 goto restart;
4335 }
4336 restarted = 0;
4337 done_iters = 0;
4338 gettimeofday(&tv_even, (struct timezone *)NULL);
4339
4340 while (1) {
4341 if (for_all_proc_cpus(cpu_is_not_present)) {
4342 re_initialize();
4343 goto restart;
4344 }
4345 if (update_effective_str(false)) {
4346 re_initialize();
4347 goto restart;
4348 }
4349 do_sleep();
4350 if (snapshot_proc_sysfs_files())
4351 goto restart;
4352 retval = for_all_cpus(get_counters, ODD_COUNTERS);
4353 if (retval < -1) {
4354 exit(retval);
4355 } else if (retval == -1) {
4356 re_initialize();
4357 goto restart;
4358 }
4359 gettimeofday(&tv_odd, (struct timezone *)NULL);
4360 timersub(&tv_odd, &tv_even, &tv_delta);
4361 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) {
4362 re_initialize();
4363 goto restart;
4364 }
4365 compute_average(EVEN_COUNTERS);
4366 format_all_counters(EVEN_COUNTERS);
4367 flush_output_stdout();
4368 if (exit_requested)
4369 break;
4370 if (num_iterations && ++done_iters >= num_iterations)
4371 break;
4372 do_sleep();
4373 if (snapshot_proc_sysfs_files())
4374 goto restart;
4375 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
4376 if (retval < -1) {
4377 exit(retval);
4378 } else if (retval == -1) {
4379 re_initialize();
4380 goto restart;
4381 }
4382 gettimeofday(&tv_even, (struct timezone *)NULL);
4383 timersub(&tv_even, &tv_odd, &tv_delta);
4384 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) {
4385 re_initialize();
4386 goto restart;
4387 }
4388 compute_average(ODD_COUNTERS);
4389 format_all_counters(ODD_COUNTERS);
4390 flush_output_stdout();
4391 if (exit_requested)
4392 break;
4393 if (num_iterations && ++done_iters >= num_iterations)
4394 break;
4395 }
4396 }
4397
4398 void check_dev_msr()
4399 {
4400 struct stat sb;
4401 char pathname[32];
4402
4403 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
4404 if (stat(pathname, &sb))
4405 if (system("/sbin/modprobe msr > /dev/null 2>&1"))
4406 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" ");
4407 }
4408
4409 /*
4410 * check for CAP_SYS_RAWIO
4411 * return 0 on success
4412 * return 1 on fail
4413 */
4414 int check_for_cap_sys_rawio(void)
4415 {
4416 cap_t caps;
4417 cap_flag_value_t cap_flag_value;
4418
4419 caps = cap_get_proc();
4420 if (caps == NULL)
4421 err(-6, "cap_get_proc\n");
4422
4423 if (cap_get_flag(caps, CAP_SYS_RAWIO, CAP_EFFECTIVE, &cap_flag_value))
4424 err(-6, "cap_get\n");
4425
4426 if (cap_flag_value != CAP_SET) {
4427 warnx("capget(CAP_SYS_RAWIO) failed," " try \"# setcap cap_sys_rawio=ep %s\"", progname);
4428 return 1;
4429 }
4430
4431 if (cap_free(caps) == -1)
4432 err(-6, "cap_free\n");
4433
4434 return 0;
4435 }
4436
4437 void check_permissions(void)
4438 {
4439 int do_exit = 0;
4440 char pathname[32];
4441
4442 /* check for CAP_SYS_RAWIO */
4443 do_exit += check_for_cap_sys_rawio();
4444
4445 /* test file permissions */
4446 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
4447 if (euidaccess(pathname, R_OK)) {
4448 do_exit++;
4449 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr");
4450 }
4451
4452 /* if all else fails, thell them to be root */
4453 if (do_exit)
4454 if (getuid() != 0)
4455 warnx("... or simply run as root");
4456
4457 if (do_exit)
4458 exit(-6);
4459 }
4460
4461 void probe_bclk(void)
4462 {
4463 unsigned long long msr;
4464 unsigned int base_ratio;
4465
4466 if (!platform->has_nhm_msrs)
4467 return;
4468
4469 if (platform->bclk_freq == BCLK_100MHZ)
4470 bclk = 100.00;
4471 else if (platform->bclk_freq == BCLK_133MHZ)
4472 bclk = 133.33;
4473 else if (platform->bclk_freq == BCLK_SLV)
4474 bclk = slm_bclk();
4475 else
4476 return;
4477
4478 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
4479 base_ratio = (msr >> 8) & 0xFF;
4480
4481 base_hz = base_ratio * bclk * 1000000;
4482 has_base_hz = 1;
4483
4484 if (platform->enable_tsc_tweak)
4485 tsc_tweak = base_hz / tsc_hz;
4486 }
4487
4488 static void remove_underbar(char *s)
4489 {
4490 char *to = s;
4491
4492 while (*s) {
4493 if (*s != '_')
4494 *to++ = *s;
4495 s++;
4496 }
4497
4498 *to = 0;
4499 }
4500
4501 static void dump_turbo_ratio_info(void)
4502 {
4503 if (!has_turbo)
4504 return;
4505
4506 if (!platform->has_nhm_msrs)
4507 return;
4508
4509 if (platform->trl_msrs & TRL_LIMIT2)
4510 dump_turbo_ratio_limit2();
4511
4512 if (platform->trl_msrs & TRL_LIMIT1)
4513 dump_turbo_ratio_limit1();
4514
4515 if (platform->trl_msrs & TRL_BASE) {
4516 dump_turbo_ratio_limits(MSR_TURBO_RATIO_LIMIT);
4517
4518 if (is_hybrid)
4519 dump_turbo_ratio_limits(MSR_SECONDARY_TURBO_RATIO_LIMIT);
4520 }
4521
4522 if (platform->trl_msrs & TRL_ATOM)
4523 dump_atom_turbo_ratio_limits();
4524
4525 if (platform->trl_msrs & TRL_KNL)
4526 dump_knl_turbo_ratio_limits();
4527
4528 if (platform->has_config_tdp)
4529 dump_config_tdp();
4530 }
4531
4532 static int read_sysfs_int(char *path)
4533 {
4534 FILE *input;
4535 int retval = -1;
4536
4537 input = fopen(path, "r");
4538 if (input == NULL) {
4539 if (debug)
4540 fprintf(outf, "NSFOD %s\n", path);
4541 return (-1);
4542 }
4543 if (fscanf(input, "%d", &retval) != 1)
4544 err(1, "%s: failed to read int from file", path);
4545 fclose(input);
4546
4547 return (retval);
4548 }
4549
4550 static void dump_sysfs_file(char *path)
4551 {
4552 FILE *input;
4553 char cpuidle_buf[64];
4554
4555 input = fopen(path, "r");
4556 if (input == NULL) {
4557 if (debug)
4558 fprintf(outf, "NSFOD %s\n", path);
4559 return;
4560 }
4561 if (!fgets(cpuidle_buf, sizeof(cpuidle_buf), input))
4562 err(1, "%s: failed to read file", path);
4563 fclose(input);
4564
4565 fprintf(outf, "%s: %s", strrchr(path, '/') + 1, cpuidle_buf);
4566 }
4567
4568 static void probe_intel_uncore_frequency(void)
4569 {
4570 int i, j;
4571 char path[128];
4572
4573 if (!genuine_intel)
4574 return;
4575
4576 if (access("/sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00", R_OK))
4577 return;
4578
4579 /* Cluster level sysfs not supported yet. */
4580 if (!access("/sys/devices/system/cpu/intel_uncore_frequency/uncore00", R_OK))
4581 return;
4582
4583 if (!access("/sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00/current_freq_khz", R_OK))
4584 BIC_PRESENT(BIC_UNCORE_MHZ);
4585
4586 if (quiet)
4587 return;
4588
4589 for (i = 0; i < topo.num_packages; ++i) {
4590 for (j = 0; j < topo.num_die; ++j) {
4591 int k, l;
4592
4593 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/min_freq_khz",
4594 i, j);
4595 k = read_sysfs_int(path);
4596 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/max_freq_khz",
4597 i, j);
4598 l = read_sysfs_int(path);
4599 fprintf(outf, "Uncore Frequency pkg%d die%d: %d - %d MHz ", i, j, k / 1000, l / 1000);
4600
4601 sprintf(path,
4602 "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/initial_min_freq_khz",
4603 i, j);
4604 k = read_sysfs_int(path);
4605 sprintf(path,
4606 "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/initial_max_freq_khz",
4607 i, j);
4608 l = read_sysfs_int(path);
4609 fprintf(outf, "(%d - %d MHz)\n", k / 1000, l / 1000);
4610 }
4611 }
4612 }
4613
4614 static void probe_graphics(void)
4615 {
4616 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK))
4617 BIC_PRESENT(BIC_GFX_rc6);
4618
4619 if (!access("/sys/class/drm/card0/gt_cur_freq_mhz", R_OK) ||
4620 !access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK))
4621 BIC_PRESENT(BIC_GFXMHz);
4622
4623 if (!access("/sys/class/drm/card0/gt_act_freq_mhz", R_OK) ||
4624 !access("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", R_OK))
4625 BIC_PRESENT(BIC_GFXACTMHz);
4626 }
4627
4628 static void dump_sysfs_cstate_config(void)
4629 {
4630 char path[64];
4631 char name_buf[16];
4632 char desc[64];
4633 FILE *input;
4634 int state;
4635 char *sp;
4636
4637 if (access("/sys/devices/system/cpu/cpuidle", R_OK)) {
4638 fprintf(outf, "cpuidle not loaded\n");
4639 return;
4640 }
4641
4642 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_driver");
4643 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor");
4644 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor_ro");
4645
4646 for (state = 0; state < 10; ++state) {
4647
4648 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state);
4649 input = fopen(path, "r");
4650 if (input == NULL)
4651 continue;
4652 if (!fgets(name_buf, sizeof(name_buf), input))
4653 err(1, "%s: failed to read file", path);
4654
4655 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
4656 sp = strchr(name_buf, '-');
4657 if (!sp)
4658 sp = strchrnul(name_buf, '\n');
4659 *sp = '\0';
4660 fclose(input);
4661
4662 remove_underbar(name_buf);
4663
4664 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc", base_cpu, state);
4665 input = fopen(path, "r");
4666 if (input == NULL)
4667 continue;
4668 if (!fgets(desc, sizeof(desc), input))
4669 err(1, "%s: failed to read file", path);
4670
4671 fprintf(outf, "cpu%d: %s: %s", base_cpu, name_buf, desc);
4672 fclose(input);
4673 }
4674 }
4675
4676 static void dump_sysfs_pstate_config(void)
4677 {
4678 char path[64];
4679 char driver_buf[64];
4680 char governor_buf[64];
4681 FILE *input;
4682 int turbo;
4683
4684 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver", base_cpu);
4685 input = fopen(path, "r");
4686 if (input == NULL) {
4687 fprintf(outf, "NSFOD %s\n", path);
4688 return;
4689 }
4690 if (!fgets(driver_buf, sizeof(driver_buf), input))
4691 err(1, "%s: failed to read file", path);
4692 fclose(input);
4693
4694 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor", base_cpu);
4695 input = fopen(path, "r");
4696 if (input == NULL) {
4697 fprintf(outf, "NSFOD %s\n", path);
4698 return;
4699 }
4700 if (!fgets(governor_buf, sizeof(governor_buf), input))
4701 err(1, "%s: failed to read file", path);
4702 fclose(input);
4703
4704 fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf);
4705 fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf);
4706
4707 sprintf(path, "/sys/devices/system/cpu/cpufreq/boost");
4708 input = fopen(path, "r");
4709 if (input != NULL) {
4710 if (fscanf(input, "%d", &turbo) != 1)
4711 err(1, "%s: failed to parse number from file", path);
4712 fprintf(outf, "cpufreq boost: %d\n", turbo);
4713 fclose(input);
4714 }
4715
4716 sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo");
4717 input = fopen(path, "r");
4718 if (input != NULL) {
4719 if (fscanf(input, "%d", &turbo) != 1)
4720 err(1, "%s: failed to parse number from file", path);
4721 fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo);
4722 fclose(input);
4723 }
4724 }
4725
4726 /*
4727 * print_epb()
4728 * Decode the ENERGY_PERF_BIAS MSR
4729 */
4730 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4731 {
4732 char *epb_string;
4733 int cpu, epb;
4734
4735 UNUSED(c);
4736 UNUSED(p);
4737
4738 if (!has_epb)
4739 return 0;
4740
4741 cpu = t->cpu_id;
4742
4743 /* EPB is per-package */
4744 if (!is_cpu_first_thread_in_package(t, c, p))
4745 return 0;
4746
4747 if (cpu_migrate(cpu)) {
4748 fprintf(outf, "print_epb: Could not migrate to CPU %d\n", cpu);
4749 return -1;
4750 }
4751
4752 epb = get_epb(cpu);
4753 if (epb < 0)
4754 return 0;
4755
4756 switch (epb) {
4757 case ENERGY_PERF_BIAS_PERFORMANCE:
4758 epb_string = "performance";
4759 break;
4760 case ENERGY_PERF_BIAS_NORMAL:
4761 epb_string = "balanced";
4762 break;
4763 case ENERGY_PERF_BIAS_POWERSAVE:
4764 epb_string = "powersave";
4765 break;
4766 default:
4767 epb_string = "custom";
4768 break;
4769 }
4770 fprintf(outf, "cpu%d: EPB: %d (%s)\n", cpu, epb, epb_string);
4771
4772 return 0;
4773 }
4774
4775 /*
4776 * print_hwp()
4777 * Decode the MSR_HWP_CAPABILITIES
4778 */
4779 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4780 {
4781 unsigned long long msr;
4782 int cpu;
4783
4784 UNUSED(c);
4785 UNUSED(p);
4786
4787 if (!has_hwp)
4788 return 0;
4789
4790 cpu = t->cpu_id;
4791
4792 /* MSR_HWP_CAPABILITIES is per-package */
4793 if (!is_cpu_first_thread_in_package(t, c, p))
4794 return 0;
4795
4796 if (cpu_migrate(cpu)) {
4797 fprintf(outf, "print_hwp: Could not migrate to CPU %d\n", cpu);
4798 return -1;
4799 }
4800
4801 if (get_msr(cpu, MSR_PM_ENABLE, &msr))
4802 return 0;
4803
4804 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", cpu, msr, (msr & (1 << 0)) ? "" : "No-");
4805
4806 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */
4807 if ((msr & (1 << 0)) == 0)
4808 return 0;
4809
4810 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr))
4811 return 0;
4812
4813 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx "
4814 "(high %d guar %d eff %d low %d)\n",
4815 cpu, msr,
4816 (unsigned int)HWP_HIGHEST_PERF(msr),
4817 (unsigned int)HWP_GUARANTEED_PERF(msr),
4818 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), (unsigned int)HWP_LOWEST_PERF(msr));
4819
4820 if (get_msr(cpu, MSR_HWP_REQUEST, &msr))
4821 return 0;
4822
4823 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx "
4824 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n",
4825 cpu, msr,
4826 (unsigned int)(((msr) >> 0) & 0xff),
4827 (unsigned int)(((msr) >> 8) & 0xff),
4828 (unsigned int)(((msr) >> 16) & 0xff),
4829 (unsigned int)(((msr) >> 24) & 0xff),
4830 (unsigned int)(((msr) >> 32) & 0xff3), (unsigned int)(((msr) >> 42) & 0x1));
4831
4832 if (has_hwp_pkg) {
4833 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr))
4834 return 0;
4835
4836 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx "
4837 "(min %d max %d des %d epp 0x%x window 0x%x)\n",
4838 cpu, msr,
4839 (unsigned int)(((msr) >> 0) & 0xff),
4840 (unsigned int)(((msr) >> 8) & 0xff),
4841 (unsigned int)(((msr) >> 16) & 0xff),
4842 (unsigned int)(((msr) >> 24) & 0xff), (unsigned int)(((msr) >> 32) & 0xff3));
4843 }
4844 if (has_hwp_notify) {
4845 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr))
4846 return 0;
4847
4848 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx "
4849 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n",
4850 cpu, msr, ((msr) & 0x1) ? "EN" : "Dis", ((msr) & 0x2) ? "EN" : "Dis");
4851 }
4852 if (get_msr(cpu, MSR_HWP_STATUS, &msr))
4853 return 0;
4854
4855 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx "
4856 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n",
4857 cpu, msr, ((msr) & 0x1) ? "" : "No-", ((msr) & 0x4) ? "" : "No-");
4858
4859 return 0;
4860 }
4861
4862 /*
4863 * print_perf_limit()
4864 */
4865 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4866 {
4867 unsigned long long msr;
4868 int cpu;
4869
4870 UNUSED(c);
4871 UNUSED(p);
4872
4873 cpu = t->cpu_id;
4874
4875 /* per-package */
4876 if (!is_cpu_first_thread_in_package(t, c, p))
4877 return 0;
4878
4879 if (cpu_migrate(cpu)) {
4880 fprintf(outf, "print_perf_limit: Could not migrate to CPU %d\n", cpu);
4881 return -1;
4882 }
4883
4884 if (platform->plr_msrs & PLR_CORE) {
4885 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr);
4886 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
4887 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)",
4888 (msr & 1 << 15) ? "bit15, " : "",
4889 (msr & 1 << 14) ? "bit14, " : "",
4890 (msr & 1 << 13) ? "Transitions, " : "",
4891 (msr & 1 << 12) ? "MultiCoreTurbo, " : "",
4892 (msr & 1 << 11) ? "PkgPwrL2, " : "",
4893 (msr & 1 << 10) ? "PkgPwrL1, " : "",
4894 (msr & 1 << 9) ? "CorePwr, " : "",
4895 (msr & 1 << 8) ? "Amps, " : "",
4896 (msr & 1 << 6) ? "VR-Therm, " : "",
4897 (msr & 1 << 5) ? "Auto-HWP, " : "",
4898 (msr & 1 << 4) ? "Graphics, " : "",
4899 (msr & 1 << 2) ? "bit2, " : "",
4900 (msr & 1 << 1) ? "ThermStatus, " : "", (msr & 1 << 0) ? "PROCHOT, " : "");
4901 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
4902 (msr & 1 << 31) ? "bit31, " : "",
4903 (msr & 1 << 30) ? "bit30, " : "",
4904 (msr & 1 << 29) ? "Transitions, " : "",
4905 (msr & 1 << 28) ? "MultiCoreTurbo, " : "",
4906 (msr & 1 << 27) ? "PkgPwrL2, " : "",
4907 (msr & 1 << 26) ? "PkgPwrL1, " : "",
4908 (msr & 1 << 25) ? "CorePwr, " : "",
4909 (msr & 1 << 24) ? "Amps, " : "",
4910 (msr & 1 << 22) ? "VR-Therm, " : "",
4911 (msr & 1 << 21) ? "Auto-HWP, " : "",
4912 (msr & 1 << 20) ? "Graphics, " : "",
4913 (msr & 1 << 18) ? "bit18, " : "",
4914 (msr & 1 << 17) ? "ThermStatus, " : "", (msr & 1 << 16) ? "PROCHOT, " : "");
4915
4916 }
4917 if (platform->plr_msrs & PLR_GFX) {
4918 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr);
4919 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
4920 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)",
4921 (msr & 1 << 0) ? "PROCHOT, " : "",
4922 (msr & 1 << 1) ? "ThermStatus, " : "",
4923 (msr & 1 << 4) ? "Graphics, " : "",
4924 (msr & 1 << 6) ? "VR-Therm, " : "",
4925 (msr & 1 << 8) ? "Amps, " : "",
4926 (msr & 1 << 9) ? "GFXPwr, " : "",
4927 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : "");
4928 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n",
4929 (msr & 1 << 16) ? "PROCHOT, " : "",
4930 (msr & 1 << 17) ? "ThermStatus, " : "",
4931 (msr & 1 << 20) ? "Graphics, " : "",
4932 (msr & 1 << 22) ? "VR-Therm, " : "",
4933 (msr & 1 << 24) ? "Amps, " : "",
4934 (msr & 1 << 25) ? "GFXPwr, " : "",
4935 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : "");
4936 }
4937 if (platform->plr_msrs & PLR_RING) {
4938 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr);
4939 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
4940 fprintf(outf, " (Active: %s%s%s%s%s%s)",
4941 (msr & 1 << 0) ? "PROCHOT, " : "",
4942 (msr & 1 << 1) ? "ThermStatus, " : "",
4943 (msr & 1 << 6) ? "VR-Therm, " : "",
4944 (msr & 1 << 8) ? "Amps, " : "",
4945 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : "");
4946 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n",
4947 (msr & 1 << 16) ? "PROCHOT, " : "",
4948 (msr & 1 << 17) ? "ThermStatus, " : "",
4949 (msr & 1 << 22) ? "VR-Therm, " : "",
4950 (msr & 1 << 24) ? "Amps, " : "",
4951 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : "");
4952 }
4953 return 0;
4954 }
4955
4956 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */
4957 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */
4958
4959 double get_quirk_tdp(void)
4960 {
4961 if (platform->rapl_quirk_tdp)
4962 return platform->rapl_quirk_tdp;
4963
4964 return 135.0;
4965 }
4966
4967 double get_tdp_intel(void)
4968 {
4969 unsigned long long msr;
4970
4971 if (platform->rapl_msrs & RAPL_PKG_POWER_INFO)
4972 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr))
4973 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units;
4974 return get_quirk_tdp();
4975 }
4976
4977 double get_tdp_amd(void)
4978 {
4979 return get_quirk_tdp();
4980 }
4981
4982 void rapl_probe_intel(void)
4983 {
4984 unsigned long long msr;
4985 unsigned int time_unit;
4986 double tdp;
4987
4988 if (rapl_joules) {
4989 if (platform->rapl_msrs & RAPL_PKG_ENERGY_STATUS)
4990 BIC_PRESENT(BIC_Pkg_J);
4991 if (platform->rapl_msrs & RAPL_CORE_ENERGY_STATUS)
4992 BIC_PRESENT(BIC_Cor_J);
4993 if (platform->rapl_msrs & RAPL_DRAM_ENERGY_STATUS)
4994 BIC_PRESENT(BIC_RAM_J);
4995 if (platform->rapl_msrs & RAPL_GFX_ENERGY_STATUS)
4996 BIC_PRESENT(BIC_GFX_J);
4997 } else {
4998 if (platform->rapl_msrs & RAPL_PKG_ENERGY_STATUS)
4999 BIC_PRESENT(BIC_PkgWatt);
5000 if (platform->rapl_msrs & RAPL_CORE_ENERGY_STATUS)
5001 BIC_PRESENT(BIC_CorWatt);
5002 if (platform->rapl_msrs & RAPL_DRAM_ENERGY_STATUS)
5003 BIC_PRESENT(BIC_RAMWatt);
5004 if (platform->rapl_msrs & RAPL_GFX_ENERGY_STATUS)
5005 BIC_PRESENT(BIC_GFXWatt);
5006 }
5007
5008 if (platform->rapl_msrs & RAPL_PKG_PERF_STATUS)
5009 BIC_PRESENT(BIC_PKG__);
5010 if (platform->rapl_msrs & RAPL_DRAM_PERF_STATUS)
5011 BIC_PRESENT(BIC_RAM__);
5012
5013 /* units on package 0, verify later other packages match */
5014 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr))
5015 return;
5016
5017 rapl_power_units = 1.0 / (1 << (msr & 0xF));
5018 if (platform->has_rapl_divisor)
5019 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000;
5020 else
5021 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F));
5022
5023 if (platform->has_fixed_rapl_unit)
5024 rapl_dram_energy_units = (15.3 / 1000000);
5025 else
5026 rapl_dram_energy_units = rapl_energy_units;
5027
5028 time_unit = msr >> 16 & 0xF;
5029 if (time_unit == 0)
5030 time_unit = 0xA;
5031
5032 rapl_time_units = 1.0 / (1 << (time_unit));
5033
5034 tdp = get_tdp_intel();
5035
5036 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
5037 if (!quiet)
5038 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
5039 }
5040
5041 void rapl_probe_amd(void)
5042 {
5043 unsigned long long msr;
5044 double tdp;
5045
5046 if (rapl_joules) {
5047 BIC_PRESENT(BIC_Pkg_J);
5048 BIC_PRESENT(BIC_Cor_J);
5049 } else {
5050 BIC_PRESENT(BIC_PkgWatt);
5051 BIC_PRESENT(BIC_CorWatt);
5052 }
5053
5054 if (get_msr(base_cpu, MSR_RAPL_PWR_UNIT, &msr))
5055 return;
5056
5057 rapl_time_units = ldexp(1.0, -(msr >> 16 & 0xf));
5058 rapl_energy_units = ldexp(1.0, -(msr >> 8 & 0x1f));
5059 rapl_power_units = ldexp(1.0, -(msr & 0xf));
5060
5061 tdp = get_tdp_amd();
5062
5063 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
5064 if (!quiet)
5065 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
5066 }
5067
5068 void print_power_limit_msr(int cpu, unsigned long long msr, char *label)
5069 {
5070 fprintf(outf, "cpu%d: %s: %sabled (%0.3f Watts, %f sec, clamp %sabled)\n",
5071 cpu, label,
5072 ((msr >> 15) & 1) ? "EN" : "DIS",
5073 ((msr >> 0) & 0x7FFF) * rapl_power_units,
5074 (1.0 + (((msr >> 22) & 0x3) / 4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units,
5075 (((msr >> 16) & 1) ? "EN" : "DIS"));
5076
5077 return;
5078 }
5079
5080 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p)
5081 {
5082 unsigned long long msr;
5083 const char *msr_name;
5084 int cpu;
5085
5086 UNUSED(c);
5087 UNUSED(p);
5088
5089 if (!platform->rapl_msrs)
5090 return 0;
5091
5092 /* RAPL counters are per package, so print only for 1st thread/package */
5093 if (!is_cpu_first_thread_in_package(t, c, p))
5094 return 0;
5095
5096 cpu = t->cpu_id;
5097 if (cpu_migrate(cpu)) {
5098 fprintf(outf, "print_rapl: Could not migrate to CPU %d\n", cpu);
5099 return -1;
5100 }
5101
5102 if (platform->rapl_msrs & RAPL_AMD_F17H) {
5103 msr_name = "MSR_RAPL_PWR_UNIT";
5104 if (get_msr(cpu, MSR_RAPL_PWR_UNIT, &msr))
5105 return -1;
5106 } else {
5107 msr_name = "MSR_RAPL_POWER_UNIT";
5108 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr))
5109 return -1;
5110 }
5111
5112 fprintf(outf, "cpu%d: %s: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr_name, msr,
5113 rapl_power_units, rapl_energy_units, rapl_time_units);
5114
5115 if (platform->rapl_msrs & RAPL_PKG_POWER_INFO) {
5116
5117 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr))
5118 return -5;
5119
5120 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
5121 cpu, msr,
5122 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
5123 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
5124 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
5125 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
5126
5127 }
5128 if (platform->rapl_msrs & RAPL_PKG) {
5129
5130 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr))
5131 return -9;
5132
5133 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n",
5134 cpu, msr, (msr >> 63) & 1 ? "" : "UN");
5135
5136 print_power_limit_msr(cpu, msr, "PKG Limit #1");
5137 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%0.3f Watts, %f* sec, clamp %sabled)\n",
5138 cpu,
5139 ((msr >> 47) & 1) ? "EN" : "DIS",
5140 ((msr >> 32) & 0x7FFF) * rapl_power_units,
5141 (1.0 + (((msr >> 54) & 0x3) / 4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units,
5142 ((msr >> 48) & 1) ? "EN" : "DIS");
5143
5144 if (get_msr(cpu, MSR_VR_CURRENT_CONFIG, &msr))
5145 return -9;
5146
5147 fprintf(outf, "cpu%d: MSR_VR_CURRENT_CONFIG: 0x%08llx\n", cpu, msr);
5148 fprintf(outf, "cpu%d: PKG Limit #4: %f Watts (%slocked)\n",
5149 cpu, ((msr >> 0) & 0x1FFF) * rapl_power_units, (msr >> 31) & 1 ? "" : "UN");
5150 }
5151
5152 if (platform->rapl_msrs & RAPL_DRAM_POWER_INFO) {
5153 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr))
5154 return -6;
5155
5156 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
5157 cpu, msr,
5158 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
5159 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
5160 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
5161 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
5162 }
5163 if (platform->rapl_msrs & RAPL_DRAM) {
5164 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr))
5165 return -9;
5166 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n",
5167 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
5168
5169 print_power_limit_msr(cpu, msr, "DRAM Limit");
5170 }
5171 if (platform->rapl_msrs & RAPL_CORE_POLICY) {
5172 if (get_msr(cpu, MSR_PP0_POLICY, &msr))
5173 return -7;
5174
5175 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF);
5176 }
5177 if (platform->rapl_msrs & RAPL_CORE_POWER_LIMIT) {
5178 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr))
5179 return -9;
5180 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n",
5181 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
5182 print_power_limit_msr(cpu, msr, "Cores Limit");
5183 }
5184 if (platform->rapl_msrs & RAPL_GFX) {
5185 if (get_msr(cpu, MSR_PP1_POLICY, &msr))
5186 return -8;
5187
5188 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF);
5189
5190 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr))
5191 return -9;
5192 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n",
5193 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
5194 print_power_limit_msr(cpu, msr, "GFX Limit");
5195 }
5196 return 0;
5197 }
5198
5199 /*
5200 * probe_rapl()
5201 *
5202 * sets rapl_power_units, rapl_energy_units, rapl_time_units
5203 */
5204 void probe_rapl(void)
5205 {
5206 if (!platform->rapl_msrs)
5207 return;
5208
5209 if (genuine_intel)
5210 rapl_probe_intel();
5211 if (authentic_amd || hygon_genuine)
5212 rapl_probe_amd();
5213
5214 if (quiet)
5215 return;
5216
5217 for_all_cpus(print_rapl, ODD_COUNTERS);
5218 }
5219
5220 /*
5221 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where
5222 * the Thermal Control Circuit (TCC) activates.
5223 * This is usually equal to tjMax.
5224 *
5225 * Older processors do not have this MSR, so there we guess,
5226 * but also allow cmdline over-ride with -T.
5227 *
5228 * Several MSR temperature values are in units of degrees-C
5229 * below this value, including the Digital Thermal Sensor (DTS),
5230 * Package Thermal Management Sensor (PTM), and thermal event thresholds.
5231 */
5232 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p)
5233 {
5234 unsigned long long msr;
5235 unsigned int tcc_default, tcc_offset;
5236 int cpu;
5237
5238 UNUSED(c);
5239 UNUSED(p);
5240
5241 /* tj_max is used only for dts or ptm */
5242 if (!(do_dts || do_ptm))
5243 return 0;
5244
5245 /* this is a per-package concept */
5246 if (!is_cpu_first_thread_in_package(t, c, p))
5247 return 0;
5248
5249 cpu = t->cpu_id;
5250 if (cpu_migrate(cpu)) {
5251 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
5252 return -1;
5253 }
5254
5255 if (tj_max_override != 0) {
5256 tj_max = tj_max_override;
5257 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", cpu, tj_max);
5258 return 0;
5259 }
5260
5261 /* Temperature Target MSR is Nehalem and newer only */
5262 if (!platform->has_nhm_msrs)
5263 goto guess;
5264
5265 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr))
5266 goto guess;
5267
5268 tcc_default = (msr >> 16) & 0xFF;
5269
5270 if (!quiet) {
5271 int bits = platform->tcc_offset_bits;
5272 unsigned long long enabled = 0;
5273
5274 if (bits && !get_msr(base_cpu, MSR_PLATFORM_INFO, &enabled))
5275 enabled = (enabled >> 30) & 1;
5276
5277 if (bits && enabled) {
5278 tcc_offset = (msr >> 24) & GENMASK(bits - 1, 0);
5279 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n",
5280 cpu, msr, tcc_default - tcc_offset, tcc_default, tcc_offset);
5281 } else {
5282 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", cpu, msr, tcc_default);
5283 }
5284 }
5285
5286 if (!tcc_default)
5287 goto guess;
5288
5289 tj_max = tcc_default;
5290
5291 return 0;
5292
5293 guess:
5294 tj_max = TJMAX_DEFAULT;
5295 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", cpu, tj_max);
5296
5297 return 0;
5298 }
5299
5300 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p)
5301 {
5302 unsigned long long msr;
5303 unsigned int dts, dts2;
5304 int cpu;
5305
5306 UNUSED(c);
5307 UNUSED(p);
5308
5309 if (!(do_dts || do_ptm))
5310 return 0;
5311
5312 cpu = t->cpu_id;
5313
5314 /* DTS is per-core, no need to print for each thread */
5315 if (!is_cpu_first_thread_in_core(t, c, p))
5316 return 0;
5317
5318 if (cpu_migrate(cpu)) {
5319 fprintf(outf, "print_thermal: Could not migrate to CPU %d\n", cpu);
5320 return -1;
5321 }
5322
5323 if (do_ptm && is_cpu_first_core_in_package(t, c, p)) {
5324 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
5325 return 0;
5326
5327 dts = (msr >> 16) & 0x7F;
5328 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", cpu, msr, tj_max - dts);
5329
5330 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr))
5331 return 0;
5332
5333 dts = (msr >> 16) & 0x7F;
5334 dts2 = (msr >> 8) & 0x7F;
5335 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
5336 cpu, msr, tj_max - dts, tj_max - dts2);
5337 }
5338
5339 if (do_dts && debug) {
5340 unsigned int resolution;
5341
5342 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
5343 return 0;
5344
5345 dts = (msr >> 16) & 0x7F;
5346 resolution = (msr >> 27) & 0xF;
5347 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n",
5348 cpu, msr, tj_max - dts, resolution);
5349
5350 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr))
5351 return 0;
5352
5353 dts = (msr >> 16) & 0x7F;
5354 dts2 = (msr >> 8) & 0x7F;
5355 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
5356 cpu, msr, tj_max - dts, tj_max - dts2);
5357 }
5358
5359 return 0;
5360 }
5361
5362 void probe_thermal(void)
5363 {
5364 if (!access("/sys/devices/system/cpu/cpu0/thermal_throttle/core_throttle_count", R_OK))
5365 BIC_PRESENT(BIC_CORE_THROT_CNT);
5366 else
5367 BIC_NOT_PRESENT(BIC_CORE_THROT_CNT);
5368
5369 for_all_cpus(set_temperature_target, ODD_COUNTERS);
5370
5371 if (quiet)
5372 return;
5373
5374 for_all_cpus(print_thermal, ODD_COUNTERS);
5375 }
5376
5377 int get_cpu_type(struct thread_data *t, struct core_data *c, struct pkg_data *p)
5378 {
5379 unsigned int eax, ebx, ecx, edx;
5380
5381 UNUSED(c);
5382 UNUSED(p);
5383
5384 if (!genuine_intel)
5385 return 0;
5386
5387 if (cpu_migrate(t->cpu_id)) {
5388 fprintf(outf, "Could not migrate to CPU %d\n", t->cpu_id);
5389 return -1;
5390 }
5391
5392 if (max_level < 0x1a)
5393 return 0;
5394
5395 __cpuid(0x1a, eax, ebx, ecx, edx);
5396 eax = (eax >> 24) & 0xFF;
5397 if (eax == 0x20)
5398 t->is_atom = true;
5399 return 0;
5400 }
5401
5402 void decode_feature_control_msr(void)
5403 {
5404 unsigned long long msr;
5405
5406 if (!get_msr(base_cpu, MSR_IA32_FEAT_CTL, &msr))
5407 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n",
5408 base_cpu, msr, msr & FEAT_CTL_LOCKED ? "" : "UN-", msr & (1 << 18) ? "SGX" : "");
5409 }
5410
5411 void decode_misc_enable_msr(void)
5412 {
5413 unsigned long long msr;
5414
5415 if (!genuine_intel)
5416 return;
5417
5418 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr))
5419 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n",
5420 base_cpu, msr,
5421 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-",
5422 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-",
5423 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "" : "No-",
5424 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "",
5425 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : "");
5426 }
5427
5428 void decode_misc_feature_control(void)
5429 {
5430 unsigned long long msr;
5431
5432 if (!platform->has_msr_misc_feature_control)
5433 return;
5434
5435 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr))
5436 fprintf(outf,
5437 "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n",
5438 base_cpu, msr, msr & (0 << 0) ? "No-" : "", msr & (1 << 0) ? "No-" : "",
5439 msr & (2 << 0) ? "No-" : "", msr & (3 << 0) ? "No-" : "");
5440 }
5441
5442 /*
5443 * Decode MSR_MISC_PWR_MGMT
5444 *
5445 * Decode the bits according to the Nehalem documentation
5446 * bit[0] seems to continue to have same meaning going forward
5447 * bit[1] less so...
5448 */
5449 void decode_misc_pwr_mgmt_msr(void)
5450 {
5451 unsigned long long msr;
5452
5453 if (!platform->has_msr_misc_pwr_mgmt)
5454 return;
5455
5456 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr))
5457 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n",
5458 base_cpu, msr,
5459 msr & (1 << 0) ? "DIS" : "EN", msr & (1 << 1) ? "EN" : "DIS", msr & (1 << 8) ? "EN" : "DIS");
5460 }
5461
5462 /*
5463 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG
5464 *
5465 * This MSRs are present on Silvermont processors,
5466 * Intel Atom processor E3000 series (Baytrail), and friends.
5467 */
5468 void decode_c6_demotion_policy_msr(void)
5469 {
5470 unsigned long long msr;
5471
5472 if (!platform->has_msr_c6_demotion_policy_config)
5473 return;
5474
5475 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr))
5476 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n",
5477 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
5478
5479 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr))
5480 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n",
5481 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
5482 }
5483
5484 void print_dev_latency(void)
5485 {
5486 char *path = "/dev/cpu_dma_latency";
5487 int fd;
5488 int value;
5489 int retval;
5490
5491 fd = open(path, O_RDONLY);
5492 if (fd < 0) {
5493 warnx("capget(CAP_SYS_ADMIN) failed, try \"# setcap cap_sys_admin=ep %s\"", progname);
5494 return;
5495 }
5496
5497 retval = read(fd, (void *)&value, sizeof(int));
5498 if (retval != sizeof(int)) {
5499 warn("read failed %s", path);
5500 close(fd);
5501 return;
5502 }
5503 fprintf(outf, "/dev/cpu_dma_latency: %d usec (%s)\n", value, value == 2000000000 ? "default" : "constrained");
5504
5505 close(fd);
5506 }
5507
5508 /*
5509 * Linux-perf manages the HW instructions-retired counter
5510 * by enabling when requested, and hiding rollover
5511 */
5512 void linux_perf_init(void)
5513 {
5514 if (!BIC_IS_ENABLED(BIC_IPC))
5515 return;
5516
5517 if (access("/proc/sys/kernel/perf_event_paranoid", F_OK))
5518 return;
5519
5520 fd_instr_count_percpu = calloc(topo.max_cpu_num + 1, sizeof(int));
5521 if (fd_instr_count_percpu == NULL)
5522 err(-1, "calloc fd_instr_count_percpu");
5523
5524 BIC_PRESENT(BIC_IPC);
5525 }
5526
5527 void probe_cstates(void)
5528 {
5529 probe_cst_limit();
5530
5531 if (platform->supported_cstates & CC1)
5532 BIC_PRESENT(BIC_CPU_c1);
5533
5534 if (platform->supported_cstates & CC3)
5535 BIC_PRESENT(BIC_CPU_c3);
5536
5537 if (platform->supported_cstates & CC6)
5538 BIC_PRESENT(BIC_CPU_c6);
5539
5540 if (platform->supported_cstates & CC7)
5541 BIC_PRESENT(BIC_CPU_c7);
5542
5543 if (platform->supported_cstates & PC2 && (pkg_cstate_limit >= PCL__2))
5544 BIC_PRESENT(BIC_Pkgpc2);
5545
5546 if (platform->supported_cstates & PC3 && (pkg_cstate_limit >= PCL__3))
5547 BIC_PRESENT(BIC_Pkgpc3);
5548
5549 if (platform->supported_cstates & PC6 && (pkg_cstate_limit >= PCL__6))
5550 BIC_PRESENT(BIC_Pkgpc6);
5551
5552 if (platform->supported_cstates & PC7 && (pkg_cstate_limit >= PCL__7))
5553 BIC_PRESENT(BIC_Pkgpc7);
5554
5555 if (platform->supported_cstates & PC8 && (pkg_cstate_limit >= PCL__8))
5556 BIC_PRESENT(BIC_Pkgpc8);
5557
5558 if (platform->supported_cstates & PC9 && (pkg_cstate_limit >= PCL__9))
5559 BIC_PRESENT(BIC_Pkgpc9);
5560
5561 if (platform->supported_cstates & PC10 && (pkg_cstate_limit >= PCL_10))
5562 BIC_PRESENT(BIC_Pkgpc10);
5563
5564 if (platform->has_msr_module_c6_res_ms)
5565 BIC_PRESENT(BIC_Mod_c6);
5566
5567 if (platform->has_ext_cst_msrs) {
5568 BIC_PRESENT(BIC_Totl_c0);
5569 BIC_PRESENT(BIC_Any_c0);
5570 BIC_PRESENT(BIC_GFX_c0);
5571 BIC_PRESENT(BIC_CPUGFX);
5572 }
5573
5574 if (quiet)
5575 return;
5576
5577 dump_power_ctl();
5578 dump_cst_cfg();
5579 decode_c6_demotion_policy_msr();
5580 print_dev_latency();
5581 dump_sysfs_cstate_config();
5582 print_irtl();
5583 }
5584
5585 void probe_lpi(void)
5586 {
5587 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", R_OK))
5588 BIC_PRESENT(BIC_CPU_LPI);
5589 else
5590 BIC_NOT_PRESENT(BIC_CPU_LPI);
5591
5592 if (!access(sys_lpi_file_sysfs, R_OK)) {
5593 sys_lpi_file = sys_lpi_file_sysfs;
5594 BIC_PRESENT(BIC_SYS_LPI);
5595 } else if (!access(sys_lpi_file_debugfs, R_OK)) {
5596 sys_lpi_file = sys_lpi_file_debugfs;
5597 BIC_PRESENT(BIC_SYS_LPI);
5598 } else {
5599 sys_lpi_file_sysfs = NULL;
5600 BIC_NOT_PRESENT(BIC_SYS_LPI);
5601 }
5602
5603 }
5604
5605 void probe_pstates(void)
5606 {
5607 probe_bclk();
5608
5609 if (quiet)
5610 return;
5611
5612 dump_platform_info();
5613 dump_turbo_ratio_info();
5614 dump_sysfs_pstate_config();
5615 decode_misc_pwr_mgmt_msr();
5616
5617 for_all_cpus(print_hwp, ODD_COUNTERS);
5618 for_all_cpus(print_epb, ODD_COUNTERS);
5619 for_all_cpus(print_perf_limit, ODD_COUNTERS);
5620 }
5621
5622 void process_cpuid()
5623 {
5624 unsigned int eax, ebx, ecx, edx;
5625 unsigned int fms, family, model, stepping, ecx_flags, edx_flags;
5626 unsigned long long ucode_patch = 0;
5627
5628 eax = ebx = ecx = edx = 0;
5629
5630 __cpuid(0, max_level, ebx, ecx, edx);
5631
5632 if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
5633 genuine_intel = 1;
5634 else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
5635 authentic_amd = 1;
5636 else if (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e)
5637 hygon_genuine = 1;
5638
5639 if (!quiet)
5640 fprintf(outf, "CPUID(0): %.4s%.4s%.4s 0x%x CPUID levels\n",
5641 (char *)&ebx, (char *)&edx, (char *)&ecx, max_level);
5642
5643 __cpuid(1, fms, ebx, ecx, edx);
5644 family = (fms >> 8) & 0xf;
5645 model = (fms >> 4) & 0xf;
5646 stepping = fms & 0xf;
5647 if (family == 0xf)
5648 family += (fms >> 20) & 0xff;
5649 if (family >= 6)
5650 model += ((fms >> 16) & 0xf) << 4;
5651 ecx_flags = ecx;
5652 edx_flags = edx;
5653
5654 if (get_msr(sched_getcpu(), MSR_IA32_UCODE_REV, &ucode_patch))
5655 warnx("get_msr(UCODE)");
5656
5657 /*
5658 * check max extended function levels of CPUID.
5659 * This is needed to check for invariant TSC.
5660 * This check is valid for both Intel and AMD.
5661 */
5662 ebx = ecx = edx = 0;
5663 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx);
5664
5665 if (!quiet) {
5666 fprintf(outf, "CPUID(1): family:model:stepping 0x%x:%x:%x (%d:%d:%d) microcode 0x%x\n",
5667 family, model, stepping, family, model, stepping,
5668 (unsigned int)((ucode_patch >> 32) & 0xFFFFFFFF));
5669 fprintf(outf, "CPUID(0x80000000): max_extended_levels: 0x%x\n", max_extended_level);
5670 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s %s\n",
5671 ecx_flags & (1 << 0) ? "SSE3" : "-",
5672 ecx_flags & (1 << 3) ? "MONITOR" : "-",
5673 ecx_flags & (1 << 6) ? "SMX" : "-",
5674 ecx_flags & (1 << 7) ? "EIST" : "-",
5675 ecx_flags & (1 << 8) ? "TM2" : "-",
5676 edx_flags & (1 << 4) ? "TSC" : "-",
5677 edx_flags & (1 << 5) ? "MSR" : "-",
5678 edx_flags & (1 << 22) ? "ACPI-TM" : "-",
5679 edx_flags & (1 << 28) ? "HT" : "-", edx_flags & (1 << 29) ? "TM" : "-");
5680 }
5681
5682 probe_platform_features(family, model);
5683
5684 if (!(edx_flags & (1 << 5)))
5685 errx(1, "CPUID: no MSR");
5686
5687 if (max_extended_level >= 0x80000007) {
5688
5689 /*
5690 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8
5691 * this check is valid for both Intel and AMD
5692 */
5693 __cpuid(0x80000007, eax, ebx, ecx, edx);
5694 has_invariant_tsc = edx & (1 << 8);
5695 }
5696
5697 /*
5698 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0
5699 * this check is valid for both Intel and AMD
5700 */
5701
5702 __cpuid(0x6, eax, ebx, ecx, edx);
5703 has_aperf = ecx & (1 << 0);
5704 if (has_aperf) {
5705 BIC_PRESENT(BIC_Avg_MHz);
5706 BIC_PRESENT(BIC_Busy);
5707 BIC_PRESENT(BIC_Bzy_MHz);
5708 }
5709 do_dts = eax & (1 << 0);
5710 if (do_dts)
5711 BIC_PRESENT(BIC_CoreTmp);
5712 has_turbo = eax & (1 << 1);
5713 do_ptm = eax & (1 << 6);
5714 if (do_ptm)
5715 BIC_PRESENT(BIC_PkgTmp);
5716 has_hwp = eax & (1 << 7);
5717 has_hwp_notify = eax & (1 << 8);
5718 has_hwp_activity_window = eax & (1 << 9);
5719 has_hwp_epp = eax & (1 << 10);
5720 has_hwp_pkg = eax & (1 << 11);
5721 has_epb = ecx & (1 << 3);
5722
5723 if (!quiet)
5724 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, "
5725 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n",
5726 has_aperf ? "" : "No-",
5727 has_turbo ? "" : "No-",
5728 do_dts ? "" : "No-",
5729 do_ptm ? "" : "No-",
5730 has_hwp ? "" : "No-",
5731 has_hwp_notify ? "" : "No-",
5732 has_hwp_activity_window ? "" : "No-",
5733 has_hwp_epp ? "" : "No-", has_hwp_pkg ? "" : "No-", has_epb ? "" : "No-");
5734
5735 if (!quiet)
5736 decode_misc_enable_msr();
5737
5738 if (max_level >= 0x7 && !quiet) {
5739 int has_sgx;
5740
5741 ecx = 0;
5742
5743 __cpuid_count(0x7, 0, eax, ebx, ecx, edx);
5744
5745 has_sgx = ebx & (1 << 2);
5746
5747 is_hybrid = edx & (1 << 15);
5748
5749 fprintf(outf, "CPUID(7): %sSGX %sHybrid\n", has_sgx ? "" : "No-", is_hybrid ? "" : "No-");
5750
5751 if (has_sgx)
5752 decode_feature_control_msr();
5753 }
5754
5755 if (max_level >= 0x15) {
5756 unsigned int eax_crystal;
5757 unsigned int ebx_tsc;
5758
5759 /*
5760 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz
5761 */
5762 eax_crystal = ebx_tsc = crystal_hz = edx = 0;
5763 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx);
5764
5765 if (ebx_tsc != 0) {
5766 if (!quiet && (ebx != 0))
5767 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n",
5768 eax_crystal, ebx_tsc, crystal_hz);
5769
5770 if (crystal_hz == 0)
5771 crystal_hz = platform->crystal_freq;
5772
5773 if (crystal_hz) {
5774 tsc_hz = (unsigned long long)crystal_hz *ebx_tsc / eax_crystal;
5775 if (!quiet)
5776 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n",
5777 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal);
5778 }
5779 }
5780 }
5781 if (max_level >= 0x16) {
5782 unsigned int base_mhz, max_mhz, bus_mhz, edx;
5783
5784 /*
5785 * CPUID 16H Base MHz, Max MHz, Bus MHz
5786 */
5787 base_mhz = max_mhz = bus_mhz = edx = 0;
5788
5789 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx);
5790 if (!quiet)
5791 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n",
5792 base_mhz, max_mhz, bus_mhz);
5793 }
5794
5795 if (has_aperf)
5796 aperf_mperf_multiplier = platform->need_perf_multiplier ? 1024 : 1;
5797
5798 BIC_PRESENT(BIC_IRQ);
5799 BIC_PRESENT(BIC_TSC_MHz);
5800 }
5801
5802 void probe_pm_features(void)
5803 {
5804 probe_pstates();
5805
5806 probe_cstates();
5807
5808 probe_lpi();
5809
5810 probe_intel_uncore_frequency();
5811
5812 probe_graphics();
5813
5814 probe_rapl();
5815
5816 probe_thermal();
5817
5818 if (platform->has_nhm_msrs)
5819 BIC_PRESENT(BIC_SMI);
5820
5821 if (!quiet)
5822 decode_misc_feature_control();
5823 }
5824
5825 /*
5826 * in /dev/cpu/ return success for names that are numbers
5827 * ie. filter out ".", "..", "microcode".
5828 */
5829 int dir_filter(const struct dirent *dirp)
5830 {
5831 if (isdigit(dirp->d_name[0]))
5832 return 1;
5833 else
5834 return 0;
5835 }
5836
5837 void topology_probe(bool startup)
5838 {
5839 int i;
5840 int max_core_id = 0;
5841 int max_package_id = 0;
5842 int max_die_id = 0;
5843 int max_siblings = 0;
5844
5845 /* Initialize num_cpus, max_cpu_num */
5846 set_max_cpu_num();
5847 topo.num_cpus = 0;
5848 for_all_proc_cpus(count_cpus);
5849 if (!summary_only && topo.num_cpus > 1)
5850 BIC_PRESENT(BIC_CPU);
5851
5852 if (debug > 1)
5853 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num);
5854
5855 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology));
5856 if (cpus == NULL)
5857 err(1, "calloc cpus");
5858
5859 /*
5860 * Allocate and initialize cpu_present_set
5861 */
5862 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1));
5863 if (cpu_present_set == NULL)
5864 err(3, "CPU_ALLOC");
5865 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
5866 CPU_ZERO_S(cpu_present_setsize, cpu_present_set);
5867 for_all_proc_cpus(mark_cpu_present);
5868
5869 /*
5870 * Allocate and initialize cpu_effective_set
5871 */
5872 cpu_effective_set = CPU_ALLOC((topo.max_cpu_num + 1));
5873 if (cpu_effective_set == NULL)
5874 err(3, "CPU_ALLOC");
5875 cpu_effective_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
5876 CPU_ZERO_S(cpu_effective_setsize, cpu_effective_set);
5877 update_effective_set(startup);
5878
5879 /*
5880 * Allocate and initialize cpu_allowed_set
5881 */
5882 cpu_allowed_set = CPU_ALLOC((topo.max_cpu_num + 1));
5883 if (cpu_allowed_set == NULL)
5884 err(3, "CPU_ALLOC");
5885 cpu_allowed_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
5886 CPU_ZERO_S(cpu_allowed_setsize, cpu_allowed_set);
5887
5888 /*
5889 * Validate and update cpu_allowed_set.
5890 *
5891 * Make sure all cpus in cpu_subset are also in cpu_present_set during startup.
5892 * Give a warning when cpus in cpu_subset become unavailable at runtime.
5893 * Give a warning when cpus are not effective because of cgroup setting.
5894 *
5895 * cpu_allowed_set is the intersection of cpu_present_set/cpu_effective_set/cpu_subset.
5896 */
5897 for (i = 0; i < CPU_SUBSET_MAXCPUS; ++i) {
5898 if (cpu_subset && !CPU_ISSET_S(i, cpu_subset_size, cpu_subset))
5899 continue;
5900
5901 if (!CPU_ISSET_S(i, cpu_present_setsize, cpu_present_set)) {
5902 if (cpu_subset) {
5903 /* cpus in cpu_subset must be in cpu_present_set during startup */
5904 if (startup)
5905 err(1, "cpu%d not present", i);
5906 else
5907 fprintf(stderr, "cpu%d not present\n", i);
5908 }
5909 continue;
5910 }
5911
5912 if (CPU_COUNT_S(cpu_effective_setsize, cpu_effective_set)) {
5913 if (!CPU_ISSET_S(i, cpu_effective_setsize, cpu_effective_set)) {
5914 fprintf(stderr, "cpu%d not effective\n", i);
5915 continue;
5916 }
5917 }
5918
5919 CPU_SET_S(i, cpu_allowed_setsize, cpu_allowed_set);
5920 }
5921
5922 if (!CPU_COUNT_S(cpu_allowed_setsize, cpu_allowed_set))
5923 err(-ENODEV, "No valid cpus found");
5924 sched_setaffinity(0, cpu_allowed_setsize, cpu_allowed_set);
5925
5926 /*
5927 * Allocate and initialize cpu_affinity_set
5928 */
5929 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1));
5930 if (cpu_affinity_set == NULL)
5931 err(3, "CPU_ALLOC");
5932 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
5933 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
5934
5935 for_all_proc_cpus(init_thread_id);
5936
5937 /*
5938 * For online cpus
5939 * find max_core_id, max_package_id
5940 */
5941 for (i = 0; i <= topo.max_cpu_num; ++i) {
5942 int siblings;
5943
5944 if (cpu_is_not_present(i)) {
5945 if (debug > 1)
5946 fprintf(outf, "cpu%d NOT PRESENT\n", i);
5947 continue;
5948 }
5949
5950 cpus[i].logical_cpu_id = i;
5951
5952 /* get package information */
5953 cpus[i].physical_package_id = get_physical_package_id(i);
5954 if (cpus[i].physical_package_id > max_package_id)
5955 max_package_id = cpus[i].physical_package_id;
5956
5957 /* get die information */
5958 cpus[i].die_id = get_die_id(i);
5959 if (cpus[i].die_id > max_die_id)
5960 max_die_id = cpus[i].die_id;
5961
5962 /* get numa node information */
5963 cpus[i].physical_node_id = get_physical_node_id(&cpus[i]);
5964 if (cpus[i].physical_node_id > topo.max_node_num)
5965 topo.max_node_num = cpus[i].physical_node_id;
5966
5967 /* get core information */
5968 cpus[i].physical_core_id = get_core_id(i);
5969 if (cpus[i].physical_core_id > max_core_id)
5970 max_core_id = cpus[i].physical_core_id;
5971
5972 /* get thread information */
5973 siblings = get_thread_siblings(&cpus[i]);
5974 if (siblings > max_siblings)
5975 max_siblings = siblings;
5976 if (cpus[i].thread_id == 0)
5977 topo.num_cores++;
5978 }
5979
5980 topo.cores_per_node = max_core_id + 1;
5981 if (debug > 1)
5982 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", max_core_id, topo.cores_per_node);
5983 if (!summary_only && topo.cores_per_node > 1)
5984 BIC_PRESENT(BIC_Core);
5985
5986 topo.num_die = max_die_id + 1;
5987 if (debug > 1)
5988 fprintf(outf, "max_die_id %d, sizing for %d die\n", max_die_id, topo.num_die);
5989 if (!summary_only && topo.num_die > 1)
5990 BIC_PRESENT(BIC_Die);
5991
5992 topo.num_packages = max_package_id + 1;
5993 if (debug > 1)
5994 fprintf(outf, "max_package_id %d, sizing for %d packages\n", max_package_id, topo.num_packages);
5995 if (!summary_only && topo.num_packages > 1)
5996 BIC_PRESENT(BIC_Package);
5997
5998 set_node_data();
5999 if (debug > 1)
6000 fprintf(outf, "nodes_per_pkg %d\n", topo.nodes_per_pkg);
6001 if (!summary_only && topo.nodes_per_pkg > 1)
6002 BIC_PRESENT(BIC_Node);
6003
6004 topo.threads_per_core = max_siblings;
6005 if (debug > 1)
6006 fprintf(outf, "max_siblings %d\n", max_siblings);
6007
6008 if (debug < 1)
6009 return;
6010
6011 for (i = 0; i <= topo.max_cpu_num; ++i) {
6012 if (cpu_is_not_present(i))
6013 continue;
6014 fprintf(outf,
6015 "cpu %d pkg %d die %d node %d lnode %d core %d thread %d\n",
6016 i, cpus[i].physical_package_id, cpus[i].die_id,
6017 cpus[i].physical_node_id, cpus[i].logical_node_id, cpus[i].physical_core_id, cpus[i].thread_id);
6018 }
6019
6020 }
6021
6022 void allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p)
6023 {
6024 int i;
6025 int num_cores = topo.cores_per_node * topo.nodes_per_pkg * topo.num_packages;
6026 int num_threads = topo.threads_per_core * num_cores;
6027
6028 *t = calloc(num_threads, sizeof(struct thread_data));
6029 if (*t == NULL)
6030 goto error;
6031
6032 for (i = 0; i < num_threads; i++)
6033 (*t)[i].cpu_id = -1;
6034
6035 *c = calloc(num_cores, sizeof(struct core_data));
6036 if (*c == NULL)
6037 goto error;
6038
6039 for (i = 0; i < num_cores; i++) {
6040 (*c)[i].core_id = -1;
6041 (*c)[i].base_cpu = -1;
6042 }
6043
6044 *p = calloc(topo.num_packages, sizeof(struct pkg_data));
6045 if (*p == NULL)
6046 goto error;
6047
6048 for (i = 0; i < topo.num_packages; i++) {
6049 (*p)[i].package_id = i;
6050 (*p)[i].base_cpu = -1;
6051 }
6052
6053 return;
6054 error:
6055 err(1, "calloc counters");
6056 }
6057
6058 /*
6059 * init_counter()
6060 *
6061 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE
6062 */
6063 void init_counter(struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base, int cpu_id)
6064 {
6065 int pkg_id = cpus[cpu_id].physical_package_id;
6066 int node_id = cpus[cpu_id].logical_node_id;
6067 int core_id = cpus[cpu_id].physical_core_id;
6068 int thread_id = cpus[cpu_id].thread_id;
6069 struct thread_data *t;
6070 struct core_data *c;
6071 struct pkg_data *p;
6072
6073 /* Workaround for systems where physical_node_id==-1
6074 * and logical_node_id==(-1 - topo.num_cpus)
6075 */
6076 if (node_id < 0)
6077 node_id = 0;
6078
6079 t = GET_THREAD(thread_base, thread_id, core_id, node_id, pkg_id);
6080 c = GET_CORE(core_base, core_id, node_id, pkg_id);
6081 p = GET_PKG(pkg_base, pkg_id);
6082
6083 t->cpu_id = cpu_id;
6084 if (!cpu_is_not_allowed(cpu_id)) {
6085 if (c->base_cpu < 0)
6086 c->base_cpu = t->cpu_id;
6087 if (p->base_cpu < 0)
6088 p->base_cpu = t->cpu_id;
6089 }
6090
6091 c->core_id = core_id;
6092 p->package_id = pkg_id;
6093 }
6094
6095 int initialize_counters(int cpu_id)
6096 {
6097 init_counter(EVEN_COUNTERS, cpu_id);
6098 init_counter(ODD_COUNTERS, cpu_id);
6099 return 0;
6100 }
6101
6102 void allocate_output_buffer()
6103 {
6104 output_buffer = calloc(1, (1 + topo.num_cpus) * 2048);
6105 outp = output_buffer;
6106 if (outp == NULL)
6107 err(-1, "calloc output buffer");
6108 }
6109
6110 void allocate_fd_percpu(void)
6111 {
6112 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int));
6113 if (fd_percpu == NULL)
6114 err(-1, "calloc fd_percpu");
6115 }
6116
6117 void allocate_irq_buffers(void)
6118 {
6119 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int));
6120 if (irq_column_2_cpu == NULL)
6121 err(-1, "calloc %d", topo.num_cpus);
6122
6123 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int));
6124 if (irqs_per_cpu == NULL)
6125 err(-1, "calloc %d", topo.max_cpu_num + 1);
6126 }
6127
6128 int update_topo(struct thread_data *t, struct core_data *c, struct pkg_data *p)
6129 {
6130 topo.allowed_cpus++;
6131 if ((int)t->cpu_id == c->base_cpu)
6132 topo.allowed_cores++;
6133 if ((int)t->cpu_id == p->base_cpu)
6134 topo.allowed_packages++;
6135
6136 return 0;
6137 }
6138
6139 void topology_update(void)
6140 {
6141 topo.allowed_cpus = 0;
6142 topo.allowed_cores = 0;
6143 topo.allowed_packages = 0;
6144 for_all_cpus(update_topo, ODD_COUNTERS);
6145 }
6146 void setup_all_buffers(bool startup)
6147 {
6148 topology_probe(startup);
6149 allocate_irq_buffers();
6150 allocate_fd_percpu();
6151 allocate_counters(&thread_even, &core_even, &package_even);
6152 allocate_counters(&thread_odd, &core_odd, &package_odd);
6153 allocate_output_buffer();
6154 for_all_proc_cpus(initialize_counters);
6155 topology_update();
6156 }
6157
6158 void set_base_cpu(void)
6159 {
6160 int i;
6161
6162 for (i = 0; i < topo.max_cpu_num + 1; ++i) {
6163 if (cpu_is_not_allowed(i))
6164 continue;
6165 base_cpu = i;
6166 if (debug > 1)
6167 fprintf(outf, "base_cpu = %d\n", base_cpu);
6168 return;
6169 }
6170 err(-ENODEV, "No valid cpus found");
6171 }
6172
6173 void turbostat_init()
6174 {
6175 setup_all_buffers(true);
6176 set_base_cpu();
6177 check_dev_msr();
6178 check_permissions();
6179 process_cpuid();
6180 probe_pm_features();
6181 linux_perf_init();
6182
6183 for_all_cpus(get_cpu_type, ODD_COUNTERS);
6184 for_all_cpus(get_cpu_type, EVEN_COUNTERS);
6185
6186 if (DO_BIC(BIC_IPC))
6187 (void)get_instr_count_fd(base_cpu);
6188 }
6189
6190 int fork_it(char **argv)
6191 {
6192 pid_t child_pid;
6193 int status;
6194
6195 snapshot_proc_sysfs_files();
6196 status = for_all_cpus(get_counters, EVEN_COUNTERS);
6197 first_counter_read = 0;
6198 if (status)
6199 exit(status);
6200 gettimeofday(&tv_even, (struct timezone *)NULL);
6201
6202 child_pid = fork();
6203 if (!child_pid) {
6204 /* child */
6205 execvp(argv[0], argv);
6206 err(errno, "exec %s", argv[0]);
6207 } else {
6208
6209 /* parent */
6210 if (child_pid == -1)
6211 err(1, "fork");
6212
6213 signal(SIGINT, SIG_IGN);
6214 signal(SIGQUIT, SIG_IGN);
6215 if (waitpid(child_pid, &status, 0) == -1)
6216 err(status, "waitpid");
6217
6218 if (WIFEXITED(status))
6219 status = WEXITSTATUS(status);
6220 }
6221 /*
6222 * n.b. fork_it() does not check for errors from for_all_cpus()
6223 * because re-starting is problematic when forking
6224 */
6225 snapshot_proc_sysfs_files();
6226 for_all_cpus(get_counters, ODD_COUNTERS);
6227 gettimeofday(&tv_odd, (struct timezone *)NULL);
6228 timersub(&tv_odd, &tv_even, &tv_delta);
6229 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS))
6230 fprintf(outf, "%s: Counter reset detected\n", progname);
6231 else {
6232 compute_average(EVEN_COUNTERS);
6233 format_all_counters(EVEN_COUNTERS);
6234 }
6235
6236 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec / 1000000.0);
6237
6238 flush_output_stderr();
6239
6240 return status;
6241 }
6242
6243 int get_and_dump_counters(void)
6244 {
6245 int status;
6246
6247 snapshot_proc_sysfs_files();
6248 status = for_all_cpus(get_counters, ODD_COUNTERS);
6249 if (status)
6250 return status;
6251
6252 status = for_all_cpus(dump_counters, ODD_COUNTERS);
6253 if (status)
6254 return status;
6255
6256 flush_output_stdout();
6257
6258 return status;
6259 }
6260
6261 void print_version()
6262 {
6263 fprintf(outf, "turbostat version 2023.11.07 - Len Brown <lenb@kernel.org>\n");
6264 }
6265
6266 #define COMMAND_LINE_SIZE 2048
6267
6268 void print_bootcmd(void)
6269 {
6270 char bootcmd[COMMAND_LINE_SIZE];
6271 FILE *fp;
6272 int ret;
6273
6274 memset(bootcmd, 0, COMMAND_LINE_SIZE);
6275 fp = fopen("/proc/cmdline", "r");
6276 if (!fp)
6277 return;
6278
6279 ret = fread(bootcmd, sizeof(char), COMMAND_LINE_SIZE - 1, fp);
6280 if (ret) {
6281 bootcmd[ret] = '\0';
6282 /* the last character is already '\n' */
6283 fprintf(outf, "Kernel command line: %s", bootcmd);
6284 }
6285
6286 fclose(fp);
6287 }
6288
6289 int add_counter(unsigned int msr_num, char *path, char *name,
6290 unsigned int width, enum counter_scope scope,
6291 enum counter_type type, enum counter_format format, int flags)
6292 {
6293 struct msr_counter *msrp;
6294
6295 msrp = calloc(1, sizeof(struct msr_counter));
6296 if (msrp == NULL) {
6297 perror("calloc");
6298 exit(1);
6299 }
6300
6301 msrp->msr_num = msr_num;
6302 strncpy(msrp->name, name, NAME_BYTES - 1);
6303 if (path)
6304 strncpy(msrp->path, path, PATH_BYTES - 1);
6305 msrp->width = width;
6306 msrp->type = type;
6307 msrp->format = format;
6308 msrp->flags = flags;
6309
6310 switch (scope) {
6311
6312 case SCOPE_CPU:
6313 msrp->next = sys.tp;
6314 sys.tp = msrp;
6315 sys.added_thread_counters++;
6316 if (sys.added_thread_counters > MAX_ADDED_THREAD_COUNTERS) {
6317 fprintf(stderr, "exceeded max %d added thread counters\n", MAX_ADDED_COUNTERS);
6318 exit(-1);
6319 }
6320 break;
6321
6322 case SCOPE_CORE:
6323 msrp->next = sys.cp;
6324 sys.cp = msrp;
6325 sys.added_core_counters++;
6326 if (sys.added_core_counters > MAX_ADDED_COUNTERS) {
6327 fprintf(stderr, "exceeded max %d added core counters\n", MAX_ADDED_COUNTERS);
6328 exit(-1);
6329 }
6330 break;
6331
6332 case SCOPE_PACKAGE:
6333 msrp->next = sys.pp;
6334 sys.pp = msrp;
6335 sys.added_package_counters++;
6336 if (sys.added_package_counters > MAX_ADDED_COUNTERS) {
6337 fprintf(stderr, "exceeded max %d added package counters\n", MAX_ADDED_COUNTERS);
6338 exit(-1);
6339 }
6340 break;
6341 }
6342
6343 return 0;
6344 }
6345
6346 void parse_add_command(char *add_command)
6347 {
6348 int msr_num = 0;
6349 char *path = NULL;
6350 char name_buffer[NAME_BYTES] = "";
6351 int width = 64;
6352 int fail = 0;
6353 enum counter_scope scope = SCOPE_CPU;
6354 enum counter_type type = COUNTER_CYCLES;
6355 enum counter_format format = FORMAT_DELTA;
6356
6357 while (add_command) {
6358
6359 if (sscanf(add_command, "msr0x%x", &msr_num) == 1)
6360 goto next;
6361
6362 if (sscanf(add_command, "msr%d", &msr_num) == 1)
6363 goto next;
6364
6365 if (*add_command == '/') {
6366 path = add_command;
6367 goto next;
6368 }
6369
6370 if (sscanf(add_command, "u%d", &width) == 1) {
6371 if ((width == 32) || (width == 64))
6372 goto next;
6373 width = 64;
6374 }
6375 if (!strncmp(add_command, "cpu", strlen("cpu"))) {
6376 scope = SCOPE_CPU;
6377 goto next;
6378 }
6379 if (!strncmp(add_command, "core", strlen("core"))) {
6380 scope = SCOPE_CORE;
6381 goto next;
6382 }
6383 if (!strncmp(add_command, "package", strlen("package"))) {
6384 scope = SCOPE_PACKAGE;
6385 goto next;
6386 }
6387 if (!strncmp(add_command, "cycles", strlen("cycles"))) {
6388 type = COUNTER_CYCLES;
6389 goto next;
6390 }
6391 if (!strncmp(add_command, "seconds", strlen("seconds"))) {
6392 type = COUNTER_SECONDS;
6393 goto next;
6394 }
6395 if (!strncmp(add_command, "usec", strlen("usec"))) {
6396 type = COUNTER_USEC;
6397 goto next;
6398 }
6399 if (!strncmp(add_command, "raw", strlen("raw"))) {
6400 format = FORMAT_RAW;
6401 goto next;
6402 }
6403 if (!strncmp(add_command, "delta", strlen("delta"))) {
6404 format = FORMAT_DELTA;
6405 goto next;
6406 }
6407 if (!strncmp(add_command, "percent", strlen("percent"))) {
6408 format = FORMAT_PERCENT;
6409 goto next;
6410 }
6411
6412 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */
6413 char *eos;
6414
6415 eos = strchr(name_buffer, ',');
6416 if (eos)
6417 *eos = '\0';
6418 goto next;
6419 }
6420
6421 next:
6422 add_command = strchr(add_command, ',');
6423 if (add_command) {
6424 *add_command = '\0';
6425 add_command++;
6426 }
6427
6428 }
6429 if ((msr_num == 0) && (path == NULL)) {
6430 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n");
6431 fail++;
6432 }
6433
6434 /* generate default column header */
6435 if (*name_buffer == '\0') {
6436 if (width == 32)
6437 sprintf(name_buffer, "M0x%x%s", msr_num, format == FORMAT_PERCENT ? "%" : "");
6438 else
6439 sprintf(name_buffer, "M0X%x%s", msr_num, format == FORMAT_PERCENT ? "%" : "");
6440 }
6441
6442 if (add_counter(msr_num, path, name_buffer, width, scope, type, format, 0))
6443 fail++;
6444
6445 if (fail) {
6446 help();
6447 exit(1);
6448 }
6449 }
6450
6451 int is_deferred_add(char *name)
6452 {
6453 int i;
6454
6455 for (i = 0; i < deferred_add_index; ++i)
6456 if (!strcmp(name, deferred_add_names[i]))
6457 return 1;
6458 return 0;
6459 }
6460
6461 int is_deferred_skip(char *name)
6462 {
6463 int i;
6464
6465 for (i = 0; i < deferred_skip_index; ++i)
6466 if (!strcmp(name, deferred_skip_names[i]))
6467 return 1;
6468 return 0;
6469 }
6470
6471 void probe_sysfs(void)
6472 {
6473 char path[64];
6474 char name_buf[16];
6475 FILE *input;
6476 int state;
6477 char *sp;
6478
6479 for (state = 10; state >= 0; --state) {
6480
6481 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state);
6482 input = fopen(path, "r");
6483 if (input == NULL)
6484 continue;
6485 if (!fgets(name_buf, sizeof(name_buf), input))
6486 err(1, "%s: failed to read file", path);
6487
6488 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
6489 sp = strchr(name_buf, '-');
6490 if (!sp)
6491 sp = strchrnul(name_buf, '\n');
6492 *sp = '%';
6493 *(sp + 1) = '\0';
6494
6495 remove_underbar(name_buf);
6496
6497 fclose(input);
6498
6499 sprintf(path, "cpuidle/state%d/time", state);
6500
6501 if (!DO_BIC(BIC_sysfs) && !is_deferred_add(name_buf))
6502 continue;
6503
6504 if (is_deferred_skip(name_buf))
6505 continue;
6506
6507 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_USEC, FORMAT_PERCENT, SYSFS_PERCPU);
6508 }
6509
6510 for (state = 10; state >= 0; --state) {
6511
6512 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state);
6513 input = fopen(path, "r");
6514 if (input == NULL)
6515 continue;
6516 if (!fgets(name_buf, sizeof(name_buf), input))
6517 err(1, "%s: failed to read file", path);
6518 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
6519 sp = strchr(name_buf, '-');
6520 if (!sp)
6521 sp = strchrnul(name_buf, '\n');
6522 *sp = '\0';
6523 fclose(input);
6524
6525 remove_underbar(name_buf);
6526
6527 sprintf(path, "cpuidle/state%d/usage", state);
6528
6529 if (!DO_BIC(BIC_sysfs) && !is_deferred_add(name_buf))
6530 continue;
6531
6532 if (is_deferred_skip(name_buf))
6533 continue;
6534
6535 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_ITEMS, FORMAT_DELTA, SYSFS_PERCPU);
6536 }
6537
6538 }
6539
6540 /*
6541 * parse cpuset with following syntax
6542 * 1,2,4..6,8-10 and set bits in cpu_subset
6543 */
6544 void parse_cpu_command(char *optarg)
6545 {
6546 if (!strcmp(optarg, "core")) {
6547 if (cpu_subset)
6548 goto error;
6549 show_core_only++;
6550 return;
6551 }
6552 if (!strcmp(optarg, "package")) {
6553 if (cpu_subset)
6554 goto error;
6555 show_pkg_only++;
6556 return;
6557 }
6558 if (show_core_only || show_pkg_only)
6559 goto error;
6560
6561 cpu_subset = CPU_ALLOC(CPU_SUBSET_MAXCPUS);
6562 if (cpu_subset == NULL)
6563 err(3, "CPU_ALLOC");
6564 cpu_subset_size = CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS);
6565
6566 CPU_ZERO_S(cpu_subset_size, cpu_subset);
6567
6568 if (parse_cpu_str(optarg, cpu_subset, cpu_subset_size))
6569 goto error;
6570
6571 return;
6572
6573 error:
6574 fprintf(stderr, "\"--cpu %s\" malformed\n", optarg);
6575 help();
6576 exit(-1);
6577 }
6578
6579 void cmdline(int argc, char **argv)
6580 {
6581 int opt;
6582 int option_index = 0;
6583 static struct option long_options[] = {
6584 { "add", required_argument, 0, 'a' },
6585 { "cpu", required_argument, 0, 'c' },
6586 { "Dump", no_argument, 0, 'D' },
6587 { "debug", no_argument, 0, 'd' }, /* internal, not documented */
6588 { "enable", required_argument, 0, 'e' },
6589 { "interval", required_argument, 0, 'i' },
6590 { "IPC", no_argument, 0, 'I' },
6591 { "num_iterations", required_argument, 0, 'n' },
6592 { "header_iterations", required_argument, 0, 'N' },
6593 { "help", no_argument, 0, 'h' },
6594 { "hide", required_argument, 0, 'H' }, // meh, -h taken by --help
6595 { "Joules", no_argument, 0, 'J' },
6596 { "list", no_argument, 0, 'l' },
6597 { "out", required_argument, 0, 'o' },
6598 { "quiet", no_argument, 0, 'q' },
6599 { "show", required_argument, 0, 's' },
6600 { "Summary", no_argument, 0, 'S' },
6601 { "TCC", required_argument, 0, 'T' },
6602 { "version", no_argument, 0, 'v' },
6603 { 0, 0, 0, 0 }
6604 };
6605
6606 progname = argv[0];
6607
6608 while ((opt = getopt_long_only(argc, argv, "+C:c:Dde:hi:Jn:o:qST:v", long_options, &option_index)) != -1) {
6609 switch (opt) {
6610 case 'a':
6611 parse_add_command(optarg);
6612 break;
6613 case 'c':
6614 parse_cpu_command(optarg);
6615 break;
6616 case 'D':
6617 dump_only++;
6618 break;
6619 case 'e':
6620 /* --enable specified counter */
6621 bic_enabled = bic_enabled | bic_lookup(optarg, SHOW_LIST);
6622 break;
6623 case 'd':
6624 debug++;
6625 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT);
6626 break;
6627 case 'H':
6628 /*
6629 * --hide: do not show those specified
6630 * multiple invocations simply clear more bits in enabled mask
6631 */
6632 bic_enabled &= ~bic_lookup(optarg, HIDE_LIST);
6633 break;
6634 case 'h':
6635 default:
6636 help();
6637 exit(1);
6638 case 'i':
6639 {
6640 double interval = strtod(optarg, NULL);
6641
6642 if (interval < 0.001) {
6643 fprintf(outf, "interval %f seconds is too small\n", interval);
6644 exit(2);
6645 }
6646
6647 interval_tv.tv_sec = interval_ts.tv_sec = interval;
6648 interval_tv.tv_usec = (interval - interval_tv.tv_sec) * 1000000;
6649 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000;
6650 }
6651 break;
6652 case 'J':
6653 rapl_joules++;
6654 break;
6655 case 'l':
6656 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT);
6657 list_header_only++;
6658 quiet++;
6659 break;
6660 case 'o':
6661 outf = fopen_or_die(optarg, "w");
6662 break;
6663 case 'q':
6664 quiet = 1;
6665 break;
6666 case 'n':
6667 num_iterations = strtod(optarg, NULL);
6668
6669 if (num_iterations <= 0) {
6670 fprintf(outf, "iterations %d should be positive number\n", num_iterations);
6671 exit(2);
6672 }
6673 break;
6674 case 'N':
6675 header_iterations = strtod(optarg, NULL);
6676
6677 if (header_iterations <= 0) {
6678 fprintf(outf, "iterations %d should be positive number\n", header_iterations);
6679 exit(2);
6680 }
6681 break;
6682 case 's':
6683 /*
6684 * --show: show only those specified
6685 * The 1st invocation will clear and replace the enabled mask
6686 * subsequent invocations can add to it.
6687 */
6688 if (shown == 0)
6689 bic_enabled = bic_lookup(optarg, SHOW_LIST);
6690 else
6691 bic_enabled |= bic_lookup(optarg, SHOW_LIST);
6692 shown = 1;
6693 break;
6694 case 'S':
6695 summary_only++;
6696 break;
6697 case 'T':
6698 tj_max_override = atoi(optarg);
6699 break;
6700 case 'v':
6701 print_version();
6702 exit(0);
6703 break;
6704 }
6705 }
6706 }
6707
6708 int main(int argc, char **argv)
6709 {
6710 int fd, ret;
6711
6712 fd = open("/sys/fs/cgroup/cgroup.procs", O_WRONLY);
6713 if (fd < 0)
6714 goto skip_cgroup_setting;
6715
6716 ret = write(fd, "0\n", 2);
6717 if (ret == -1)
6718 perror("Can't update cgroup\n");
6719
6720 close(fd);
6721
6722 skip_cgroup_setting:
6723 outf = stderr;
6724 cmdline(argc, argv);
6725
6726 if (!quiet) {
6727 print_version();
6728 print_bootcmd();
6729 }
6730
6731 probe_sysfs();
6732
6733 turbostat_init();
6734
6735 msr_sum_record();
6736
6737 /* dump counters and exit */
6738 if (dump_only)
6739 return get_and_dump_counters();
6740
6741 /* list header and exit */
6742 if (list_header_only) {
6743 print_header(",");
6744 flush_output_stdout();
6745 return 0;
6746 }
6747
6748 /*
6749 * if any params left, it must be a command to fork
6750 */
6751 if (argc - optind)
6752 return fork_it(argv + optind);
6753 else
6754 turbostat_loop();
6755
6756 return 0;
6757 }
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git