1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Andes Technology
4 * Chih-Mao Chen <cmchen@andestech.com>
6 * Statically process runtime relocations on RISC-V ELF images
7 * so that it can be directly executed when loaded at LMA
8 * without fixup. Both RV32 and RV64 are supported.
11 #define CONCAT_IMPL(x, y) x##y
12 #define CONCAT(x, y) CONCAT_IMPL(x, y)
13 #define CONCAT3(x, y, z) CONCAT(CONCAT(x, y), z)
15 #define prelink_bonn CONCAT3(prelink_, PRELINK_BYTEORDER, PRELINK_INC_BITS)
16 #define uintnn_t CONCAT3(uint, PRELINK_INC_BITS, _t)
17 #define get_offset_bonn CONCAT3(get_offset_, PRELINK_BYTEORDER, PRELINK_INC_BITS)
18 #define Elf_Ehdr CONCAT3(Elf, PRELINK_INC_BITS, _Ehdr)
19 #define Elf_Phdr CONCAT3(Elf, PRELINK_INC_BITS, _Phdr)
20 #define Elf_Rela CONCAT3(Elf, PRELINK_INC_BITS, _Rela)
21 #define Elf_Sym CONCAT3(Elf, PRELINK_INC_BITS, _Sym)
22 #define Elf_Dyn CONCAT3(Elf, PRELINK_INC_BITS, _Dyn)
23 #define Elf_Addr CONCAT3(Elf, PRELINK_INC_BITS, _Addr)
24 #define ELF_R_TYPE CONCAT3(ELF, PRELINK_INC_BITS, _R_TYPE)
25 #define ELF_R_SYM CONCAT3(ELF, PRELINK_INC_BITS, _R_SYM)
26 #define target16_to_cpu CONCAT(PRELINK_BYTEORDER, 16_to_cpu)
27 #define target32_to_cpu CONCAT(PRELINK_BYTEORDER, 32_to_cpu)
28 #define target64_to_cpu CONCAT(PRELINK_BYTEORDER, 64_to_cpu)
29 #define targetnn_to_cpu CONCAT3(PRELINK_BYTEORDER, PRELINK_INC_BITS, _to_cpu)
31 static void* get_offset_bonn (void* data, Elf_Phdr* phdrs, size_t phnum, Elf_Addr addr)
35 for (p = phdrs; p < phdrs + phnum; ++p)
36 if (targetnn_to_cpu(p->p_vaddr) <= addr && targetnn_to_cpu(p->p_vaddr) + targetnn_to_cpu(p->p_memsz) > addr)
37 return data + targetnn_to_cpu(p->p_offset) + (addr - targetnn_to_cpu(p->p_vaddr));
42 static void prelink_bonn(void *data)
44 Elf_Ehdr *ehdr = data;
49 if (target16_to_cpu(ehdr->e_machine) != EM_RISCV)
50 die("Machine type is not RISC-V");
52 Elf_Phdr *phdrs = data + targetnn_to_cpu(ehdr->e_phoff);
55 for (p = phdrs; p < phdrs + target16_to_cpu(ehdr->e_phnum); ++p) {
56 if (target32_to_cpu(p->p_type) == PT_DYNAMIC) {
57 dyns = data + targetnn_to_cpu(p->p_offset);
63 die("No dynamic section found");
65 Elf_Rela *rela_dyn = NULL;
66 size_t rela_count = 0;
67 Elf_Sym *dynsym = NULL;
68 for (dyn = dyns;; ++dyn) {
69 if (targetnn_to_cpu(dyn->d_tag) == DT_NULL)
71 else if (targetnn_to_cpu(dyn->d_tag) == DT_RELA)
72 rela_dyn = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), + targetnn_to_cpu(dyn->d_un.d_ptr));
73 else if (targetnn_to_cpu(dyn->d_tag) == DT_RELASZ)
74 rela_count = targetnn_to_cpu(dyn->d_un.d_val) / sizeof(Elf_Rela);
75 else if (targetnn_to_cpu(dyn->d_tag) == DT_SYMTAB)
76 dynsym = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), + targetnn_to_cpu(dyn->d_un.d_ptr));
81 die("No .rela.dyn found");
84 die("No .dynsym found");
86 for (r = rela_dyn; r < rela_dyn + rela_count; ++r) {
87 void* buf = get_offset_bonn(data, phdrs, target16_to_cpu(ehdr->e_phnum), targetnn_to_cpu(r->r_offset));
92 if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_RELATIVE)
93 *((uintnn_t*) buf) = r->r_addend;
94 else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_32)
95 *((uint32_t*) buf) = dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value;
96 else if (ELF_R_TYPE(targetnn_to_cpu(r->r_info)) == R_RISCV_64)
97 *((uint64_t*) buf) = dynsym[ELF_R_SYM(targetnn_to_cpu(r->r_info))].st_value;
103 #undef get_offset_bonn
112 #undef target16_to_cpu
113 #undef target32_to_cpu
114 #undef target64_to_cpu
115 #undef targetnn_to_cpu