git.ipfire.org Git - thirdparty/kernel/stable-queue.git/blob

   1 From 60d53566100abde4acc5504b524bc97f89015690 Mon Sep 17 00:00:00 2001
   2 From: Adrian Hunter <adrian.hunter@intel.com>
   3 Date: Thu, 12 Nov 2020 15:36:56 +0200
   4 Subject: mmc: sdhci-pci: Prefer SDR25 timing for High Speed mode for BYT-based Intel controllers
   5
   6 From: Adrian Hunter <adrian.hunter@intel.com>
   7
   8 commit 60d53566100abde4acc5504b524bc97f89015690 upstream.
   9
  10 A UHS setting of SDR25 can give better results for High Speed mode.
  11 This is because there is no setting corresponding to high speed.  Currently
  12 SDHCI sets no value, which means zero which is also the setting for SDR12.
  13 There was an attempt to change this in sdhci.c but it caused problems for
  14 some drivers, so it was reverted and the change was made to sdhci-brcmstb
  15 in commit 2fefc7c5f7d16e ("mmc: sdhci-brcmstb: Fix incorrect switch to HS
  16 mode").  Several other drivers also do this.
  17
  18 Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
  19 Cc: stable@vger.kernel.org # v5.4+
  20 Link: https://lore.kernel.org/r/20201112133656.20317-1-adrian.hunter@intel.com
  21 Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
  22 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  23
  24 ---
  25  drivers/mmc/host/sdhci-pci-core.c |   13 +++++++++++--
  26  1 file changed, 11 insertions(+), 2 deletions(-)
  27
  28 --- a/drivers/mmc/host/sdhci-pci-core.c
  29 +++ b/drivers/mmc/host/sdhci-pci-core.c
  30 @@ -665,6 +665,15 @@ static void sdhci_intel_set_power(struct
  31         }
  32  }
  33
  34 +static void sdhci_intel_set_uhs_signaling(struct sdhci_host *host,
  35 +                                         unsigned int timing)
  36 +{
  37 +       /* Set UHS timing to SDR25 for High Speed mode */
  38 +       if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS)
  39 +               timing = MMC_TIMING_UHS_SDR25;
  40 +       sdhci_set_uhs_signaling(host, timing);
  41 +}
  42 +
  43  #define INTEL_HS400_ES_REG 0x78
  44  #define INTEL_HS400_ES_BIT BIT(0)
  45
  46 @@ -721,7 +730,7 @@ static const struct sdhci_ops sdhci_inte
  47         .enable_dma             = sdhci_pci_enable_dma,
  48         .set_bus_width          = sdhci_set_bus_width,
  49         .reset                  = sdhci_reset,
  50 -       .set_uhs_signaling      = sdhci_set_uhs_signaling,
  51 +       .set_uhs_signaling      = sdhci_intel_set_uhs_signaling,
  52         .hw_reset               = sdhci_pci_hw_reset,
  53  };
  54
  55 @@ -731,7 +740,7 @@ static const struct sdhci_ops sdhci_inte
  56         .enable_dma             = sdhci_pci_enable_dma,
  57         .set_bus_width          = sdhci_set_bus_width,
  58         .reset                  = sdhci_cqhci_reset,
  59 -       .set_uhs_signaling      = sdhci_set_uhs_signaling,
  60 +       .set_uhs_signaling      = sdhci_intel_set_uhs_signaling,
  61         .hw_reset               = sdhci_pci_hw_reset,
  62         .irq                    = sdhci_cqhci_irq,
  63  };