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1 From e75d18cecbb3805895d8ed64da4f78575ec96043 Mon Sep 17 00:00:00 2001
2 From: Sudeep Holla <sudeep.holla@arm.com>
3 Date: Mon, 8 Aug 2022 09:46:40 +0100
4 Subject: arm64: cacheinfo: Fix incorrect assignment of signed error value to unsigned fw_level
5
6 From: Sudeep Holla <sudeep.holla@arm.com>
7
8 commit e75d18cecbb3805895d8ed64da4f78575ec96043 upstream.
9
10 Though acpi_find_last_cache_level() always returned signed value and the
11 document states it will return any errors caused by lack of a PPTT table,
12 it never returned negative values before.
13
14 Commit 0c80f9e165f8 ("ACPI: PPTT: Leave the table mapped for the runtime usage")
15 however changed it by returning -ENOENT if no PPTT was found. The value
16 returned from acpi_find_last_cache_level() is then assigned to unsigned
17 fw_level.
18
19 It will result in the number of cache leaves calculated incorrectly as
20 a huge value which will then cause the following warning from __alloc_pages
21 as the order would be great than MAX_ORDER because of incorrect and huge
22 cache leaves value.
23
24 | WARNING: CPU: 0 PID: 1 at mm/page_alloc.c:5407 __alloc_pages+0x74/0x314
25 | Modules linked in:
26 | CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.19.0-10393-g7c2a8d3ac4c0 #73
27 | pstate: 20000005 (nzCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
28 | pc : __alloc_pages+0x74/0x314
29 | lr : alloc_pages+0xe8/0x318
30 | Call trace:
31 | __alloc_pages+0x74/0x314
32 | alloc_pages+0xe8/0x318
33 | kmalloc_order_trace+0x68/0x1dc
34 | __kmalloc+0x240/0x338
35 | detect_cache_attributes+0xe0/0x56c
36 | update_siblings_masks+0x38/0x284
37 | store_cpu_topology+0x78/0x84
38 | smp_prepare_cpus+0x48/0x134
39 | kernel_init_freeable+0xc4/0x14c
40 | kernel_init+0x2c/0x1b4
41 | ret_from_fork+0x10/0x20
42
43 Fix the same by changing fw_level to be signed integer and return the
44 error from init_cache_level() early in case of error.
45
46 Reported-and-Tested-by: Bruno Goncalves <bgoncalv@redhat.com>
47 Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
48 Link: https://lore.kernel.org/r/20220808084640.3165368-1-sudeep.holla@arm.com
49 Signed-off-by: Will Deacon <will@kernel.org>
50 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
51 ---
52 arch/arm64/kernel/cacheinfo.c | 6 +++++-
53 1 file changed, 5 insertions(+), 1 deletion(-)
54
55 --- a/arch/arm64/kernel/cacheinfo.c
56 +++ b/arch/arm64/kernel/cacheinfo.c
57 @@ -45,7 +45,8 @@ static void ci_leaf_init(struct cacheinf
58
59 int init_cache_level(unsigned int cpu)
60 {
61 - unsigned int ctype, level, leaves, fw_level;
62 + unsigned int ctype, level, leaves;
63 + int fw_level;
64 struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
65
66 for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) {
67 @@ -63,6 +64,9 @@ int init_cache_level(unsigned int cpu)
68 else
69 fw_level = acpi_find_last_cache_level(cpu);
70
71 + if (fw_level < 0)
72 + return fw_level;
73 +
74 if (level < fw_level) {
75 /*
76 * some external caches not specified in CLIDR_EL1