git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From db7a4a11e8be375b0a9c159f688e0cea49eacc5d Mon Sep 17 00:00:00 2001
   2 From: Lorenzo Bianconi <lorenzo@kernel.org>
   3 Date: Thu, 27 Jun 2024 13:04:24 +0200
   4 Subject: [PATCH 2/4] clk: en7523: Remove pcie prepare/unpreare callbacks for
   5  EN7581 SoC
   6
   7 Get rid of prepare and unpreare callbacks for PCIe clock since they can
   8 be modeled as a reset line cosumed by the PCIe driver
   9 (pcie-mediatek-gen3)
  10
  11 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  12 Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
  13 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  14 Link: https://lore.kernel.org/r/16df149975514d3030499c48fc1c64f090093595.1719485847.git.lorenzo@kernel.org
  15 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  16 ---
  17  drivers/clk/clk-en7523.c | 41 ++--------------------------------------
  18  1 file changed, 2 insertions(+), 39 deletions(-)
  19
  20 --- a/drivers/clk/clk-en7523.c
  21 +++ b/drivers/clk/clk-en7523.c
  22 @@ -366,9 +366,8 @@ static struct clk_hw *en7523_register_pc
  23         cg->base = np_base;
  24         cg->hw.init = &init;
  25
  26 -       if (init.ops->disable)
  27 -               init.ops->disable(&cg->hw);
  28 -       init.ops->unprepare(&cg->hw);
  29 +       if (init.ops->unprepare)
  30 +               init.ops->unprepare(&cg->hw);
  31
  32         if (clk_hw_register(dev, &cg->hw))
  33                 return NULL;
  34 @@ -386,23 +385,6 @@ static int en7581_pci_is_enabled(struct
  35         return (val & mask) == mask;
  36  }
  37
  38 -static int en7581_pci_prepare(struct clk_hw *hw)
  39 -{
  40 -       struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
  41 -       void __iomem *np_base = cg->base;
  42 -       u32 val, mask;
  43 -
  44 -       mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
  45 -              REG_RESET_CONTROL_PCIEHB;
  46 -       val = readl(np_base + REG_RESET_CONTROL1);
  47 -       writel(val & ~mask, np_base + REG_RESET_CONTROL1);
  48 -       val = readl(np_base + REG_RESET_CONTROL2);
  49 -       writel(val & ~REG_RESET2_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2);
  50 -       usleep_range(5000, 10000);
  51 -
  52 -       return 0;
  53 -}
  54 -
  55  static int en7581_pci_enable(struct clk_hw *hw)
  56  {
  57         struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
  58 @@ -419,23 +401,6 @@ static int en7581_pci_enable(struct clk_
  59         return 0;
  60  }
  61
  62 -static void en7581_pci_unprepare(struct clk_hw *hw)
  63 -{
  64 -       struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
  65 -       void __iomem *np_base = cg->base;
  66 -       u32 val, mask;
  67 -
  68 -       mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
  69 -              REG_RESET_CONTROL_PCIEHB;
  70 -       val = readl(np_base + REG_RESET_CONTROL1);
  71 -       writel(val | mask, np_base + REG_RESET_CONTROL1);
  72 -       mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2;
  73 -       writel(val | mask, np_base + REG_RESET_CONTROL1);
  74 -       val = readl(np_base + REG_RESET_CONTROL2);
  75 -       writel(val | REG_RESET_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2);
  76 -       msleep(100);
  77 -}
  78 -
  79  static void en7581_pci_disable(struct clk_hw *hw)
  80  {
  81         struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
  82 @@ -656,9 +621,7 @@ static const struct en_clk_soc_data en75
  83  static const struct en_clk_soc_data en7581_data = {
  84         .pcie_ops = {
  85                 .is_enabled = en7581_pci_is_enabled,
  86 -               .prepare = en7581_pci_prepare,
  87                 .enable = en7581_pci_enable,
  88 -               .unprepare = en7581_pci_unprepare,
  89                 .disable = en7581_pci_disable,
  90         },
  91         .reset = {