git.ipfire.org Git - thirdparty/kernel/stable-queue.git/blob

   1 From 10b74af310735860510a533433b1d3ab2e05a138 Mon Sep 17 00:00:00 2001
   2 From: Quentin Schulz <quentin.schulz@theobroma-systems.com>
   3 Date: Mon, 31 Jan 2022 17:32:24 +0100
   4 Subject: clk: rockchip: re-add rational best approximation algorithm to the fractional divider
   5
   6 From: Quentin Schulz <quentin.schulz@theobroma-systems.com>
   7
   8 commit 10b74af310735860510a533433b1d3ab2e05a138 upstream.
   9
  10 In commit 4e7cf74fa3b2 ("clk: fractional-divider: Export approximation
  11 algorithm to the CCF users"), the code handling the rational best
  12 approximation algorithm was replaced by a call to the core
  13 clk_fractional_divider_general_approximation function which did the same
  14 thing back then.
  15
  16 However, in commit 82f53f9ee577 ("clk: fractional-divider: Introduce
  17 POWER_OF_TWO_PS flag"), this common code was made conditional on
  18 CLK_FRAC_DIVIDER_POWER_OF_TWO_PS flag which was not added back to the
  19 rockchip clock driver.
  20
  21 This broke the ltk050h3146w-a2 MIPI DSI display present on a PX30-based
  22 downstream board.
  23
  24 Let's add the flag to the fractional divider flags so that the original
  25 and intended behavior is brought back to the rockchip clock drivers.
  26
  27 Fixes: 82f53f9ee577 ("clk: fractional-divider: Introduce POWER_OF_TWO_PS flag")
  28 Cc: stable@vger.kernel.org
  29 Cc: Quentin Schulz <foss+kernel@0leil.net>
  30 Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
  31 Link: https://lore.kernel.org/r/20220131163224.708002-1-quentin.schulz@theobroma-systems.com
  32 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  33 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  34 ---
  35  drivers/clk/rockchip/clk.c |    3 +++
  36  1 file changed, 3 insertions(+)
  37
  38 --- a/drivers/clk/rockchip/clk.c
  39 +++ b/drivers/clk/rockchip/clk.c
  40 @@ -180,6 +180,7 @@ static void rockchip_fractional_approxim
  41                 unsigned long rate, unsigned long *parent_rate,
  42                 unsigned long *m, unsigned long *n)
  43  {
  44 +       struct clk_fractional_divider *fd = to_clk_fd(hw);
  45         unsigned long p_rate, p_parent_rate;
  46         struct clk_hw *p_parent;
  47
  48 @@ -190,6 +191,8 @@ static void rockchip_fractional_approxim
  49                 *parent_rate = p_parent_rate;
  50         }
  51
  52 +       fd->flags |= CLK_FRAC_DIVIDER_POWER_OF_TWO_PS;
  53 +
  54         clk_fractional_divider_general_approximation(hw, rate, parent_rate, m, n);
  55  }
  56