git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From 82e6bf912d5846646892becea659b39d178d79e3 Mon Sep 17 00:00:00 2001
   2 From: Lorenzo Bianconi <lorenzo@kernel.org>
   3 Date: Tue, 12 Nov 2024 01:08:53 +0100
   4 Subject: [PATCH 5/6] clk: en7523: move en7581_reset_register() in
   5  en7581_clk_hw_init()
   6
   7 Move en7581_reset_register routine in en7581_clk_hw_init() since reset
   8 feature is supported just by EN7581 SoC.
   9 Get rid of reset struct in en_clk_soc_data data struct.
  10
  11 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  12 Link: https://lore.kernel.org/r/20241112-clk-en7581-syscon-v2-6-8ada5e394ae4@kernel.org
  13 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  14 ---
  15  drivers/clk/clk-en7523.c | 93 ++++++++++++++--------------------------
  16  1 file changed, 33 insertions(+), 60 deletions(-)
  17
  18 --- a/drivers/clk/clk-en7523.c
  19 +++ b/drivers/clk/clk-en7523.c
  20 @@ -76,11 +76,6 @@ struct en_rst_data {
  21
  22  struct en_clk_soc_data {
  23         const struct clk_ops pcie_ops;
  24 -       struct {
  25 -               const u16 *bank_ofs;
  26 -               const u16 *idx_map;
  27 -               u16 idx_map_nr;
  28 -       } reset;
  29         int (*hw_init)(struct platform_device *pdev,
  30                        struct clk_hw_onecell_data *clk_data);
  31  };
  32 @@ -595,32 +590,6 @@ static void en7581_register_clocks(struc
  33         clk_data->num = EN7523_NUM_CLOCKS;
  34  }
  35
  36 -static int en7581_clk_hw_init(struct platform_device *pdev,
  37 -                             struct clk_hw_onecell_data *clk_data)
  38 -{
  39 -       void __iomem *np_base;
  40 -       struct regmap *map;
  41 -       u32 val;
  42 -
  43 -       map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu");
  44 -       if (IS_ERR(map))
  45 -               return PTR_ERR(map);
  46 -
  47 -       np_base = devm_platform_ioremap_resource(pdev, 0);
  48 -       if (IS_ERR(np_base))
  49 -               return PTR_ERR(np_base);
  50 -
  51 -       en7581_register_clocks(&pdev->dev, clk_data, map, np_base);
  52 -
  53 -       val = readl(np_base + REG_NP_SCU_SSTR);
  54 -       val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK);
  55 -       writel(val, np_base + REG_NP_SCU_SSTR);
  56 -       val = readl(np_base + REG_NP_SCU_PCIC);
  57 -       writel(val | 3, np_base + REG_NP_SCU_PCIC);
  58 -
  59 -       return 0;
  60 -}
  61 -
  62  static int en7523_reset_update(struct reset_controller_dev *rcdev,
  63                                unsigned long id, bool assert)
  64  {
  65 @@ -670,23 +639,18 @@ static int en7523_reset_xlate(struct res
  66         return rst_data->idx_map[reset_spec->args[0]];
  67  }
  68
  69 -static const struct reset_control_ops en7523_reset_ops = {
  70 +static const struct reset_control_ops en7581_reset_ops = {
  71         .assert = en7523_reset_assert,
  72         .deassert = en7523_reset_deassert,
  73         .status = en7523_reset_status,
  74  };
  75
  76 -static int en7523_reset_register(struct platform_device *pdev,
  77 -                                const struct en_clk_soc_data *soc_data)
  78 +static int en7581_reset_register(struct platform_device *pdev)
  79  {
  80         struct device *dev = &pdev->dev;
  81         struct en_rst_data *rst_data;
  82         void __iomem *base;
  83
  84 -       /* no reset lines available */
  85 -       if (!soc_data->reset.idx_map_nr)
  86 -               return 0;
  87 -
  88         base = devm_platform_ioremap_resource(pdev, 1);
  89         if (IS_ERR(base))
  90                 return PTR_ERR(base);
  91 @@ -695,13 +659,13 @@ static int en7523_reset_register(struct
  92         if (!rst_data)
  93                 return -ENOMEM;
  94
  95 -       rst_data->bank_ofs = soc_data->reset.bank_ofs;
  96 -       rst_data->idx_map = soc_data->reset.idx_map;
  97 +       rst_data->bank_ofs = en7581_rst_ofs;
  98 +       rst_data->idx_map = en7581_rst_map;
  99         rst_data->base = base;
 100
 101 -       rst_data->rcdev.nr_resets = soc_data->reset.idx_map_nr;
 102 +       rst_data->rcdev.nr_resets = ARRAY_SIZE(en7581_rst_map);
 103         rst_data->rcdev.of_xlate = en7523_reset_xlate;
 104 -       rst_data->rcdev.ops = &en7523_reset_ops;
 105 +       rst_data->rcdev.ops = &en7581_reset_ops;
 106         rst_data->rcdev.of_node = dev->of_node;
 107         rst_data->rcdev.of_reset_n_cells = 1;
 108         rst_data->rcdev.owner = THIS_MODULE;
 109 @@ -710,6 +674,32 @@ static int en7523_reset_register(struct
 110         return devm_reset_controller_register(dev, &rst_data->rcdev);
 111  }
 112
 113 +static int en7581_clk_hw_init(struct platform_device *pdev,
 114 +                             struct clk_hw_onecell_data *clk_data)
 115 +{
 116 +       void __iomem *np_base;
 117 +       struct regmap *map;
 118 +       u32 val;
 119 +
 120 +       map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu");
 121 +       if (IS_ERR(map))
 122 +               return PTR_ERR(map);
 123 +
 124 +       np_base = devm_platform_ioremap_resource(pdev, 0);
 125 +       if (IS_ERR(np_base))
 126 +               return PTR_ERR(np_base);
 127 +
 128 +       en7581_register_clocks(&pdev->dev, clk_data, map, np_base);
 129 +
 130 +       val = readl(np_base + REG_NP_SCU_SSTR);
 131 +       val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK);
 132 +       writel(val, np_base + REG_NP_SCU_SSTR);
 133 +       val = readl(np_base + REG_NP_SCU_PCIC);
 134 +       writel(val | 3, np_base + REG_NP_SCU_PCIC);
 135 +
 136 +       return en7581_reset_register(pdev);
 137 +}
 138 +
 139  static int en7523_clk_probe(struct platform_device *pdev)
 140  {
 141         struct device_node *node = pdev->dev.of_node;
 142 @@ -728,19 +718,7 @@ static int en7523_clk_probe(struct platf
 143         if (r)
 144                 return r;
 145
 146 -       r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 147 -       if (r)
 148 -               return dev_err_probe(&pdev->dev, r, "Could not register clock provider: %s\n",
 149 -                                    pdev->name);
 150 -
 151 -       r = en7523_reset_register(pdev, soc_data);
 152 -       if (r) {
 153 -               of_clk_del_provider(node);
 154 -               return dev_err_probe(&pdev->dev, r, "Could not register reset controller: %s\n",
 155 -                                    pdev->name);
 156 -       }
 157 -
 158 -       return 0;
 159 +       return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 160  }
 161
 162  static const struct en_clk_soc_data en7523_data = {
 163 @@ -758,11 +736,6 @@ static const struct en_clk_soc_data en75
 164                 .enable = en7581_pci_enable,
 165                 .disable = en7581_pci_disable,
 166         },
 167 -       .reset = {
 168 -               .bank_ofs = en7581_rst_ofs,
 169 -               .idx_map = en7581_rst_map,
 170 -               .idx_map_nr = ARRAY_SIZE(en7581_rst_map),
 171 -       },
 172         .hw_init = en7581_clk_hw_init,
 173  };
 174