git.ipfire.org Git - thirdparty/kernel/stable-queue.git/blob

   1 rom bb98e72adaf9d19719aba35f802d4836f5d5176c Mon Sep 17 00:00:00 2001
   2 From: Hans de Goede <hdegoede@redhat.com>
   3 Date: Fri, 2 Dec 2016 15:29:04 +0100
   4 Subject: drm/i915/dsi: Do not clear DPOUNIT_CLOCK_GATE_DISABLE from vlv_init_display_clock_gating
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   8
   9 From: Hans de Goede <hdegoede@redhat.com>
  10
  11 commit bb98e72adaf9d19719aba35f802d4836f5d5176c upstream.
  12
  13 On my Cherrytrail CUBE iwork8 Air tablet PIPE-A would get stuck on loading
  14 i915 at boot 1 out of every 3 boots, resulting in a non functional LCD.
  15 Once the i915 driver has successfully loaded, the panel can be disabled /
  16 enabled without hitting this issue.
  17
  18 The getting stuck is caused by vlv_init_display_clock_gating() clearing
  19 the DPOUNIT_CLOCK_GATE_DISABLE bit in DSPCLK_GATE_D when called from
  20 chv_pipe_power_well_ops.enable() on driver load, while a pipe is enabled
  21 driving the DSI LCD by the BIOS.
  22
  23 Clearing this bit while DSI is in use is a known issue and
  24 intel_dsi_pre_enable() / intel_dsi_post_disable() already set / clear it
  25 as appropriate.
  26
  27 This commit modifies vlv_init_display_clock_gating() to leave the
  28 DPOUNIT_CLOCK_GATE_DISABLE bit alone fixing the pipe getting stuck.
  29
  30 Changes in v2:
  31 -Replace PIPE-A with "a pipe" or "the pipe" in the commit msg and
  32 comment
  33
  34 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97330
  35 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
  36 Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
  37 Link: http://patchwork.freedesktop.org/patch/msgid/20161202142904.25613-1-hdegoede@redhat.com
  38 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
  39 (cherry picked from commit 721d484563e1a51ada760089c490cbc47e909756)
  40 Signed-off-by: Jani Nikula <jani.nikula@intel.com>
  41 Signed-off-by: River Zhou <riverzhou2000@163.com>
  42 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  43 ---
  44  drivers/gpu/drm/i915/intel_pm.c |   13 ++++++++++++-
  45  1 file changed, 12 insertions(+), 1 deletion(-)
  46
  47 --- a/drivers/gpu/drm/i915/intel_pm.c
  48 +++ b/drivers/gpu/drm/i915/intel_pm.c
  49 @@ -6803,7 +6803,18 @@ static void ivybridge_init_clock_gating(
  50
  51  static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
  52  {
  53 -       I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
  54 +        u32 val;
  55 +
  56 +        /*
  57 +        * On driver load, a pipe may be active and driving a DSI display.
  58 +        * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck
  59 +        * (and never recovering) in this case. intel_dsi_post_disable() will
  60 +        * clear it when we turn off the display.
  61 +        */
  62 +        val = I915_READ(DSPCLK_GATE_D);
  63 +        val &= DPOUNIT_CLOCK_GATE_DISABLE;
  64 +        val |= VRHUNIT_CLOCK_GATE_DISABLE;
  65 +        I915_WRITE(DSPCLK_GATE_D, val);
  66
  67         /*
  68          * Disable trickle feed and enable pnd deadline calculation