git.ipfire.org Git - thirdparty/kernel/stable-queue.git/blob

   1 From 7fa981cad216e9f64f49e22112f610c0bfed91bc Mon Sep 17 00:00:00 2001
   2 From: Kan Liang <kan.liang@linux.intel.com>
   3 Date: Tue, 11 Jan 2022 10:20:38 -0800
   4 Subject: perf/x86/intel: Add a quirk for the calculation of the number of counters on Alder Lake
   5
   6 From: Kan Liang <kan.liang@linux.intel.com>
   7
   8 commit 7fa981cad216e9f64f49e22112f610c0bfed91bc upstream.
   9
  10 For some Alder Lake machine with all E-cores disabled in a BIOS, the
  11 below warning may be triggered.
  12
  13 [ 2.010766] hw perf events fixed 5 > max(4), clipping!
  14
  15 Current perf code relies on the CPUID leaf 0xA and leaf 7.EDX[15] to
  16 calculate the number of the counters and follow the below assumption.
  17
  18 For a hybrid configuration, the leaf 7.EDX[15] (X86_FEATURE_HYBRID_CPU)
  19 is set. The leaf 0xA only enumerate the common counters. Linux perf has
  20 to manually add the extra GP counters and fixed counters for P-cores.
  21 For a non-hybrid configuration, the X86_FEATURE_HYBRID_CPU should not
  22 be set. The leaf 0xA enumerates all counters.
  23
  24 However, that's not the case when all E-cores are disabled in a BIOS.
  25 Although there are only P-cores in the system, the leaf 7.EDX[15]
  26 (X86_FEATURE_HYBRID_CPU) is still set. But the leaf 0xA is updated
  27 to enumerate all counters of P-cores. The inconsistency triggers the
  28 warning.
  29
  30 Several software ways were considered to handle the inconsistency.
  31 - Drop the leaf 0xA and leaf 7.EDX[15] CPUID enumeration support.
  32   Hardcode the number of counters. This solution may be a problem for
  33   virtualization. A hypervisor cannot control the number of counters
  34   in a Linux guest via changing the guest CPUID enumeration anymore.
  35 - Find another CPUID bit that is also updated with E-cores disabled.
  36   There may be a problem in the virtualization environment too. Because
  37   a hypervisor may disable the feature/CPUID bit.
  38 - The P-cores have a maximum of 8 GP counters and 4 fixed counters on
  39   ADL. The maximum number can be used to detect the case.
  40   This solution is implemented in this patch.
  41
  42 Fixes: ee72a94ea4a6 ("perf/x86/intel: Fix fixed counter check warning for some Alder Lake")
  43 Reported-by: Damjan Marion (damarion) <damarion@cisco.com>
  44 Reported-by: Chan Edison <edison_chan_gz@hotmail.com>
  45 Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
  46 Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
  47 Tested-by: Damjan Marion (damarion) <damarion@cisco.com>
  48 Cc: stable@vger.kernel.org
  49 Link: https://lkml.kernel.org/r/1641925238-149288-1-git-send-email-kan.liang@linux.intel.com
  50 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  51 ---
  52  arch/x86/events/intel/core.c |   13 +++++++++++++
  53  1 file changed, 13 insertions(+)
  54
  55 --- a/arch/x86/events/intel/core.c
  56 +++ b/arch/x86/events/intel/core.c
  57 @@ -6242,6 +6242,19 @@ __init int intel_pmu_init(void)
  58                         pmu->num_counters = x86_pmu.num_counters;
  59                         pmu->num_counters_fixed = x86_pmu.num_counters_fixed;
  60                 }
  61 +
  62 +               /*
  63 +                * Quirk: For some Alder Lake machine, when all E-cores are disabled in
  64 +                * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However,
  65 +                * the X86_FEATURE_HYBRID_CPU is still set. The above codes will
  66 +                * mistakenly add extra counters for P-cores. Correct the number of
  67 +                * counters here.
  68 +                */
  69 +               if ((pmu->num_counters > 8) || (pmu->num_counters_fixed > 4)) {
  70 +                       pmu->num_counters = x86_pmu.num_counters;
  71 +                       pmu->num_counters_fixed = x86_pmu.num_counters_fixed;
  72 +               }
  73 +
  74                 pmu->max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, pmu->num_counters);
  75                 pmu->unconstrained = (struct event_constraint)
  76                                         __EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1,