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1 From 9f8ccdb5088bd03062d9ad9c0f6abf600cbed8e8 Mon Sep 17 00:00:00 2001
2 From: Vadim Pasternak <vadimp@nvidia.com>
3 Date: Sun, 13 Aug 2023 08:37:34 +0000
4 Subject: platform: mellanox: mlx-platform: Modify graceful shutdown callback and power down mask
5
6 From: Vadim Pasternak <vadimp@nvidia.com>
7
8 commit 9f8ccdb5088bd03062d9ad9c0f6abf600cbed8e8 upstream.
9
10 Use kernel_power_off() instead of kernel_halt() to pass through
11 machine_power_off() -> pm_power_off(), otherwise axillary power does
12 not go off.
13
14 Change "power down" bitmask.
15
16 Fixes: dd635e33b5c9 ("platform: mellanox: Introduce support of new Nvidia L1 switch")
17 Signed-off-by: Vadim Pasternak <vadimp@nvidia.com>
18 Reviewed-by: Michael Shych <michaelsh@nvidia.com>
19 Link: https://lore.kernel.org/r/20230813083735.39090-4-vadimp@nvidia.com
20 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
21 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
22 ---
23 drivers/platform/x86/mlx-platform.c | 4 ++--
24 1 file changed, 2 insertions(+), 2 deletions(-)
25
26 --- a/drivers/platform/x86/mlx-platform.c
27 +++ b/drivers/platform/x86/mlx-platform.c
28 @@ -222,7 +222,7 @@
29 MLXPLAT_CPLD_AGGR_MASK_LC_SDWN)
30 #define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1
31 #define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2 BIT(2)
32 -#define MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT BIT(4)
33 +#define MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT GENMASK(5, 4)
34 #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6)
35 #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0)
36 #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0)
37 @@ -2356,7 +2356,7 @@ mlxplat_mlxcpld_l1_switch_pwr_events_han
38 u8 action)
39 {
40 dev_info(&mlxplat_dev->dev, "System shutdown due to short press of power button");
41 - kernel_halt();
42 + kernel_power_off();
43 return 0;
44 }
45