git.ipfire.org Git - thirdparty/kernel/stable-queue.git/blob

   1 From 69a46ce1f15b4391c128d581f6936750f9bfa052 Mon Sep 17 00:00:00 2001
   2 From: Tom Chung <chiahsuan.chung@amd.com>
   3 Date: Wed, 19 Mar 2025 16:31:31 +0800
   4 Subject: drm/amd/display: Do not enable Replay and PSR while VRR is on in amdgpu_dm_commit_planes()
   5
   6 From: Tom Chung <chiahsuan.chung@amd.com>
   7
   8 commit 69a46ce1f15b4391c128d581f6936750f9bfa052 upstream.
   9
  10 [Why]
  11 Replay and PSR will cause some video corruption while VRR is enabled.
  12
  13 [How]
  14 Do not enable the Replay and PSR while VRR is active in
  15 amdgpu_dm_enable_self_refresh().
  16
  17 Fixes: 67edb81d6e9a ("drm/amd/display: Disable replay and psr while VRR is enabled")
  18 Reviewed-by: Sun peng Li <sunpeng.li@amd.com>
  19 Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
  20 Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
  21 Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
  22 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
  23 Cc: stable@vger.kernel.org
  24 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  25 ---
  26  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 6 ++++--
  27  1 file changed, 4 insertions(+), 2 deletions(-)
  28
  29 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
  30 index 36a830a7440f..87058271b00c 100644
  31 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
  32 +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
  33 @@ -113,6 +113,7 @@ bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state)
  34   *
  35   * Panel Replay and PSR SU
  36   * - Enable when:
  37 + *      - VRR is disabled
  38   *      - vblank counter is disabled
  39   *      - entry is allowed: usermode demonstrates an adequate number of fast
  40   *        commits)
  41 @@ -131,19 +132,20 @@ static void amdgpu_dm_crtc_set_panel_sr_feature(
  42         bool is_sr_active = (link->replay_settings.replay_allow_active ||
  43                                  link->psr_settings.psr_allow_active);
  44         bool is_crc_window_active = false;
  45 +       bool vrr_active = amdgpu_dm_crtc_vrr_active_irq(vblank_work->acrtc);
  46
  47  #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
  48         is_crc_window_active =
  49                 amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base);
  50  #endif
  51
  52 -       if (link->replay_settings.replay_feature_enabled &&
  53 +       if (link->replay_settings.replay_feature_enabled && !vrr_active &&
  54                 allow_sr_entry && !is_sr_active && !is_crc_window_active) {
  55                 amdgpu_dm_replay_enable(vblank_work->stream, true);
  56         } else if (vblank_enabled) {
  57                 if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active)
  58                         amdgpu_dm_psr_disable(vblank_work->stream, false);
  59 -       } else if (link->psr_settings.psr_feature_enabled &&
  60 +       } else if (link->psr_settings.psr_feature_enabled && !vrr_active &&
  61                 allow_sr_entry && !is_sr_active && !is_crc_window_active) {
  62
  63                 struct amdgpu_dm_connector *aconn =
  64 --
  65 2.49.0
  66