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   1 /*
   2  * Support for Intel Camera Imaging ISP subsystem.
   3  * Copyright (c) 2015, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #ifndef __ISYS_STREAM2MMIO_PRIVATE_H_INCLUDED__
  16 #define __ISYS_STREAM2MMIO_PRIVATE_H_INCLUDED__
  17
  18 #include "isys_stream2mmio_public.h"
  19 #include "device_access.h"      /* ia_css_device_load_uint32 */
  20 #include "assert_support.h"     /* assert */
  21 #include "print_support.h"      /* print */
  22
  23 #define STREAM2MMIO_COMMAND_REG_ID             0
  24 #define STREAM2MMIO_ACKNOWLEDGE_REG_ID         1
  25 #define STREAM2MMIO_PIX_WIDTH_ID_REG_ID        2
  26 #define STREAM2MMIO_START_ADDR_REG_ID          3      /* master port address,NOT Byte */
  27 #define STREAM2MMIO_END_ADDR_REG_ID            4      /* master port address,NOT Byte */
  28 #define STREAM2MMIO_STRIDE_REG_ID              5      /* stride in master port words, increment is per packet for long sids, stride is not used for short sid's*/
  29 #define STREAM2MMIO_NUM_ITEMS_REG_ID           6      /* number of packets for store packets cmd, number of words for store_words cmd */
  30 #define STREAM2MMIO_BLOCK_WHEN_NO_CMD_REG_ID   7      /* if this register is 1, input will be stalled if there is no pending command for this sid */
  31 #define STREAM2MMIO_REGS_PER_SID               8
  32
  33 /*****************************************************
  34  *
  35  * Native command interface (NCI).
  36  *
  37  *****************************************************/
  38 /**
  39  * @brief Get the stream2mmio-controller state.
  40  * Refer to "stream2mmio_public.h" for details.
  41  */
  42 STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_get_state(
  43                 const stream2mmio_ID_t ID,
  44                 stream2mmio_state_t *state)
  45 {
  46         stream2mmio_sid_ID_t i;
  47
  48         /*
  49          * Get the values of the register-set per
  50          * stream2mmio-controller sids.
  51          */
  52         for (i = STREAM2MMIO_SID0_ID; i < N_STREAM2MMIO_SID_PROCS[ID]; i++) {
  53                 stream2mmio_get_sid_state(ID, i, &state->sid_state[i]);
  54         }
  55 }
  56
  57 /**
  58  * @brief Get the state of the stream2mmio-controller sidess.
  59  * Refer to "stream2mmio_public.h" for details.
  60  */
  61 STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_get_sid_state(
  62                 const stream2mmio_ID_t ID,
  63                 const stream2mmio_sid_ID_t sid_id,
  64                 stream2mmio_sid_state_t *state)
  65 {
  66         state->rcv_ack =
  67                 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_ACKNOWLEDGE_REG_ID);
  68
  69         state->pix_width_id =
  70                 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_PIX_WIDTH_ID_REG_ID);
  71
  72         state->start_addr =
  73                 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_START_ADDR_REG_ID);
  74
  75         state->end_addr =
  76                 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_END_ADDR_REG_ID);
  77
  78         state->strides =
  79                 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_STRIDE_REG_ID);
  80
  81         state->num_items =
  82                 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_NUM_ITEMS_REG_ID);
  83
  84         state->block_when_no_cmd =
  85                 stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_BLOCK_WHEN_NO_CMD_REG_ID);
  86 }
  87
  88 /**
  89  * @brief Dump the state of the stream2mmio-controller sidess.
  90  * Refer to "stream2mmio_public.h" for details.
  91  */
  92 STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_print_sid_state(
  93                 stream2mmio_sid_state_t *state)
  94 {
  95         ia_css_print("\t \t Receive acks 0x%x\n", state->rcv_ack);
  96         ia_css_print("\t \t Pixel width 0x%x\n", state->pix_width_id);
  97         ia_css_print("\t \t Startaddr 0x%x\n", state->start_addr);
  98         ia_css_print("\t \t Endaddr 0x%x\n", state->end_addr);
  99         ia_css_print("\t \t Strides 0x%x\n", state->strides);
 100         ia_css_print("\t \t Num Items 0x%x\n", state->num_items);
 101         ia_css_print("\t \t block when no cmd 0x%x\n", state->block_when_no_cmd);
 102 }
 103
 104 /**
 105  * @brief Dump the ibuf-controller state.
 106  * Refer to "stream2mmio_public.h" for details.
 107  */
 108 STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_dump_state(
 109                 const stream2mmio_ID_t ID,
 110                 stream2mmio_state_t *state)
 111 {
 112         stream2mmio_sid_ID_t i;
 113
 114         /*
 115          * Get the values of the register-set per
 116          * stream2mmio-controller sids.
 117          */
 118         for (i = STREAM2MMIO_SID0_ID; i < N_STREAM2MMIO_SID_PROCS[ID]; i++) {
 119                 ia_css_print("StREAM2MMIO ID %d SID %d\n", ID, i);
 120                 stream2mmio_print_sid_state(&state->sid_state[i]);
 121         }
 122 }
 123
 124 /* end of NCI */
 125
 126 /*****************************************************
 127  *
 128  * Device level interface (DLI).
 129  *
 130  *****************************************************/
 131 /**
 132  * @brief Load the register value.
 133  * Refer to "stream2mmio_public.h" for details.
 134  */
 135 STORAGE_CLASS_STREAM2MMIO_C hrt_data stream2mmio_reg_load(
 136                 const stream2mmio_ID_t ID,
 137                 const stream2mmio_sid_ID_t sid_id,
 138                 const uint32_t reg_idx)
 139 {
 140         u32 reg_bank_offset;
 141
 142         assert(ID < N_STREAM2MMIO_ID);
 143
 144         reg_bank_offset = STREAM2MMIO_REGS_PER_SID * sid_id;
 145         return ia_css_device_load_uint32(STREAM2MMIO_CTRL_BASE[ID] +
 146                         (reg_bank_offset + reg_idx) * sizeof(hrt_data));
 147 }
 148
 149 /**
 150  * @brief Store a value to the register.
 151  * Refer to "stream2mmio_public.h" for details.
 152  */
 153 STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_reg_store(
 154                 const stream2mmio_ID_t ID,
 155                 const hrt_address reg,
 156                 const hrt_data value)
 157 {
 158         assert(ID < N_STREAM2MMIO_ID);
 159         assert(STREAM2MMIO_CTRL_BASE[ID] != (hrt_address)-1);
 160
 161         ia_css_device_store_uint32(STREAM2MMIO_CTRL_BASE[ID] +
 162                 reg * sizeof(hrt_data), value);
 163 }
 164
 165 /* end of DLI */
 166
 167 #endif /* __ISYS_STREAM2MMIO_PRIVATE_H_INCLUDED__ */