git.ipfire.org Git - thirdparty/openwrt.git/blob

   1 From f98eded9e9ab048c88ff59c5523e703a6ced5523 Mon Sep 17 00:00:00 2001
   2 From: Lorenzo Bianconi <lorenzo@kernel.org>
   3 Date: Tue, 12 Nov 2024 01:08:52 +0100
   4 Subject: [PATCH 4/6] clk: en7523: fix estimation of fixed rate for EN7581
   5
   6 Introduce en7581_base_clks array in order to define per-SoC fixed-rate
   7 clock parameters and fix wrong parameters for emi, npu and crypto EN7581
   8 clocks
   9
  10 Fixes: 66bc47326ce2 ("clk: en7523: Add EN7581 support")
  11 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  12 Link: https://lore.kernel.org/r/20241112-clk-en7581-syscon-v2-5-8ada5e394ae4@kernel.org
  13 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  14 ---
  15  drivers/clk/clk-en7523.c | 105 ++++++++++++++++++++++++++++++++++++++-
  16  1 file changed, 103 insertions(+), 2 deletions(-)
  17
  18 --- a/drivers/clk/clk-en7523.c
  19 +++ b/drivers/clk/clk-en7523.c
  20 @@ -37,6 +37,7 @@
  21  #define REG_NP_SCU_SSTR                        0x9c
  22  #define REG_PCIE_XSI0_SEL_MASK         GENMASK(14, 13)
  23  #define REG_PCIE_XSI1_SEL_MASK         GENMASK(12, 11)
  24 +#define REG_CRYPTO_CLKSRC2             0x20c
  25
  26  #define REG_RST_CTRL2                  0x00
  27  #define REG_RST_CTRL1                  0x04
  28 @@ -89,6 +90,10 @@ static const u32 emi_base[] = { 33300000
  29  static const u32 bus_base[] = { 500000000, 540000000 };
  30  static const u32 slic_base[] = { 100000000, 3125000 };
  31  static const u32 npu_base[] = { 333000000, 400000000, 500000000 };
  32 +/* EN7581 */
  33 +static const u32 emi7581_base[] = { 540000000, 480000000, 400000000, 300000000 };
  34 +static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 };
  35 +static const u32 crypto_base[] = { 540000000, 480000000 };
  36
  37  static const struct en_clk_desc en7523_base_clks[] = {
  38         {
  39 @@ -186,6 +191,102 @@ static const struct en_clk_desc en7523_b
  40         }
  41  };
  42
  43 +static const struct en_clk_desc en7581_base_clks[] = {
  44 +       {
  45 +               .id = EN7523_CLK_GSW,
  46 +               .name = "gsw",
  47 +
  48 +               .base_reg = REG_GSW_CLK_DIV_SEL,
  49 +               .base_bits = 1,
  50 +               .base_shift = 8,
  51 +               .base_values = gsw_base,
  52 +               .n_base_values = ARRAY_SIZE(gsw_base),
  53 +
  54 +               .div_bits = 3,
  55 +               .div_shift = 0,
  56 +               .div_step = 1,
  57 +               .div_offset = 1,
  58 +       }, {
  59 +               .id = EN7523_CLK_EMI,
  60 +               .name = "emi",
  61 +
  62 +               .base_reg = REG_EMI_CLK_DIV_SEL,
  63 +               .base_bits = 2,
  64 +               .base_shift = 8,
  65 +               .base_values = emi7581_base,
  66 +               .n_base_values = ARRAY_SIZE(emi7581_base),
  67 +
  68 +               .div_bits = 3,
  69 +               .div_shift = 0,
  70 +               .div_step = 1,
  71 +               .div_offset = 1,
  72 +       }, {
  73 +               .id = EN7523_CLK_BUS,
  74 +               .name = "bus",
  75 +
  76 +               .base_reg = REG_BUS_CLK_DIV_SEL,
  77 +               .base_bits = 1,
  78 +               .base_shift = 8,
  79 +               .base_values = bus_base,
  80 +               .n_base_values = ARRAY_SIZE(bus_base),
  81 +
  82 +               .div_bits = 3,
  83 +               .div_shift = 0,
  84 +               .div_step = 1,
  85 +               .div_offset = 1,
  86 +       }, {
  87 +               .id = EN7523_CLK_SLIC,
  88 +               .name = "slic",
  89 +
  90 +               .base_reg = REG_SPI_CLK_FREQ_SEL,
  91 +               .base_bits = 1,
  92 +               .base_shift = 0,
  93 +               .base_values = slic_base,
  94 +               .n_base_values = ARRAY_SIZE(slic_base),
  95 +
  96 +               .div_reg = REG_SPI_CLK_DIV_SEL,
  97 +               .div_bits = 5,
  98 +               .div_shift = 24,
  99 +               .div_val0 = 20,
 100 +               .div_step = 2,
 101 +       }, {
 102 +               .id = EN7523_CLK_SPI,
 103 +               .name = "spi",
 104 +
 105 +               .base_reg = REG_SPI_CLK_DIV_SEL,
 106 +
 107 +               .base_value = 400000000,
 108 +
 109 +               .div_bits = 5,
 110 +               .div_shift = 8,
 111 +               .div_val0 = 40,
 112 +               .div_step = 2,
 113 +       }, {
 114 +               .id = EN7523_CLK_NPU,
 115 +               .name = "npu",
 116 +
 117 +               .base_reg = REG_NPU_CLK_DIV_SEL,
 118 +               .base_bits = 2,
 119 +               .base_shift = 8,
 120 +               .base_values = npu7581_base,
 121 +               .n_base_values = ARRAY_SIZE(npu7581_base),
 122 +
 123 +               .div_bits = 3,
 124 +               .div_shift = 0,
 125 +               .div_step = 1,
 126 +               .div_offset = 1,
 127 +       }, {
 128 +               .id = EN7523_CLK_CRYPTO,
 129 +               .name = "crypto",
 130 +
 131 +               .base_reg = REG_CRYPTO_CLKSRC2,
 132 +               .base_bits = 1,
 133 +               .base_shift = 0,
 134 +               .base_values = crypto_base,
 135 +               .n_base_values = ARRAY_SIZE(crypto_base),
 136 +       }
 137 +};
 138 +
 139  static const u16 en7581_rst_ofs[] = {
 140         REG_RST_CTRL2,
 141         REG_RST_CTRL1,
 142 @@ -457,8 +558,8 @@ static void en7581_register_clocks(struc
 143         u32 rate;
 144         int i;
 145
 146 -       for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) {
 147 -               const struct en_clk_desc *desc = &en7523_base_clks[i];
 148 +       for (i = 0; i < ARRAY_SIZE(en7581_base_clks); i++) {
 149 +               const struct en_clk_desc *desc = &en7581_base_clks[i];
 150                 u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg;
 151                 int err;
 152