git.ipfire.org Git - thirdparty/kernel/stable-queue.git/blob

   1 From e05237f9da42ee52e73acea0bb082d788e111229 Mon Sep 17 00:00:00 2001
   2 From: Marc Kleine-Budde <mkl@pengutronix.de>
   3 Date: Fri, 9 Nov 2018 15:01:50 +0100
   4 Subject: can: flexcan: remove not needed struct flexcan_priv::tx_mb and struct flexcan_priv::tx_mb_idx
   5
   6 From: Marc Kleine-Budde <mkl@pengutronix.de>
   7
   8 commit e05237f9da42ee52e73acea0bb082d788e111229 upstream.
   9
  10 The previous patch changes the TX path to always use the last mailbox
  11 regardless of the used offload scheme (rx-fifo or timestamp based). This
  12 means members "tx_mb" and "tx_mb_idx" of the struct flexcan_priv don't
  13 depend on the offload scheme, so replace them by compile time constants.
  14
  15 Cc: linux-stable <stable@vger.kernel.org>
  16 Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
  17 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  18
  19 ---
  20  drivers/net/can/flexcan.c |   27 ++++++++++++---------------
  21  1 file changed, 12 insertions(+), 15 deletions(-)
  22
  23 --- a/drivers/net/can/flexcan.c
  24 +++ b/drivers/net/can/flexcan.c
  25 @@ -258,9 +258,7 @@ struct flexcan_priv {
  26         struct can_rx_offload offload;
  27
  28         struct flexcan_regs __iomem *regs;
  29 -       struct flexcan_mb __iomem *tx_mb;
  30         struct flexcan_mb __iomem *tx_mb_reserved;
  31 -       u8 tx_mb_idx;
  32         u32 reg_ctrl_default;
  33         u32 reg_imask1_default;
  34         u32 reg_imask2_default;
  35 @@ -514,6 +512,7 @@ static int flexcan_get_berr_counter(cons
  36  static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
  37  {
  38         const struct flexcan_priv *priv = netdev_priv(dev);
  39 +       struct flexcan_regs __iomem *regs = priv->regs;
  40         struct can_frame *cf = (struct can_frame *)skb->data;
  41         u32 can_id;
  42         u32 data;
  43 @@ -536,17 +535,17 @@ static netdev_tx_t flexcan_start_xmit(st
  44
  45         if (cf->can_dlc > 0) {
  46                 data = be32_to_cpup((__be32 *)&cf->data[0]);
  47 -               priv->write(data, &priv->tx_mb->data[0]);
  48 +               priv->write(data, &regs->mb[FLEXCAN_TX_MB].data[0]);
  49         }
  50         if (cf->can_dlc > 4) {
  51                 data = be32_to_cpup((__be32 *)&cf->data[4]);
  52 -               priv->write(data, &priv->tx_mb->data[1]);
  53 +               priv->write(data, &regs->mb[FLEXCAN_TX_MB].data[1]);
  54         }
  55
  56         can_put_echo_skb(skb, dev, 0);
  57
  58 -       priv->write(can_id, &priv->tx_mb->can_id);
  59 -       priv->write(ctrl, &priv->tx_mb->can_ctrl);
  60 +       priv->write(can_id, &regs->mb[FLEXCAN_TX_MB].can_id);
  61 +       priv->write(ctrl, &regs->mb[FLEXCAN_TX_MB].can_ctrl);
  62
  63         /* Errata ERR005829 step8:
  64          * Write twice INACTIVE(0x8) code to first MB.
  65 @@ -745,7 +744,7 @@ static inline u64 flexcan_read_reg_iflag
  66         u32 iflag1, iflag2;
  67
  68         iflag2 = priv->read(&regs->iflag2) & priv->reg_imask2_default &
  69 -               ~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
  70 +               ~FLEXCAN_IFLAG_MB(FLEXCAN_TX_MB);
  71         iflag1 = priv->read(&regs->iflag1) & priv->reg_imask1_default;
  72
  73         return (u64)iflag2 << 32 | iflag1;
  74 @@ -795,7 +794,7 @@ static irqreturn_t flexcan_irq(int irq,
  75         reg_iflag2 = priv->read(&regs->iflag2);
  76
  77         /* transmission complete interrupt */
  78 -       if (reg_iflag2 & FLEXCAN_IFLAG_MB(priv->tx_mb_idx)) {
  79 +       if (reg_iflag2 & FLEXCAN_IFLAG_MB(FLEXCAN_TX_MB)) {
  80                 u32 reg_ctrl = priv->read(&regs->mb[FLEXCAN_TX_MB].can_ctrl);
  81
  82                 handled = IRQ_HANDLED;
  83 @@ -806,8 +805,8 @@ static irqreturn_t flexcan_irq(int irq,
  84
  85                 /* after sending a RTR frame MB is in RX mode */
  86                 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
  87 -                           &priv->tx_mb->can_ctrl);
  88 -               priv->write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), &regs->iflag2);
  89 +                           &regs->mb[FLEXCAN_TX_MB].can_ctrl);
  90 +               priv->write(FLEXCAN_IFLAG_MB(FLEXCAN_TX_MB), &regs->iflag2);
  91                 netif_wake_queue(dev);
  92         }
  93
  94 @@ -949,7 +948,7 @@ static int flexcan_chip_start(struct net
  95         reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
  96         reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
  97                 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_IRMQ |
  98 -               FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
  99 +               FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(FLEXCAN_TX_MB);
 100
 101         if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
 102                 reg_mcr &= ~FLEXCAN_MCR_FEN;
 103 @@ -1017,7 +1016,7 @@ static int flexcan_chip_start(struct net
 104
 105         /* mark TX mailbox as INACTIVE */
 106         priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 107 -                   &priv->tx_mb->can_ctrl);
 108 +                   &regs->mb[FLEXCAN_TX_MB].can_ctrl);
 109
 110         /* acceptance mask/acceptance code (accept everything) */
 111         priv->write(0x0, &regs->rxgmask);
 112 @@ -1376,11 +1375,9 @@ static int flexcan_probe(struct platform
 113                 priv->tx_mb_reserved = &regs->mb[FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP];
 114         else
 115                 priv->tx_mb_reserved = &regs->mb[FLEXCAN_TX_MB_RESERVED_OFF_FIFO];
 116 -       priv->tx_mb_idx = FLEXCAN_TX_MB;
 117 -       priv->tx_mb = &regs->mb[priv->tx_mb_idx];
 118
 119         priv->reg_imask1_default = 0;
 120 -       priv->reg_imask2_default = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
 121 +       priv->reg_imask2_default = FLEXCAN_IFLAG_MB(FLEXCAN_TX_MB);
 122
 123         priv->offload.mailbox_read = flexcan_mailbox_read;
 124