git.ipfire.org Git - thirdparty/kernel/stable-queue.git/blob

   1 From cdf357f1e13a08a11261edacb3083746f65c1ed9 Mon Sep 17 00:00:00 2001
   2 From: Will Deacon <will.deacon@arm.com>
   3 Date: Thu, 5 Aug 2010 11:20:51 +0100
   4 Subject: ARM: 6299/1: errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID
   5
   6 From: Will Deacon <will.deacon@arm.com>
   7
   8 commit cdf357f1e13a08a11261edacb3083746f65c1ed9 upstream.
   9
  10 On versions of the Cortex-A9 prior to r2p0, performing TLB invalidations by
  11 ASID match can result in the incorrect ASID being broadcast to other CPUs.
  12 As a consequence of this, the targetted TLB entries are not invalidated
  13 across the system.
  14
  15 This workaround changes the TLB flushing routines to invalidate entries
  16 regardless of the ASID.
  17
  18 Tested-by: Rob Clark <rob@ti.com>
  19 Acked-by: Catalin Marinas <catalin.marinas@arm.com>
  20 Signed-off-by: Will Deacon <will.deacon@arm.com>
  21 Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
  22 Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
  23
  24 ---
  25  arch/arm/Kconfig                |   12 ++++++++++++
  26  arch/arm/include/asm/tlbflush.h |    8 ++++++++
  27  2 files changed, 20 insertions(+)
  28
  29 --- a/arch/arm/Kconfig
  30 +++ b/arch/arm/Kconfig
  31 @@ -887,6 +887,18 @@ config ARM_ERRATA_460075
  32           ACTLR register. Note that setting specific bits in the ACTLR register
  33           may not be available in non-secure mode.
  34
  35 +config ARM_ERRATA_720789
  36 +       bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
  37 +       depends on CPU_V7 && SMP
  38 +       help
  39 +         This option enables the workaround for the 720789 Cortex-A9 (prior to
  40 +         r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
  41 +         broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
  42 +         As a consequence of this erratum, some TLB entries which should be
  43 +         invalidated are not, resulting in an incoherency in the system page
  44 +         tables. The workaround changes the TLB flushing routines to invalidate
  45 +         entries regardless of the ASID.
  46 +
  47  endmenu
  48
  49  source "arch/arm/common/Kconfig"
  50 --- a/arch/arm/include/asm/tlbflush.h
  51 +++ b/arch/arm/include/asm/tlbflush.h
  52 @@ -369,7 +369,11 @@ static inline void local_flush_tlb_mm(st
  53         if (tlb_flag(TLB_V6_I_ASID))
  54                 asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
  55         if (tlb_flag(TLB_V7_UIS_ASID))
  56 +#ifdef CONFIG_ARM_ERRATA_720789
  57 +               asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc");
  58 +#else
  59                 asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc");
  60 +#endif
  61
  62         if (tlb_flag(TLB_BTB)) {
  63                 /* flush the branch target cache */
  64 @@ -409,7 +413,11 @@ local_flush_tlb_page(struct vm_area_stru
  65         if (tlb_flag(TLB_V6_I_PAGE))
  66                 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
  67         if (tlb_flag(TLB_V7_UIS_PAGE))
  68 +#ifdef CONFIG_ARM_ERRATA_720789
  69 +               asm("mcr p15, 0, %0, c8, c3, 3" : : "r" (uaddr & PAGE_MASK) : "cc");
  70 +#else
  71                 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc");
  72 +#endif
  73
  74         if (tlb_flag(TLB_BTB)) {
  75                 /* flush the branch target cache */